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| author |   Xavier Simonart <xavier.simonart@intel.com> | 2019-03-08 13:32:53 +0100 |
|---|---|---|
| committer | Xavier Simonart <xavier.simonart@intel.com> | 2019-03-08 13:32:53 +0100 |
| commit | 3d17d9c7e0daae0b82973283a23f3e85d0decabd (patch) | |
| tree | f857a5bd7783e1942b70802658173a38d18d9059 /patches | |
| parent | d813669721c37f0dcbb8f12b950cde7362265c50 (diff) | |
Fix PROX generator latency
When PROX fails to transmit packets (e.g. because switch or NIC
is overloaded) some cleanup needs to be done related to packet id
and latency.
In addition, in some casesi, the clock estimate is slighly over-estimated
which might result, in rare cases, in negative (hence very high) latencies,
due to the extrapolation of timestamps.
This has been workarounded bydecreasing the extrapolation, tolerating up to 1%
clock estimate error
Change-Id: I1ba17dfe0d5e2f9f9167f4f087ed0d96da1293c2
Signed-off-by: Xavier Simonart <xavier.simonart@intel.com>
Diffstat (limited to 'patches')
0 files changed, 0 insertions, 0 deletions