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| author |   Xavier Simonart <xavier.simonart@intel.com> | 2020-05-10 21:04:08 +0200 |
|---|---|---|
| committer | Xavier Simonart <xavier.simonart@intel.com> | 2020-05-29 23:34:46 +0200 |
| commit | 1614130d60abfaa89a41ba8eed5f9bbf41d9a4f4 (patch) | |
| tree | a25af2c624a87aa850faa38a663f4554b0d498c7 /common/VIL/pipeline_loadb | |
| parent | 08fee9c5d2e1d1f3fe14d00683c2a4b7a17e7876 (diff) | |
Improve performance in l3 submode
Two cases where performance has been improved
- When using a gateway from a routing table (l3 submode),
store the mac within the next hop table, to avoid a hash_lookup.
This gives ~10% improvement.
- Read tsc only once per bulk (of up to 64 packets).
This gives ~10% improvement to swap, 4% to gen.
In addition a small fix has been added, preventig "No route" Error
to be written too aften.
Change-Id: I8a7ab74a32f09c8ff47f751ee91e84afee1b2147
Signed-off-by: Xavier Simonart <xavier.simonart@intel.com>
Diffstat (limited to 'common/VIL/pipeline_loadb')
0 files changed, 0 insertions, 0 deletions