Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

4 files changed, 0 insertions, 241 deletions

diff --git a/qemu/roms/u-boot/board/xes/xpedite517x/Makefile b/qemu/roms/u-boot/board/xes/xpedite517x/Makefile
deleted file mode 100644
index d88c3d4b9..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite517x/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= xpedite517x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
diff --git a/qemu/roms/u-boot/board/xes/xpedite517x/ddr.c b/qemu/roms/u-boot/board/xes/xpedite517x/ddr.c
deleted file mode 100644
index fd602ea7e..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite517x/ddr.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork.  These are:
- *   1.) CPO (Read Capture Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths and
- *                   chip-specific internal delays.
- *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths.
- *                   Unless clock and DQ lanes are very different
- *                   lengths (>2"), this should be set to the nominal value
- *                   of 1/2 clock delay.
- *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *           - DDR_SDRAM_CLK_CNTL register
- *           Source: Signal Integrity Simulations
- *   4.) 2T Timing on Addr/Ctl
- *           - TIMING_CFG_2 register
- *           Source: Signal Integrity Simulations
- *           Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     PCB routing on the XPedite5170 is nearly identical to the XPedite5370
- *     so we use the XPedite5370 settings as a basis for the XPedite5170.
- */
-
-typedef struct board_memctl_options {
-	uint16_t datarate_mhz_low;
-	uint16_t datarate_mhz_high;
-	uint8_t clk_adjust;
-	uint8_t cpo_override;
-	uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 9,
-			.write_data_delay	= 2,
-		},
-	},
-	{
-		/* Controller 1 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 7,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			dimm_params_t *pdimm,
-			unsigned int ctrl_num)
-{
-	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
-	sys_info_t sysinfo;
-	int i;
-	unsigned int datarate;
-
-	get_sys_info(&sysinfo);
-	datarate = get_ddr_freq(0) / 1000000;
-
-	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
-		if ((bopts[i].datarate_mhz_low <= datarate) &&
-		    (bopts[i].datarate_mhz_high >= datarate)) {
-			debug("controller %d:\n", ctrl_num);
-			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
-			debug(" cpo = %d\n", bopts[i].cpo_override);
-			debug(" write_data_delay = %d\n",
-				bopts[i].write_data_delay);
-			popts->clk_adjust = bopts[i].clk_adjust;
-			popts->cpo_override = bopts[i].cpo_override;
-			popts->write_data_delay = bopts[i].write_data_delay;
-		}
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/qemu/roms/u-boot/board/xes/xpedite517x/law.c b/qemu/roms/u-boot/board/xes/xpedite517x/law.c
deleted file mode 100644
index 2aad5d256..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite517x/law.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE
-	/* NAND LAW covers 2 NAND flashes */
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/qemu/roms/u-boot/board/xes/xpedite517x/xpedite517x.c b/qemu/roms/u-boot/board/xes/xpedite517x/xpedite517x.c
deleted file mode 100644
index b7ad34950..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite517x/xpedite517x.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-#include "../common/fsl_8xxx_misc.h"
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
-extern void ft_board_pci_setup(void *blob, bd_t *bd);
-#endif
-
-/*
- * Print out which flash was booted from and if booting from the 2nd flash,
- * swap flash chip selects to maintain consistent flash numbering/addresses.
- */
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	phys_size_t dram_size = fsl_ddr_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/* Initialize and enable DDR ECC */
-	ddr_enable_ecc(dram_size);
-#endif
-
-	return dram_size;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-}
-#endif