Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

4 files changed, 0 insertions, 363 deletions

diff --git a/qemu/roms/u-boot/board/ti/dra7xx/Makefile b/qemu/roms/u-boot/board/ti/dra7xx/Makefile
deleted file mode 100644
index 434e8d128..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2013
-# Texas Instruments, <www.ti.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= evm.o
diff --git a/qemu/roms/u-boot/board/ti/dra7xx/README b/qemu/roms/u-boot/board/ti/dra7xx/README
deleted file mode 100644
index 533da01a3..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/README
+++ /dev/null
@@ -1,26 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'dra7xx_evm' build and some
-related uses.
-
-eMMC boot partition use
-=======================
-
-It is possible, depending on SYSBOOT configuration to boot from the eMMC
-boot partitions using (name depending on documentation referenced)
-Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
-example we load MLO and u-boot.img from the build into DDR and then use
-'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
-set boot0 as the boot device.
-U-Boot # setenv autoload no
-U-Boot # usb start
-U-Boot # dhcp
-U-Boot # mmc dev 1 1
-U-Boot # tftp ${loadaddr} dra7xx/MLO
-U-Boot # mmc write ${loadaddr} 0 100
-U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
-U-Boot # mmc write ${loadaddr} 300 400
-U-Boot # mmc bootbus 1 2 0 2
-U-Boot # mmc partconf 1 1 1 0
-U-Boot # mmc rst-function 1 1
diff --git a/qemu/roms/u-boot/board/ti/dra7xx/evm.c b/qemu/roms/u-boot/board/ti/dra7xx/evm.c
deleted file mode 100644
index 073d15127..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/evm.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- * Based on previous work by:
- * Aneesh V       <aneesh@ti.com>
- * Steve Sakoman  <steve@sakoman.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <palmas.h>
-#include <sata.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sata.h>
-#include <environment.h>
-
-#include "mux_data.h"
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-#include <cpsw.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
-	"Board: DRA7xx\n"
-};
-
-/*
- * Adjust I/O delays on the Tx control and data lines of each MAC port. This
- * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
- * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
- * essentially need to counteract the DRA7xx internal delay, and we do this
- * by delaying the control and data lines. If not using this PHY, you probably
- * don't need to do this stuff!
- */
-static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
-{
-	int i = 0;
-	u32 reg_val;
-	u32 delta;
-	u32 coarse;
-	u32 fine;
-
-	writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
-
-	while(io_dly[i].addr) {
-		writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
-		       io_dly[i].addr);
-		delta = io_dly[i].dly;
-		reg_val = readl(io_dly[i].addr) & 0x3ff;
-		coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
-		coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
-		fine = (reg_val & 0x1F) + (delta & 0x1F);
-		fine = (fine > 0x1F) ? (0x1F) : (fine);
-		reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
-				CFG_IO_DELAY_LOCK_MASK |
-				((coarse << 5) | (fine));
-		writel(reg_val, io_dly[i].addr);
-		i++;
-	}
-
-	writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
-}
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
-	gpmc_init();
-	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-	init_sata(0);
-	return 0;
-}
-
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
-	return 0;
-}
-
-static void do_set_mux32(u32 base,
-			 struct pad_conf_entry const *array, int size)
-{
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
-	for (i = 0; i < size; i++, pad++)
-		writel(pad->val, base + pad->offset);
-}
-
-void set_muxconf_regs_essential(void)
-{
-	do_set_mux32((*ctrl)->control_padconf_core_base,
-		     core_padconf_array_essential,
-		     sizeof(core_padconf_array_essential) /
-		     sizeof(struct pad_conf_entry));
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
-	omap_mmc_init(0, 0, 0, -1, -1);
-	omap_mmc_init(1, 0, 0, -1, -1);
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
-int spl_start_uboot(void)
-{
-	/* break into full u-boot on 'c' */
-	if (serial_tstc() && serial_getc() == 'c')
-		return 1;
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
-	env_init();
-	env_relocate_spec();
-	if (getenv_yesno("boot_os") != 1)
-		return 1;
-#endif
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-/* Delay value to add to calibrated value */
-#define RGMII0_TXCTL_DLY_VAL		((0x3 << 5) + 0x8)
-#define RGMII0_TXD0_DLY_VAL		((0x3 << 5) + 0x8)
-#define RGMII0_TXD1_DLY_VAL		((0x3 << 5) + 0x2)
-#define RGMII0_TXD2_DLY_VAL		((0x4 << 5) + 0x0)
-#define RGMII0_TXD3_DLY_VAL		((0x4 << 5) + 0x0)
-#define VIN2A_D13_DLY_VAL		((0x3 << 5) + 0x8)
-#define VIN2A_D17_DLY_VAL		((0x3 << 5) + 0x8)
-#define VIN2A_D16_DLY_VAL		((0x3 << 5) + 0x2)
-#define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
-#define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)
-
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 2,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_addr	= 3,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-	uint32_t ctrl_val;
-	const struct io_delay io_dly[] = {
-		{CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
-		{CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
-		{CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
-		{CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
-		{CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
-		{CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
-		{CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
-		{CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
-		{CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
-		{CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
-		{0}
-	};
-
-	/* Adjust IO delay for RGMII tx path */
-	dra7xx_adj_io_delay(io_dly);
-
-	/* try reading mac address from efuse */
-	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
-	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
-	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
-	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-	mac_addr[2] = mac_hi & 0xFF;
-	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
-	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
-	mac_addr[5] = mac_lo & 0xFF;
-
-	if (!getenv("ethaddr")) {
-		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
-		if (is_valid_ether_addr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-
-	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
-	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
-	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
-	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-	mac_addr[2] = mac_hi & 0xFF;
-	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
-	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
-	mac_addr[5] = mac_lo & 0xFF;
-
-	if (!getenv("eth1addr")) {
-		if (is_valid_ether_addr(mac_addr))
-			eth_setenv_enetaddr("eth1addr", mac_addr);
-	}
-
-	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
-	ctrl_val |= 0x22;
-	writel(ctrl_val, (*ctrl)->control_core_control_io1);
-
-	ret = cpsw_register(&cpsw_data);
-	if (ret < 0)
-		printf("Error %d registering CPSW switch\n", ret);
-
-	return ret;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/dra7xx/mux_data.h b/qemu/roms/u-boot/board/ti/dra7xx/mux_data.h
deleted file mode 100644
index 38de9d5a8..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/mux_data.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Sricharan R	<r.sricharan@ti.com>
- * Nishant Kamat <nskamat@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _MUX_DATA_DRA7XX_H_
-#define _MUX_DATA_DRA7XX_H_
-
-#include <asm/arch/mux_dra7xx.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-	{MMC1_CLK, (IEN | PTU | PDIS | M0)},	/* MMC1_CLK */
-	{MMC1_CMD, (IEN | PTU | PDIS | M0)},	/* MMC1_CMD */
-	{MMC1_DAT0, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT0 */
-	{MMC1_DAT1, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT1 */
-	{MMC1_DAT2, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT2 */
-	{MMC1_DAT3, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT3 */
-	{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
-	{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
-	{GPMC_A19, (IEN | PTU | PDIS | M1)},	/* mmc2_dat4 */
-	{GPMC_A20, (IEN | PTU | PDIS | M1)},	/* mmc2_dat5 */
-	{GPMC_A21, (IEN | PTU | PDIS | M1)},	/* mmc2_dat6 */
-	{GPMC_A22, (IEN | PTU | PDIS | M1)},	/* mmc2_dat7 */
-	{GPMC_A23, (IEN | PTU | PDIS | M1)},	/* mmc2_clk */
-	{GPMC_A24, (IEN | PTU | PDIS | M1)},	/* mmc2_dat0 */
-	{GPMC_A25, (IEN | PTU | PDIS | M1)},	/* mmc2_dat1 */
-	{GPMC_A26, (IEN | PTU | PDIS | M1)},	/* mmc2_dat2 */
-	{GPMC_A27, (IEN | PTU | PDIS | M1)},	/* mmc2_dat3 */
-	{GPMC_CS1, (IEN | PTU | PDIS | M1)},	/* mmm2_cmd */
-	{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
-	{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
-	{UART1_CTSN, (IEN | PTU | PDIS | M3)},	/* UART1_CTSN */
-	{UART1_RTSN, (IEN | PTU | PDIS | M3)},	/* UART1_RTSN */
-	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
-	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
-	{MDIO_MCLK, (PTU | PEN | M0)},		/* MDIO_MCLK  */
-	{MDIO_D, (IEN | PTU | PEN | M0)},	/* MDIO_D  */
-	{RGMII0_TXC, (M0) },
-	{RGMII0_TXCTL, (M0) },
-	{RGMII0_TXD3, (M0) },
-	{RGMII0_TXD2, (M0) },
-	{RGMII0_TXD1, (M0) },
-	{RGMII0_TXD0, (M0) },
-	{RGMII0_RXC, (IEN | M0) },
-	{RGMII0_RXCTL, (IEN | M0) },
-	{RGMII0_RXD3, (IEN | M0) },
-	{RGMII0_RXD2, (IEN | M0) },
-	{RGMII0_RXD1, (IEN | M0) },
-	{RGMII0_RXD0, (IEN | M0) },
-	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
-	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
-	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
-	{GPMC_A16, (IEN | PDIS | M1)},  /* QSPI1_D[1] */
-	{GPMC_A17, (IEN | PDIS | M1)},  /* QSPI1_D[0] */
-	{GPMC_A18, (M1)},  /* QSPI1_SCLK */
-	{GPMC_A3, (IEN | PDIS | M1)},   /* QSPI1_CS2 */
-	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
-	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
-	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
-	{USB2_DRVVBUS, (M0 | IEN | FSC) },
-};
-#endif /* _MUX_DATA_DRA7XX_H_ */