| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2019-02-07 | Update Intel Copyright for files edited in 2019 |   John O Loughlin | 1 | -1/+1 | |
| JIRA: YARDSTICK-1591 Change-Id: I3ea9039d25bfce578681adb9e27e1598e84a1f56 Signed-off-by: John O Loughlin <john.oloughlin@intel.com> | |||||
| 2019-02-04 | Support NSB NFVi buffering and Load Balance on 2 and 4 ports |   DanielMartinBuckley | 1 | -0/+114 | |
| JIRA: YARDSTICK-1582 Most use cases support 4 ports. Buffering support only 1 core. Request is about supporting buffering & Load balance for 2 and 4 ports Change-Id: I734f9d6702825b31253a21092c86fc72e367586b Signed-off-by: Daniel Martin Buckley <daniel.m.buckley@intel.com> | |||||
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index : yardstick | |
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