Support NSB NFVi buffering and Load Balance on 2 and 4 ports

JIRA: YARDSTICK-1582

Most use cases support 4 ports.
Buffering support only 1 core.
Request is about supporting buffering & Load balance
for 2 and 4 ports

Change-Id: I734f9d6702825b31253a21092c86fc72e367586b
Signed-off-by: Daniel Martin Buckley <daniel.m.buckley@intel.com>

1 files changed, 29 insertions, 6 deletions

diff --git a/samples/vnf_samples/nsut/prox/configs/handle_lb-4.cfg b/samples/vnf_samples/nsut/prox/configs/handle_lb-4.cfg
index b85e00b5c..233a88522 100644
--- a/samples/vnf_samples/nsut/prox/configs/handle_lb-4.cfg
+++ b/samples/vnf_samples/nsut/prox/configs/handle_lb-4.cfg
@@ -50,13 +50,12 @@ tx desc=2048
 promiscuous=yes
 
 [defaults]
-mempool size=13K
 memcache size=512
 mempool size=16K
 
 [global]
 start time=5
-name=Handle 5 Tuple Load Balance 1-to-4
+name=Handle 5 Tuple Load Balance
 
 [core 0]
 mode=master
@@ -66,10 +65,34 @@ name=Handle_LB
 task=0
 mode=lb5tuple
 rx port=if0
-tx cores=2,3,4,5
+tx cores=5,6,7,8
 drop=no
 
 [core 2]
+name=Handle_LB
+task=0
+mode=lb5tuple
+rx port=if1
+tx cores=5,6,7,8
+drop=no
+
+[core 3]
+name=Handle_LB
+task=0
+mode=lb5tuple
+rx port=if2
+tx cores=5,6,7,8
+drop=no
+
+[core 4]
+name=Handle_LB
+task=0
+mode=lb5tuple
+rx port=if3
+tx cores=5,6,7,8
+drop=no
+
+[core 5]
 name=TX_p0
 task=0
 mode=l2fwd
@@ -78,7 +101,7 @@ rx ring=yes
 tx port=if0
 drop=no
 
-[core 3]
+[core 6]
 name=TX_p1
 task=0
 mode=l2fwd
@@ -87,7 +110,7 @@ rx ring=yes
 tx port=if1
 drop=no
 
-[core 4]
+[core 7]
 name=TX_p2
 task=0
 mode=l2fwd
@@ -96,7 +119,7 @@ rx ring=yes
 tx port=if2
 drop=no
 
-[core 5]
+[core 8]
 name=TX_p3
 task=0
 mode=l2fwd