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| author |   Abhijit Sinha <abhijit.sinha@intel.com> | 2018-11-07 17:24:46 +0000 |
|---|---|---|
| committer |   Gerrit Code Review <gerrit@opnfv.org> | 2018-11-07 17:24:46 +0000 |
| commit | 372b3225b1ea632a2d889f10a0d853bc2224209c (patch) | |
| tree | 616a92fba82ed47b49158db59ca0b7379a25fe04 /ansible/list_stacks.yml | |
| parent | 9f6f4cc38206b4700e01439f804821bbc7e2aabc (diff) | |
| parent | 465e2c0f2891c5ec194761f5465c10645305243f (diff) | |
Merge "Add prox test case for SRIOV & 4 ports."
Diffstat (limited to 'ansible/list_stacks.yml')
0 files changed, 0 insertions, 0 deletions