blob: 2b5017ebb40984288fe5e8ee1f2cfb9ad9087cc4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
; Copyright (c) 2017 Intel Corporation
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http:#www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
[EAL]
# add pci whitelist eg below
w = 05:00.0
w = 05:00.1
[PIPELINE0]
type = MASTER
core = 0
[PIPELINE1]
type = ARPICMP
core = 1
pktq_in = SWQ2
pktq_out = SWQ7
pktq_in_prv = RXQ0.0
prv_to_pub_map = (0,1)
prv_que_handler = (0)
[PIPELINE2]
type = TXRX
core = 2
pktq_in = RXQ0.0 RXQ1.0
pktq_out = SWQ0 SWQ1 SWQ2
pipeline_txrx_type = RXRX
dest_if_offset=176
[PIPELINE3]
type = LOADB
core = 3
pktq_in = SWQ0 SWQ1
pktq_out = SWQ3 SWQ4
outport_offset = 136
phyport_offset = 204
n_vnf_threads = 1
prv_que_handler = (0)
[PIPELINE4]
type = ACL
core = 4
pktq_in = SWQ3 SWQ4
pktq_out = SWQ5 SWQ6
n_flows = 1000000
pkt_type = ipv6
traffic_type = 6
[PIPELINE5]
type = TXRX
core = 5
pktq_in = SWQ5 SWQ6 SWQ7
pktq_out = TXQ0.0 TXQ1.0
pipeline_txrx_type = TXTX
|
