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;;
;; Copyright (c) 2010-2017 Intel Corporation
;;
;; Licensed under the Apache License, Version 2.0 (the "License");
;; you may not use this file except in compliance with the License.
;; You may obtain a copy of the License at
;;
;; http://www.apache.org/licenses/LICENSE-2.0
;;
;; Unless required by applicable law or agreed to in writing, software
;; distributed under the License is distributed on an "AS IS" BASIS,
;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;; See the License for the specific language governing permissions and
;; limitations under the License.
;;
[eal options]
-n=4 ; force number of memory channels
no-output=no ; disable DPDK debug output
[port 0]
name=p0
mac=00:00:00:00:00:01
[port 1]
name=p1
mac=00:00:00:00:00:02
[port 2]
name=p2
mac=00:00:00:00:00:03
[port 3]
name=p3
mac=00:00:00:00:00:04
[defaults]
mempool size=4K
[global]
start time=5
name=Basic Gen
[core 0s0]
mode=master
[core 1s0]
name=p0
task=0
mode=gen
tx port=p0
bps=1250000000
pkt inline=00 00 01 00 00 01 00 00 02 00 00 02 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
[core 2s0]
name=p1
task=0
mode=gen
tx port=p1
bps=1250000000
pkt inline=00 00 01 00 00 01 00 00 02 00 00 02 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
[core 3s0]
name=p2
task=0
mode=gen
tx port=p2
bps=1250000000
pkt inline=00 00 01 00 00 01 00 00 02 00 00 02 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
[core 4s0]
name=p3
task=0
mode=gen
tx port=p3
bps=1250000000
pkt inline=00 00 01 00 00 01 00 00 02 00 00 02 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
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