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| author |   Anand B Jyoti <anand.b.jyoti@intel.com> | 2017-06-26 05:31:13 +0530 |
|---|---|---|
| committer | Anand B Jyoti <anand.b.jyoti@intel.com> | 2017-06-26 05:31:13 +0530 |
| commit | 18acbcb75fcd0dd276da9d3022aaf6cb25999e1c (patch) | |
| tree | ec9e97f02e9cac9f44fbc9ebf3319d9dec664056 /common/VIL/l2l3_stack/tsx.c | |
| parent | e65864efce7da482bc9f337189de5f8c49df5091 (diff) | |
dpdk: Disable debug logs in ACL rte_table_acl_build
JIRA: SAMPLEVNF-46
Debug logs enabled by default causes delay in application initialization
as there can be many ACL rules to be setup during initialization.
This patch disables the ACL logs during rte_table_acl_build by default
and can be enabled by setting the RTE_LOG_LEVEL to DEBUG.
Change-Id: I48e642f8768135087b0ed4f1677c1c9ac9e0df58
Signed-off-by: Anand B Jyoti <anand.b.jyoti@intel.com>
Diffstat (limited to 'common/VIL/l2l3_stack/tsx.c')
0 files changed, 0 insertions, 0 deletions