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authorYujun Zhang <zhang.yujunz@zte.com.cn>2016-11-04 13:40:05 +0800
committerYujun Zhang <zhang.yujunz@zte.com.cn>2016-11-07 15:42:23 +0800
commit9aa19e5f0eac7aeedd539d2705670fb2fc7ad1af (patch)
tree4de0a329e3ef3f5fe50e1a86260c8fe935e6b8a7
parentc7761e0760aaacb801478308b6774dccb33cbf2e (diff)
Add spec for time line diagram
Change-Id: Ib3f5697f5afee294a469979bc66244f054edb1fd Signed-off-by: Yujun Zhang <zhang.yujunz@zte.com.cn>
-rw-r--r--docs/designspec/dashboard.rst16
1 files changed, 16 insertions, 0 deletions
diff --git a/docs/designspec/dashboard.rst b/docs/designspec/dashboard.rst
index 555b3a24..60c4720d 100644
--- a/docs/designspec/dashboard.rst
+++ b/docs/designspec/dashboard.rst
@@ -133,3 +133,19 @@ A draft design is as following::
| HIDE COMMON|
+------------+
+Time line
+---------
+
+Time line diagram for analysis of time critical performance test::
+
+ +-----------------+-----------+-------------+-------------+-----+
+ | | | | | |
+ +-----------------> | | | |
+ | +-----------> | | |
+ | ? ms +-------------> | |
+ | ? ms +------------>+ |
+ | ? ms ? ms |
+ | |
+ +---------------------------------------------------------------+
+
+The time cost between checkpoints shall be displayed in the diagram.