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/*
* Copyright (C) 2013 Boundary Devices
* Copyright (C) 2013 SolidRun ltd.
* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ZQ Calibrations */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
/* write leveling */
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
/*
* DQS gating, read delay, write delay calibration values
* based on calibration compare of 0x00ffff00
*/
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
/* read data bit delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
/* Complete calibration by forced measurement */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/*
* MMDC init:
* in DDR3, 32-bit mode, only MMDC0 is initiated:
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
/* CS0_END - 0x2fffffff, 512M */
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
DATA 4, 0x021b0400, 0x11420000
/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
/*
* Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
* MR2
*/
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
/* MR3 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
/* MR1 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
/* MR0 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
/* ZQ calibration */
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
/* final DDR setup */
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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