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/*
 * linux/include/linux/timecounter.h
 *
 * based on code that migrated away from
 * linux/include/linux/clocksource.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#ifndef _LINUX_TIMECOUNTER_H
#define _LINUX_TIMECOUNTER_H

#include <linux/types.h>

/* simplify initialization of mask field */
#define CYCLECOUNTER_MASK(bits) (cycle_t)((bits) < 64 ? ((1ULL<<(bits))-1) : -1)

/**
 * struct cyclecounter - hardware abstraction for a free running counter
 *	Provides completely state-free accessors to the underlying hardware.
 *	Depending on which hardware it reads, the cycle counter may wrap
 *	around quickly. Locking rules (if necessary) have to be defined
 *	by the implementor and user of specific instances of this API.
 *
 * @read:		returns the current cycle value
 * @mask:		bitmask for two's complement
 *			subtraction of non 64 bit counters,
 *			see CYCLECOUNTER_MASK() helper macro
 * @mult:		cycle to nanosecond multiplier
 * @shift:		cycle to nanosecond divisor (power of two)
 */
struct cyclecounter {
	cycle_t (*read)(const struct cyclecounter *cc);
	cycle_t mask;
	u32 mult;
	u32 shift;
};

/**
 * struct timecounter - layer above a %struct cyclecounter which counts nanoseconds
 *	Contains the state needed by timecounter_read() to detect
 *	cycle counter wrap around. Initialize with
 *	timecounter_init(). Also used to convert cycle counts into the
 *	corresponding nanosecond counts with timecounter_cyc2time(). Users
 *	of this code are responsible for initializing the underlying
 *	cycle counter hardware, locking issues and reading the time
 *	more often than the cycle counter wraps around. The nanosecond
 *	counter will only wrap around after ~585 years.
 *
 * @cc:			the cycle counter used by this instance
 * @cycle_last:		most recent cycle counter value seen by
 *			timecounter_read()
 * @nsec:		continuously increasing count
 * @mask:		bit mask for maintaining the 'frac' field
 * @frac:		accumulated fractional nanoseconds
 */
struct timecounter {
	const struct cyclecounter *cc;
	cycle_t cycle_last;
	u64 nsec;
	u64 mask;
	u64 frac;
};

/**
 * cyclecounter_cyc2ns - converts cycle counter cycles to nanoseconds
 * @cc:		Pointer to cycle counter.
 * @cycles:	Cycles
 * @mask:	bit mask for maintaining the 'frac' field
 * @frac:	pointer to storage for the fractional nanoseconds.
 */
static inline u64 cyclecounter_cyc2ns(const struct cyclecounter *cc,
				      cycle_t cycles, u64 mask, u64 *frac)
{
	u64 ns = (u64) cycles;

	ns = (ns * cc->mult) + *frac;
	*frac = ns & mask;
	return ns >> cc->shift;
}

/**
 * timecounter_adjtime - Shifts the time of the clock.
 * @delta:	Desired change in nanoseconds.
 */
static inline void timecounter_adjtime(struct timecounter *tc, s64 delta)
{
	tc->nsec += delta;
}

/**
 * timecounter_init - initialize a time counter
 * @tc:			Pointer to time counter which is to be initialized/reset
 * @cc:			A cycle counter, ready to be used.
 * @start_tstamp:	Arbitrary initial time stamp.
 *
 * After this call the current cycle register (roughly) corresponds to
 * the initial time stamp. Every call to timecounter_read() increments
 * the time stamp counter by the number of elapsed nanoseconds.
 */
extern void timecounter_init(struct timecounter *tc,
			     const struct cyclecounter *cc,
			     u64 start_tstamp);

/**
 * timecounter_read - return nanoseconds elapsed since timecounter_init()
 *                    plus the initial time stamp
 * @tc:          Pointer to time counter.
 *
 * In other words, keeps track of time since the same epoch as
 * the function which generated the initial time stamp.
 */
extern u64 timecounter_read(struct timecounter *tc);

/**
 * timecounter_cyc2time - convert a cycle counter to same
 *                        time base as values returned by
 *                        timecounter_read()
 * @tc:		Pointer to time counter.
 * @cycle_tstamp:	a value returned by tc->cc->read()
 *
 * Cycle counts that are converted correctly as long as they
 * fall into the interval [-1/2 max cycle count, +1/2 max cycle count],
 * with "max cycle count" == cs->mask+1.
 *
 * This allows conversion of cycle counter values which were generated
 * in the past.
 */
extern u64 timecounter_cyc2time(struct timecounter *tc,
				cycle_t cycle_tstamp);

#endif
pan>); rdt_features.rdtm_supported = 1; } else { plog_info("\tDoes not support Intel RDT Monitoring capability\n"); return; } if ((r.ebx >> 15) & 1) { plog_info("\tRDT-A. Supports Intel RDT Allocation capability\n"); rdt_features.rdta_supported = 1; } else { plog_info("\tDoes not support Intel RDT Allocation capability\n"); } cpuid(&r, 0xf, 0x0, 0x0, 0x0); if ((r.edx >> 1) & 1) { plog_info("\tSupports L3 Cache Intel RDT Monitoring\n"); rdt_features.cmt_supported = 1; } plog_info("\tIntel RDT Monitoring has %d maximum RMID\n", r.ebx); rdt_features.rdtm_max_rmid = r.ebx; cpuid(&r, 0xf, 0x0, 0x1, 0x0); if ((r.edx >> 0) & 1) { plog_info("\tSupports L3 occupancy monitoring\n"); rdt_features.cmt_supported = 1; } if ((r.edx >> 1) & 1) { plog_info("\tSupports L3 Total bandwidth monitoring\n"); rdt_features.mbm_tot_supported = 1; } if ((r.edx >> 2) & 1) { plog_info("\tSupports L3 Local bandwidth monitoring\n"); rdt_features.mbm_loc_supported = 1; } rdt_features.cmt_max_rmid = r.ecx; rdt_features.upscaling_factor = r.ebx; rdt_features.event_types = r.edx; plog_info("\tL3 Cache Intel RDT Monitoring Capability has %d maximum RMID\n", r.ecx); plog_info("\tUpscaling_factor = %d\n", rdt_features.upscaling_factor); cpuid(&r, 0x10, 0x0, 0x0, 0x0); if ((r.ebx >> 1) & 1) { plog_info("\tSupports L3 Cache Allocation Technology\n"); rdt_features.l3_cat_supported = 1; } if ((r.ebx >> 2) & 1) { plog_info("\tSupports L2 Cache Allocation Technology\n"); rdt_features.l2_cat_supported = 1; } if ((r.ebx >> 3) & 1) { plog_info("\tSupports MBA Allocation Technology\n"); rdt_features.mba_supported = 1; } cpuid(&r, 0x10, 0x0, 0x1, 0x0); if ((r.ecx >> 2) & 1) plog_info("\tCode and Data Prioritization Technology supported\n"); plog_info("\tL3 Cache Allocation Technology Enumeration Highest COS number = %d\n", r.edx & 0xffff); rdt_features.cat_max_rmid = r.edx & 0xffff; rdt_features.cat_num_ways = r.eax + 1; cpuid(&r, 0x10, 0x0, 0x2, 0x0); plog_info("\tL2 Cache Allocation Technology Enumeration COS number = %d\n", r.edx & 0xffff); cpuid(&r, 0x10, 0x0, 0x3, 0x0); plog_info("\tMemory Bandwidth Allocation Enumeration COS number = %d\n", r.edx & 0xffff); rdt_features.mba_max_rmid = r.ecx; } int mbm_is_supported(void) { return (rdt_features.rdtm_supported && rdt_features.mbm_tot_supported && rdt_features.mbm_loc_supported); } int mba_is_supported(void) { return (rdt_features.rdta_supported && rdt_features.mba_supported); } int cmt_is_supported(void) { if ((rdt_features.rdtm_supported || rdt_features.rdta_supported) && (prox_cfg.flags & DSF_DISABLE_CMT)) { rdt_features.rdtm_supported = rdt_features.rdta_supported = 0; plog_info("cqm and cat features disabled by config file\n"); } return (rdt_features.rdtm_supported && rdt_features.cmt_supported); } int cat_is_supported(void) { if ((rdt_features.rdtm_supported || rdt_features.rdta_supported) && (prox_cfg.flags & DSF_DISABLE_CMT)) { rdt_features.rdtm_supported = rdt_features.rdta_supported = 0; plog_info("cqm and cat features disabled by config file\n"); } return (rdt_features.rdta_supported && rdt_features.l3_cat_supported); } int rdt_is_supported(void) { return (cmt_is_supported() || cat_is_supported()); } int rdt_get_features(struct rdt_features* feat) { if (!cmt_is_supported() && !cat_is_supported()) return 1; *feat = rdt_features; return 0; } int cqm_assoc(uint8_t lcore_id, uint64_t rmid) { uint64_t val = 0; int ret = 0; ret = msr_read(&val, lcore_id, IA32_QM_ASSOC); if (ret != 0) { plog_err("Unable to read msr %x on core %u\n", IA32_QM_ASSOC, lcore_id); } val &= 0x3FFULL; plog_dbg("core %u, rmid was %lu, now setting to %lu\n", lcore_id, val, rmid); val |= (uint64_t)(rmid & 0x3FFULL); ret = msr_write(lcore_id, rmid, IA32_QM_ASSOC); if (ret != 0) { plog_err("Unable to set msr %x on core %u to value %lx\n", IA32_QM_ASSOC, lcore_id, val); } return ret; } int cqm_assoc_read(uint8_t lcore_id, uint64_t *rmid) { return msr_read(rmid, lcore_id, IA32_QM_ASSOC); } void rdt_init_stat_core(uint8_t lcore_id) { stat_core = lcore_id; } /* read a specific rmid value using core 0 */ int cmt_read_ctr(uint64_t* ret, uint64_t rmid, uint8_t lcore_id) { uint64_t event_id = L3_CACHE_OCCUPANCY; uint64_t es = rmid; es = (es << 32) | event_id; if (msr_write(lcore_id, es, IA32_QM_EVTSEL) < 0) { return 1; } if (msr_read(ret, lcore_id, IA32_QM_CTR) < 0) { return 2; } return 0; } int mbm_read_tot_bdw(uint64_t* ret, uint64_t rmid, uint8_t lcore_id) { uint64_t event_id = L3_TOTAL_EXTERNAL_BANDWIDTH; uint64_t es = rmid; es = (es << 32) | event_id; if (msr_write(lcore_id, es, IA32_QM_EVTSEL) < 0) { return 1; } if (msr_read(ret, lcore_id, IA32_QM_CTR) < 0) { return 2; } return 0; } int mbm_read_loc_bdw(uint64_t* ret, uint64_t rmid, uint8_t lcore_id) { uint64_t event_id = L3_LOCAL_EXTERNAL_BANDWIDTH; uint64_t es = rmid; es = (es << 32) | event_id; if (msr_write(lcore_id, es, IA32_QM_EVTSEL) < 0) { return 1; } if (msr_read(ret, lcore_id, IA32_QM_CTR) < 0) { return 2; } return 0; } int cat_log_init(uint8_t lcore_id) { uint64_t tmp_rmid; int rc, i = 0; for (i = 0; i < IA32_QM_L3CA_END - IA32_QM_L3CA_START; i++) { rc = msr_read(&tmp_rmid,lcore_id,IA32_QM_L3CA_START + i); if (rc < 0) { break; } plog_info("\tAt initialization: Cache allocation set %d (msr %x): mask %lx\n", i, IA32_QM_L3CA_START + i, tmp_rmid); } return i; } int cat_set_class_mask(uint8_t lcore_id, uint32_t set, uint32_t mask) { uint64_t tmp_rmid; int rc; rc = msr_write(lcore_id, mask, IA32_QM_L3CA_START + set); if (rc < 0) { plog_err("Failed to write Cache allocation\n"); return -1; } return 0; } int cat_get_class_mask(uint8_t lcore_id, uint32_t set, uint32_t *mask) { uint64_t tmp_rmid; int rc; rc = msr_read(&tmp_rmid,lcore_id,IA32_QM_L3CA_START + set); if (rc < 0) { plog_err("Failed to read Cache allocation\n"); return -1; } *mask = tmp_rmid & 0xffffffff; return 0; } void cat_reset_cache(uint32_t lcore_id) { int rc; uint32_t mask = (1 << rdt_features.cat_num_ways) -1; for (uint32_t set = 0; set <= rdt_features.cat_max_rmid; set++) { rc = msr_write(lcore_id, mask, IA32_QM_L3CA_START + set); if (rc < 0) { plog_err("Failed to reset Cache allocation\n"); } } } int cat_get_num_ways(void) { return rdt_features.cat_num_ways; }