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/*
 *  include/linux/mmc/sd.h
 *
 *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

#ifndef LINUX_MMC_SD_H
#define LINUX_MMC_SD_H

/* SD commands                           type  argument     response */
  /* class 0 */
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR     3   /* bcr                     R6  */
#define SD_SEND_IF_COND           8   /* bcr  [11:0] See below   R7  */
#define SD_SWITCH_VOLTAGE         11  /* ac                      R1  */

  /* class 10 */
#define SD_SWITCH                 6   /* adtc [31:0] See below   R1  */

  /* class 5 */
#define SD_ERASE_WR_BLK_START    32   /* ac   [31:0] data addr   R1  */
#define SD_ERASE_WR_BLK_END      33   /* ac   [31:0] data addr   R1  */

  /* Application commands */
#define SD_APP_SET_BUS_WIDTH      6   /* ac   [1:0] bus width    R1  */
#define SD_APP_SD_STATUS         13   /* adtc                    R1  */
#define SD_APP_SEND_NUM_WR_BLKS  22   /* adtc                    R1  */
#define SD_APP_OP_COND           41   /* bcr  [31:0] OCR         R3  */
#define SD_APP_SEND_SCR          51   /* adtc                    R1  */

/* OCR bit definitions */
#define SD_OCR_S18R		(1 << 24)    /* 1.8V switching request */
#define SD_ROCR_S18A		SD_OCR_S18R  /* 1.8V switching accepted by card */
#define SD_OCR_XPC		(1 << 28)    /* SDXC power control */
#define SD_OCR_CCS		(1 << 30)    /* Card Capacity Status */

/*
 * SD_SWITCH argument format:
 *
 *      [31] Check (0) or switch (1)
 *      [30:24] Reserved (0)
 *      [23:20] Function group 6
 *      [19:16] Function group 5
 *      [15:12] Function group 4
 *      [11:8] Function group 3
 *      [7:4] Function group 2
 *      [3:0] Function group 1
 */

/*
 * SD_SEND_IF_COND argument format:
 *
 *	[31:12] Reserved (0)
 *	[11:8] Host Voltage Supply Flags
 *	[7:0] Check Pattern (0xAA)
 */

/*
 * SCR field definitions
 */

#define SCR_SPEC_VER_0		0	/* Implements system specification 1.0 - 1.01 */
#define SCR_SPEC_VER_1		1	/* Implements system specification 1.10 */
#define SCR_SPEC_VER_2		2	/* Implements system specification 2.00-3.0X */

/*
 * SD bus widths
 */
#define SD_BUS_WIDTH_1		0
#define SD_BUS_WIDTH_4		2

/*
 * SD_SWITCH mode
 */
#define SD_SWITCH_CHECK		0
#define SD_SWITCH_SET		1

/*
 * SD_SWITCH function groups
 */
#define SD_SWITCH_GRP_ACCESS	0

/*
 * SD_SWITCH access modes
 */
#define SD_SWITCH_ACCESS_DEF	0
#define SD_SWITCH_ACCESS_HS	1

#endif /* LINUX_MMC_SD_H */
>cs_rd_off; /* Read deassertion time */ u32 cs_wr_off; /* Write deassertion time */ /* ADV signal timings corresponding to GPMC_CONFIG3 */ u32 adv_on; /* Assertion time */ u32 adv_rd_off; /* Read deassertion time */ u32 adv_wr_off; /* Write deassertion time */ /* WE signals timings corresponding to GPMC_CONFIG4 */ u32 we_on; /* WE assertion time */ u32 we_off; /* WE deassertion time */ /* OE signals timings corresponding to GPMC_CONFIG4 */ u32 oe_on; /* OE assertion time */ u32 oe_off; /* OE deassertion time */ /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ u32 page_burst_access; /* Multiple access word delay */ u32 access; /* Start-cycle to first data valid delay */ u32 rd_cycle; /* Total read cycle time */ u32 wr_cycle; /* Total write cycle time */ u32 bus_turnaround; u32 cycle2cycle_delay; u32 wait_monitoring; u32 clk_activation; /* The following are only on OMAP3430 */ u32 wr_access; /* WRACCESSTIME */ u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */ struct gpmc_bool_timings bool_timings; }; /* Device timings in picoseconds */ struct gpmc_device_timings { u32 t_ceasu; /* address setup to CS valid */ u32 t_avdasu; /* address setup to ADV valid */ /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is * of tusb using these timings even for sync whilst * ideally for adv_rd/(wr)_off it should have considered * t_avdh instead. This indirectly necessitates r/w * variations of t_avdp as it is possible to have one * sync & other async */ u32 t_avdp_r; /* ADV low time (what about t_cer ?) */ u32 t_avdp_w; u32 t_aavdh; /* address hold time */ u32 t_oeasu; /* address setup to OE valid */ u32 t_aa; /* access time from ADV assertion */ u32 t_iaa; /* initial access time */ u32 t_oe; /* access time from OE assertion */ u32 t_ce; /* access time from CS asertion */ u32 t_rd_cycle; /* read cycle time */ u32 t_cez_r; /* read CS deassertion to high Z */ u32 t_cez_w; /* write CS deassertion to high Z */ u32 t_oez; /* OE deassertion to high Z */ u32 t_weasu; /* address setup to WE valid */ u32 t_wpl; /* write assertion time */ u32 t_wph; /* write deassertion time */ u32 t_wr_cycle; /* write cycle time */ u32 clk; u32 t_bacc; /* burst access valid clock to output delay */ u32 t_ces; /* CS setup time to clk */ u32 t_avds; /* ADV setup time to clk */ u32 t_avdh; /* ADV hold time from clk */ u32 t_ach; /* address hold time from clk */ u32 t_rdyo; /* clk to ready valid */ u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */ u32 t_ce_avd; /* CS on to ADV on delay */ /* XXX: check the possibility of combining * cyc_aavhd_oe & cyc_aavdh_we */ u8 cyc_aavdh_oe;/* read address hold time in cycles */ u8 cyc_aavdh_we;/* write address hold time in cycles */ u8 cyc_oe; /* access time from OE assertion in cycles */ u8 cyc_wpl; /* write deassertion time in cycles */ u32 cyc_iaa; /* initial access time in cycles */ /* extra delays */ bool ce_xdelay; bool avd_xdelay; bool oe_xdelay; bool we_xdelay; }; struct gpmc_settings { bool burst_wrap; /* enables wrap bursting */ bool burst_read; /* enables read page/burst mode */ bool burst_write; /* enables write page/burst mode */ bool device_nand; /* device is NAND */ bool sync_read; /* enables synchronous reads */ bool sync_write; /* enables synchronous writes */ bool wait_on_read; /* monitor wait on reads */ bool wait_on_write; /* monitor wait on writes */ u32 burst_len; /* page/burst length */ u32 device_width; /* device bus width (8 or 16 bit) */ u32 mux_add_data; /* multiplex address & data */ u32 wait_pin; /* wait-pin to be used */ }; extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, struct gpmc_settings *gpmc_s, struct gpmc_device_timings *dev_t); struct gpmc_nand_regs; struct device_node; extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); extern int gpmc_get_client_irq(unsigned irq_config); extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); extern void gpmc_cs_write_reg(int cs, int idx, u32 val); extern int gpmc_calc_divider(unsigned int sync_clk); extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, const struct gpmc_settings *s); extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p); extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); extern int gpmc_configure(int cmd, int wval); extern void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); struct gpmc_timings; struct omap_nand_platform_data; struct omap_onenand_platform_data; #if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) extern int gpmc_nand_init(struct omap_nand_platform_data *d, struct gpmc_timings *gpmc_t); #else static inline int gpmc_nand_init(struct omap_nand_platform_data *d, struct gpmc_timings *gpmc_t) { return 0; } #endif #if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) extern void gpmc_onenand_init(struct omap_onenand_platform_data *d); #else #define board_onenand_data NULL static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d) { } #endif