summaryrefslogtreecommitdiffstats
path: root/kernel/arch/powerpc/boot/dts/fsl/ppa8548.dts
blob: 8f9ffbe0e4f49f8f9601ea486c154763573a9d7f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
/*
 * PPA8548 Device Tree Source (36-bit address map)
 * Copyright 2013 Prodrive B.V.
 *
 * Based on:
 * MPC8548 CDS Device Tree Source (36-bit address map)
 * Copyright 2012 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/include/ "mpc8548si-pre.dtsi"

/ {
	model = "ppa8548";
	compatible = "ppa8548";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	memory {
		device_type = "memory";
		reg = <0 0 0x0 0x40000000>;
	};

	lbc: localbus@fe0005000 {
		reg = <0xf 0xe0005000 0 0x1000>;
		ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
	};

	soc: soc8548@fe0000000 {
		ranges = <0 0xf 0xe0000000 0x100000>;
	};

	pci0: pci@fe0008000 {
		/* ppa8548 board doesn't support PCI */
		status = "disabled";
	};

	pci1: pci@fe0009000 {
		/* ppa8548 board doesn't support PCI */
		status = "disabled";
	};

	pci2: pcie@fe000a000 {
		/* ppa8548 board doesn't support PCI */
		status = "disabled";
	};

	rio: rapidio@fe00c0000 {
		reg = <0xf 0xe00c0000 0x0 0x11000>;
		port1 {
			ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
		};
	};
};

&lbc {
	nor@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x00800000>;
		bank-width = <2>;
		device-width = <2>;

		partition@0 {
			reg = <0x0 0x7A0000>;
			label = "user";
		};

		partition@7A0000 {
			reg = <0x7A0000 0x20000>;
			label = "env";
			read-only;
		};

		partition@7C0000 {
			reg = <0x7C0000 0x40000>;
			label = "u-boot";
			read-only;
		};
	};
};

&soc {
	i2c@3000 {
		rtc@6f {
			compatible = "intersil,isl1208";
			reg = <0x6f>;
		};
	};

	i2c@3100 {
	};

	/*
	 * Only ethernet controller @25000 and @26000 are used.
	 * Use alias enet2 and enet3 for the remainig controllers,
	 * to stay compatible with mpc8548si-pre.dtsi.
	 */
	enet2: ethernet@24000 {
		status = "disabled";
	};

	mdio@24520 {
		phy0: ethernet-phy@0 {
			interrupts = <7 1 0 0>;
			reg = <0x0>;
		};
		phy1: ethernet-phy@1 {
			interrupts = <8 1 0 0>;
			reg = <0x1>;
		};
		tbi0: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet0: ethernet@25000 {
		tbi-handle = <&tbi1>;
		phy-handle = <&phy0>;
	};

	mdio@25520 {
		tbi1: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet1: ethernet@26000 {
		tbi-handle = <&tbi2>;
		phy-handle = <&phy1>;
	};

	mdio@26520 {
		tbi2: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet3: ethernet@27000 {
		status = "disabled";
	};

	mdio@27520 {
		tbi3: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	crypto@30000 {
		status = "disabled";
	};
};

/include/ "mpc8548si-post.dtsi"