diff options
Diffstat (limited to 'qemu/roms/u-boot/include/usb')
| -rw-r--r-- | qemu/roms/u-boot/include/usb/ci_udc.h | 14 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/designware_udc.h | 184 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/ehci-fsl.h | 281 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/fotg210.h | 363 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/fusbh200.h | 60 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/lin_gadget_compat.h | 56 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/mpc8xx_udc.h | 178 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/omap1510_udc.h | 174 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/pxa27x_udc.h | 32 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/s3c_udc.h | 112 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/udc.h | 53 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/usb/ulpi.h | 319 |
12 files changed, 0 insertions, 1826 deletions
diff --git a/qemu/roms/u-boot/include/usb/ci_udc.h b/qemu/roms/u-boot/include/usb/ci_udc.h deleted file mode 100644 index 0dee50461..000000000 --- a/qemu/roms/u-boot/include/usb/ci_udc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __CI_UDC_H__ -#define __CI_UDC_H__ - -#define EP_MAX_PACKET_SIZE 0x200 -#define EP0_MAX_PACKET_SIZE 64 -#endif /* __CI_UDC_H__ */ diff --git a/qemu/roms/u-boot/include/usb/designware_udc.h b/qemu/roms/u-boot/include/usb/designware_udc.h deleted file mode 100644 index 2e1cdf138..000000000 --- a/qemu/roms/u-boot/include/usb/designware_udc.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DW_UDC_H -#define __DW_UDC_H - -/* - * Defines for USBD - * - * The udc_ahb controller has three AHB slaves: - * - * 1. THe UDC registers - * 2. The plug detect - * 3. The RX/TX FIFO - */ - -#define MAX_ENDPOINTS 16 - -struct udc_endp_regs { - u32 endp_cntl; - u32 endp_status; - u32 endp_bsorfn; - u32 endp_maxpacksize; - u32 reserved_1; - u32 endp_desc_point; - u32 reserved_2; - u32 write_done; -}; - -/* Endpoint Control Register definitions */ - -#define ENDP_CNTL_STALL 0x00000001 -#define ENDP_CNTL_FLUSH 0x00000002 -#define ENDP_CNTL_SNOOP 0x00000004 -#define ENDP_CNTL_POLL 0x00000008 -#define ENDP_CNTL_CONTROL 0x00000000 -#define ENDP_CNTL_ISO 0x00000010 -#define ENDP_CNTL_BULK 0x00000020 -#define ENDP_CNTL_INT 0x00000030 -#define ENDP_CNTL_NAK 0x00000040 -#define ENDP_CNTL_SNAK 0x00000080 -#define ENDP_CNTL_CNAK 0x00000100 -#define ENDP_CNTL_RRDY 0x00000200 - -/* Endpoint Satus Register definitions */ - -#define ENDP_STATUS_PIDMSK 0x0000000f -#define ENDP_STATUS_OUTMSK 0x00000030 -#define ENDP_STATUS_OUT_NONE 0x00000000 -#define ENDP_STATUS_OUT_DATA 0x00000010 -#define ENDP_STATUS_OUT_SETUP 0x00000020 -#define ENDP_STATUS_IN 0x00000040 -#define ENDP_STATUS_BUFFNAV 0x00000080 -#define ENDP_STATUS_FATERR 0x00000100 -#define ENDP_STATUS_HOSTBUSERR 0x00000200 -#define ENDP_STATUS_TDC 0x00000400 -#define ENDP_STATUS_RXPKTMSK 0x003ff800 - -struct udc_regs { - struct udc_endp_regs in_regs[MAX_ENDPOINTS]; - struct udc_endp_regs out_regs[MAX_ENDPOINTS]; - u32 dev_conf; - u32 dev_cntl; - u32 dev_stat; - u32 dev_int; - u32 dev_int_mask; - u32 endp_int; - u32 endp_int_mask; - u32 reserved_3[0x39]; - u32 reserved_4; /* offset 0x500 */ - u32 udc_endp_reg[MAX_ENDPOINTS]; -}; - -/* Device Configuration Register definitions */ - -#define DEV_CONF_HS_SPEED 0x00000000 -#define DEV_CONF_LS_SPEED 0x00000002 -#define DEV_CONF_FS_SPEED 0x00000003 -#define DEV_CONF_REMWAKEUP 0x00000004 -#define DEV_CONF_SELFPOW 0x00000008 -#define DEV_CONF_SYNCFRAME 0x00000010 -#define DEV_CONF_PHYINT_8 0x00000020 -#define DEV_CONF_PHYINT_16 0x00000000 -#define DEV_CONF_UTMI_BIDIR 0x00000040 -#define DEV_CONF_STATUS_STALL 0x00000080 - -/* Device Control Register definitions */ - -#define DEV_CNTL_RESUME 0x00000001 -#define DEV_CNTL_TFFLUSH 0x00000002 -#define DEV_CNTL_RXDMAEN 0x00000004 -#define DEV_CNTL_TXDMAEN 0x00000008 -#define DEV_CNTL_DESCRUPD 0x00000010 -#define DEV_CNTL_BIGEND 0x00000020 -#define DEV_CNTL_BUFFILL 0x00000040 -#define DEV_CNTL_TSHLDEN 0x00000080 -#define DEV_CNTL_BURSTEN 0x00000100 -#define DEV_CNTL_DMAMODE 0x00000200 -#define DEV_CNTL_SOFTDISCONNECT 0x00000400 -#define DEV_CNTL_SCALEDOWN 0x00000800 -#define DEV_CNTL_BURSTLENU 0x00010000 -#define DEV_CNTL_BURSTLENMSK 0x00ff0000 -#define DEV_CNTL_TSHLDLENU 0x01000000 -#define DEV_CNTL_TSHLDLENMSK 0xff000000 - -/* Device Status Register definitions */ - -#define DEV_STAT_CFG 0x0000000f -#define DEV_STAT_INTF 0x000000f0 -#define DEV_STAT_ALT 0x00000f00 -#define DEV_STAT_SUSP 0x00001000 -#define DEV_STAT_ENUM 0x00006000 -#define DEV_STAT_ENUM_SPEED_HS 0x00000000 -#define DEV_STAT_ENUM_SPEED_FS 0x00002000 -#define DEV_STAT_ENUM_SPEED_LS 0x00004000 -#define DEV_STAT_RXFIFO_EMPTY 0x00008000 -#define DEV_STAT_PHY_ERR 0x00010000 -#define DEV_STAT_TS 0xf0000000 - -/* Device Interrupt Register definitions */ - -#define DEV_INT_MSK 0x0000007f -#define DEV_INT_SETCFG 0x00000001 -#define DEV_INT_SETINTF 0x00000002 -#define DEV_INT_INACTIVE 0x00000004 -#define DEV_INT_USBRESET 0x00000008 -#define DEV_INT_SUSPUSB 0x00000010 -#define DEV_INT_SOF 0x00000020 -#define DEV_INT_ENUM 0x00000040 - -/* Endpoint Interrupt Register definitions */ - -#define ENDP0_INT_CTRLIN 0x00000001 -#define ENDP1_INT_BULKIN 0x00000002 -#define ENDP_INT_NONISOIN_MSK 0x0000AAAA -#define ENDP2_INT_BULKIN 0x00000004 -#define ENDP0_INT_CTRLOUT 0x00010000 -#define ENDP1_INT_BULKOUT 0x00020000 -#define ENDP2_INT_BULKOUT 0x00040000 -#define ENDP_INT_NONISOOUT_MSK 0x55540000 - -/* Endpoint Register definitions */ -#define ENDP_EPDIR_OUT 0x00000000 -#define ENDP_EPDIR_IN 0x00000010 -#define ENDP_EPTYPE_CNTL 0x0 -#define ENDP_EPTYPE_ISO 0x1 -#define ENDP_EPTYPE_BULK 0x2 -#define ENDP_EPTYPE_INT 0x3 - -/* - * Defines for Plug Detect - */ - -struct plug_regs { - u32 plug_state; - u32 plug_pending; -}; - -/* Plug State Register definitions */ -#define PLUG_STATUS_EN 0x1 -#define PLUG_STATUS_ATTACHED 0x2 -#define PLUG_STATUS_PHY_RESET 0x4 -#define PLUG_STATUS_PHY_MODE 0x8 - -/* - * Defines for UDC FIFO (Slave Mode) - */ -struct udcfifo_regs { - u32 *fifo_p; -}; - -/* - * UDC endpoint definitions - */ -#define UDC_EP0 0 -#define UDC_EP1 1 -#define UDC_EP2 2 -#define UDC_EP3 3 - -#endif /* __DW_UDC_H */ diff --git a/qemu/roms/u-boot/include/usb/ehci-fsl.h b/qemu/roms/u-boot/include/usb/ehci-fsl.h deleted file mode 100644 index c9ee1d5bf..000000000 --- a/qemu/roms/u-boot/include/usb/ehci-fsl.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc - * Copyright (c) 2005 MontaVista Software - * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EHCI_FSL_H -#define _EHCI_FSL_H - -#include <asm/processor.h> - -/* Global offsets */ -#define FSL_SKIP_PCI 0x100 - -/* offsets for the non-ehci registers in the FSL SOC USB controller */ -#define FSL_SOC_USB_ULPIVP 0x170 -#define FSL_SOC_USB_PORTSC1 0x184 -#define PORT_PTS_MSK (3 << 30) -#define PORT_PTS_UTMI (0 << 30) -#define PORT_PTS_ULPI (2 << 30) -#define PORT_PTS_SERIAL (3 << 30) -#define PORT_PTS_PTW (1 << 28) -#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */ -#define PORT_PTS_PHCD (1 << 23) -#define PORT_PP (1 << 12) -#define PORT_PR (1 << 8) - -/* USBMODE Register bits */ -#define CM_IDLE (0 << 0) -#define CM_RESERVED (1 << 0) -#define CM_DEVICE (2 << 0) -#define CM_HOST (3 << 0) -#define ES_BE (1 << 2) /* Big Endian Select, default is LE */ -#define USBMODE_RESERVED_2 (0 << 2) -#define SLOM (1 << 3) -#define SDIS (1 << 4) - -/* CONTROL Register bits */ -#define ULPI_INT_EN (1 << 0) -#define WU_INT_EN (1 << 1) -#define USB_EN (1 << 2) -#define LSF_EN (1 << 3) -#define KEEP_OTG_ON (1 << 4) -#define OTG_PORT (1 << 5) -#define REFSEL_12MHZ (0 << 6) -#define REFSEL_16MHZ (1 << 6) -#define REFSEL_48MHZ (2 << 6) -#define PLL_RESET (1 << 8) -#define UTMI_PHY_EN (1 << 9) -#define PHY_CLK_SEL_UTMI (0 << 10) -#define PHY_CLK_SEL_ULPI (1 << 10) -#define CLKIN_SEL_USB_CLK (0 << 11) -#define CLKIN_SEL_USB_CLK2 (1 << 11) -#define CLKIN_SEL_SYS_CLK (2 << 11) -#define CLKIN_SEL_SYS_CLK2 (3 << 11) -#define RESERVED_18 (0 << 13) -#define RESERVED_17 (0 << 14) -#define RESERVED_16 (0 << 15) -#define WU_INT (1 << 16) -#define PHY_CLK_VALID (1 << 17) - -#define FSL_SOC_USB_PORTSC2 0x188 - -/* OTG Status Control Register bits */ -#define FSL_SOC_USB_OTGSC 0x1a4 -#define CTRL_VBUS_DISCHARGE (0x1<<0) -#define CTRL_VBUS_CHARGE (0x1<<1) -#define CTRL_OTG_TERMINATION (0x1<<3) -#define CTRL_DATA_PULSING (0x1<<4) -#define CTRL_ID_PULL_EN (0x1<<5) -#define HA_DATA_PULSE (0x1<<6) -#define HA_BA (0x1<<7) -#define STS_USB_ID (0x1<<8) -#define STS_A_VBUS_VALID (0x1<<9) -#define STS_A_SESSION_VALID (0x1<<10) -#define STS_B_SESSION_VALID (0x1<<11) -#define STS_B_SESSION_END (0x1<<12) -#define STS_1MS_TOGGLE (0x1<<13) -#define STS_DATA_PULSING (0x1<<14) -#define INTSTS_USB_ID (0x1<<16) -#define INTSTS_A_VBUS_VALID (0x1<<17) -#define INTSTS_A_SESSION_VALID (0x1<<18) -#define INTSTS_B_SESSION_VALID (0x1<<19) -#define INTSTS_B_SESSION_END (0x1<<20) -#define INTSTS_1MS (0x1<<21) -#define INTSTS_DATA_PULSING (0x1<<22) -#define INTR_USB_ID_EN (0x1<<24) -#define INTR_A_VBUS_VALID_EN (0x1<<25) -#define INTR_A_SESSION_VALID_EN (0x1<<26) -#define INTR_B_SESSION_VALID_EN (0x1<<27) -#define INTR_B_SESSION_END_EN (0x1<<28) -#define INTR_1MS_TIMER_EN (0x1<<29) -#define INTR_DATA_PULSING_EN (0x1<<30) -#define INTSTS_MASK (0x00ff0000) - -/* USBCMD Bits of interest */ -#define EHCI_FSL_USBCMD_RST (1 << 1) -#define EHCI_FSL_USBCMD_RS (1 << 0) - -#define INTERRUPT_ENABLE_BITS_MASK \ - (INTR_USB_ID_EN | \ - INTR_1MS_TIMER_EN | \ - INTR_A_VBUS_VALID_EN | \ - INTR_A_SESSION_VALID_EN | \ - INTR_B_SESSION_VALID_EN | \ - INTR_B_SESSION_END_EN | \ - INTR_DATA_PULSING_EN) - -#define INTERRUPT_STATUS_BITS_MASK \ - (INTSTS_USB_ID | \ - INTR_1MS_TIMER_EN | \ - INTSTS_A_VBUS_VALID | \ - INTSTS_A_SESSION_VALID | \ - INTSTS_B_SESSION_VALID | \ - INTSTS_B_SESSION_END | \ - INTSTS_DATA_PULSING) - -#define FSL_SOC_USB_USBMODE 0x1a8 - -#define USBGENCTRL 0x200 /* NOTE: big endian */ -#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ -#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ -#define GC_PPP (1 << 3) /* Port Power Polarity */ -#define GC_PFP (1 << 2) /* Power Fault Polarity */ -#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ -#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ - -#define ISIPHYCTRL 0x204 /* NOTE: big endian */ -#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ -#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ -#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ -#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ -#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ - -#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ -#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ -#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ -#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ -#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ -#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ -#define SNOOP_SIZE_2GB 0x1e - -/* System Clock Control Register */ -#define MPC83XX_SCCR_USB_MASK 0x00f00000 -#define MPC83XX_SCCR_USB_DRCM_11 0x00300000 -#define MPC83XX_SCCR_USB_DRCM_01 0x00100000 -#define MPC83XX_SCCR_USB_DRCM_10 0x00200000 - -#if defined(CONFIG_MPC83xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR -#if defined(CONFIG_MPC834x) -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR -#else -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif -#elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_MPC512X) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif - -/* - * Increasing TX FIFO threshold value from 2 to 4 decreases - * data burst rate with which data packets are posted from the TX - * latency FIFO to compensate for latencies in DDR pipeline during DMA - */ -#define TXFIFOTHRESH 4 - -/* - * USB Registers - */ -struct usb_ehci { - u32 id; /* 0x000 - Identification register */ - u32 hwgeneral; /* 0x004 - General hardware parameters */ - u32 hwhost; /* 0x008 - Host hardware parameters */ - u32 hwdevice; /* 0x00C - Device hardware parameters */ - u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */ - u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */ - u8 res1[0x68]; - u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */ - u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */ - u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ - u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ - u32 sbuscfg; /* 0x090 - System Bus Interface Control */ - u8 res2[0x6C]; - u8 caplength; /* 0x100 - Capability Register Length */ - u8 res3[0x1]; - u16 hciversion; /* 0x102 - Host Interface Version */ - u32 hcsparams; /* 0x104 - Host Structural Parameters */ - u32 hccparams; /* 0x108 - Host Capability Parameters */ - u8 res4[0x14]; - u32 dciversion; /* 0x120 - Device Interface Version */ - u32 dciparams; /* 0x124 - Device Controller Params */ - u8 res5[0x18]; - u32 usbcmd; /* 0x140 - USB Command */ - u32 usbsts; /* 0x144 - USB Status */ - u32 usbintr; /* 0x148 - USB Interrupt Enable */ - u32 frindex; /* 0x14C - USB Frame Index */ - u8 res6[0x4]; - u32 perlistbase; /* 0x154 - Periodic List Base - - USB Device Address */ - u32 ep_list_addr; /* 0x158 - Next Asynchronous List - - End Point Address */ - u8 res7[0x4]; - u32 burstsize; /* 0x160 - Programmable Burst Size */ -#define FSL_EHCI_TXPBURST(X) ((X) << 8) -#define FSL_EHCI_RXPBURST(X) (X) - u32 txfilltuning; /* 0x164 - Host TT Transmit - pre-buffer packet tuning */ - u8 res8[0x8]; - u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ - u8 res9[0xc]; - u32 config_flag; /* 0x180 - Configured Flag Register */ - u32 portsc; /* 0x184 - Port status/control */ - u8 res10[0x1C]; - u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */ - u32 usbmode; /* 0x1a8 - USB Device Mode */ - u32 epsetupstat; /* 0x1ac - End Point Setup Status */ - u32 epprime; /* 0x1b0 - End Point Init Status */ - u32 epflush; /* 0x1b4 - End Point De-initlialize */ - u32 epstatus; /* 0x1b8 - End Point Status */ - u32 epcomplete; /* 0x1bc - End Point Complete */ - u32 epctrl0; /* 0x1c0 - End Point Control 0 */ - u32 epctrl1; /* 0x1c4 - End Point Control 1 */ - u32 epctrl2; /* 0x1c8 - End Point Control 2 */ - u32 epctrl3; /* 0x1cc - End Point Control 3 */ - u32 epctrl4; /* 0x1d0 - End Point Control 4 */ - u32 epctrl5; /* 0x1d4 - End Point Control 5 */ - u8 res11[0x28]; - u32 usbgenctrl; /* 0x200 - USB General Control */ - u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */ - u8 res12[0x1F8]; - u32 snoop1; /* 0x400 - Snoop 1 */ - u32 snoop2; /* 0x404 - Snoop 2 */ - u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ - u32 prictrl; /* 0x40c - Priority Control */ - u32 sictrl; /* 0x410 - System Interface Control */ - u8 res13[0xEC]; - u32 control; /* 0x500 - Control */ - u8 res14[0xafc]; -}; - -/* - * For MXC SOCs - */ - -/* values for portsc field */ -#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) -#define MXC_EHCI_FORCE_FS (1 << 24) -#define MXC_EHCI_UTMI_8BIT (0 << 28) -#define MXC_EHCI_UTMI_16BIT (1 << 28) -#define MXC_EHCI_SERIAL (1 << 29) -#define MXC_EHCI_MODE_UTMI (0 << 30) -#define MXC_EHCI_MODE_PHILIPS (1 << 30) -#define MXC_EHCI_MODE_ULPI (2 << 30) -#define MXC_EHCI_MODE_SERIAL (3 << 30) - -/* values for flags field */ -#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) -#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) -#define MXC_EHCI_INTERFACE_MASK (0xf) - -#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) -#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) -#define MXC_EHCI_TTL_ENABLED (1 << 8) - -#define MXC_EHCI_INTERNAL_PHY (1 << 9) -#define MXC_EHCI_IPPUE_DOWN (1 << 10) -#define MXC_EHCI_IPPUE_UP (1 << 11) - -/* Board-specific initialization */ -int board_ehci_hcd_init(int port); - -#endif /* _EHCI_FSL_H */ diff --git a/qemu/roms/u-boot/include/usb/fotg210.h b/qemu/roms/u-boot/include/usb/fotg210.h deleted file mode 100644 index b83e8f593..000000000 --- a/qemu/roms/u-boot/include/usb/fotg210.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Faraday USB 2.0 OTG Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FOTG210_H -#define _FOTG210_H - -struct fotg210_regs { - /* USB Host Controller */ - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t rsvd1[3]; - uint32_t miscr; /* 0x40: Miscellaneous Register */ - uint32_t rsvd2[15]; - /* USB OTG Controller */ - uint32_t otgcsr;/* 0x80: OTG Control Status Register */ - uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */ - uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */ - uint32_t rsvd3[13]; - uint32_t isr; /* 0xC0: Global Interrupt Status Register */ - uint32_t imr; /* 0xC4: Global Interrupt Mask Register */ - uint32_t rsvd4[14]; - /* USB Device Controller */ - uint32_t dev_ctrl;/* 0x100: Device Control Register */ - uint32_t dev_addr;/* 0x104: Device Address Register */ - uint32_t dev_test;/* 0x108: Device Test Register */ - uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */ - uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */ - uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */ - uint32_t rsvd5[2]; - uint32_t cxfifo;/* 0x120: CX FIFO Register */ - uint32_t idle; /* 0x124: IDLE Counter Register */ - uint32_t rsvd6[2]; - uint32_t gimr; /* 0x130: Group Interrupt Mask Register */ - uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */ - uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */ - uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */ - uint32_t gisr; /* 0x140: Group Interrupt Status Register */ - uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */ - uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */ - uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */ - uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */ - uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */ - uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */ - uint32_t rsvd7[1]; - uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */ - uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */ - uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */ - uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */ - uint32_t fifomap;/* 0x1a8: FIFO Map Register */ - uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */ - uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */ - uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */ - uint32_t rsvd8[1]; - uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */ - uint32_t dma_addr; /* 0x1cc: DMA Address Register */ - uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */ -}; - -/* Miscellaneous Register */ -#define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */ -#define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* OTG Control Status Register */ -#define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */ -#define OTGCSR_SPD_LOW (1 << 22) -#define OTGCSR_SPD_FULL (0 << 22) -#define OTGCSR_SPD_MASK (3 << 22) -#define OTGCSR_SPD_SHIFT 22 -#define OTGCSR_SPD(x) (((x) >> 22) & 0x03) -#define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */ -#define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */ -#define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */ -#define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */ -#define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */ -#define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */ -#define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */ -#define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */ -#define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/ -#define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/ -#define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/ -#define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/ -#define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/ -#define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/ -#define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */ -#define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */ -#define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */ -#define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */ -#define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */ -#define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */ -#define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */ -#define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */ -#define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */ - -/* OTG Interrupt Status Register */ -#define OTGISR_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGISR_OVD (1 << 10) /* over-current detected */ -#define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGISR_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGISR_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGISR_BSRP (1 << 0) /* B-device SRP complete */ - -/* OTG Interrupt Enable Register */ -#define OTGIER_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGIER_OVD (1 << 10) /* over-current detected */ -#define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGIER_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGIER_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGIER_BSRP (1 << 0) /* B-device SRP complete */ - -/* Global Interrupt Status Register (W1C) */ -#define ISR_HOST (1 << 2) /* USB Host interrupt */ -#define ISR_OTG (1 << 1) /* USB OTG interrupt */ -#define ISR_DEV (1 << 0) /* USB Device interrupt */ -#define ISR_MASK 0x07 - -/* Global Interrupt Mask Register */ -#define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */ -#define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */ -#define IMR_HOST (1 << 2) /* USB Host interrupt */ -#define IMR_OTG (1 << 1) /* USB OTG interrupt */ -#define IMR_DEV (1 << 0) /* USB Device interrupt */ -#define IMR_MASK 0x0f - -/* Device Control Register */ -#define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */ -#define DEVCTRL_HS (1 << 6) /* High Speed Mode */ -#define DEVCTRL_FS (0 << 6) /* Full Speed Mode */ -#define DEVCTRL_EN (1 << 5) /* Chip Enable */ -#define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */ -#define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */ -#define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */ -#define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */ -#define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */ - -/* Device Address Register */ -#define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */ -#define DEVADDR_ADDR(x) ((x) & 0x7f) -#define DEVADDR_ADDR_MASK 0x7f - -/* Device Test Register */ -#define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */ -#define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */ -#define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */ -#define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */ -#define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */ -#define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */ -#define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */ - -/* SOF Frame Number Register */ -#define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */ -#define SOFFNR_FNR(x) ((x) & 0x7ff) /* SOF Frame Number */ - -/* SOF Mask Timer Register */ -#define SOFMTR_TMR(x) ((x) & 0xffff) - -/* PHY Test Mode Selector Register */ -#define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */ -#define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */ -#define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */ -#define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */ -#define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */ - -/* CX FIFO Register */ -#define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */ -#define CXFIFO_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */ -#define CXFIFO_FIFOE_FIFO0 (1 << 8) -#define CXFIFO_FIFOE_FIFO1 (1 << 9) -#define CXFIFO_FIFOE_FIFO2 (1 << 10) -#define CXFIFO_FIFOE_FIFO3 (1 << 11) -#define CXFIFO_FIFOE_MASK (0x0f << 8) -#define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */ -#define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */ -#define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */ -#define CXFIFO_CXSTALL (1 << 2) /* CX Stall */ -#define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */ -#define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */ - -/* IDLE Counter Register */ -#define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */ - -/* Group Interrupt Mask(Disable) Register */ -#define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */ -#define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */ -#define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */ -#define GIMR_MASK 0x07 - -/* Group Interrupt Mask(Disable) Register 0 (CX) */ -#define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GIMR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GIMR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ -#define GIMR0_MASK 0x3f - -/* Group Interrupt Mask(Disable) Register 1 (FIFO) */ -#define GIMR1_FIFO_IN(x) (1 << (((x) & 3) + 16)) /* FIFOx IN */ -#define GIMR1_FIFO_TX(x) GIMR1_FIFO_IN(x) -#define GIMR1_FIFO_OUT(x) (1 << (((x) & 3) * 2)) /* FIFOx OUT */ -#define GIMR1_FIFO_SPK(x) (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */ -#define GIMR1_FIFO_RX(x) (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x)) -#define GIMR1_MASK 0xf00ff - -/* Group Interrupt Mask(Disable) Register 2 (Device) */ -#define GIMR2_WAKEUP (1 << 10) /* Device waked up */ -#define GIMR2_IDLE (1 << 9) /* Device idle */ -#define GIMR2_DMAERR (1 << 8) /* DMA error */ -#define GIMR2_DMAFIN (1 << 7) /* DMA finished */ -#define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GIMR2_RESET (1 << 0) /* Reset Interrupt */ -#define GIMR2_MASK 0x7ff - -/* Group Interrupt Status Register */ -#define GISR_GRP2 (1 << 2) /* Interrupt group 2 */ -#define GISR_GRP1 (1 << 1) /* Interrupt group 1 */ -#define GISR_GRP0 (1 << 0) /* Interrupt group 0 */ - -/* Group Interrupt Status Register 0 (CX) */ -#define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GISR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GISR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ - -/* Group Interrupt Status Register 1 (FIFO) */ -#define GISR1_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */ -#define GISR1_OUT_FIFO(x) (1 << (((x) & 0x03) * 2)) /* FIFOx OUT */ -#define GISR1_SPK_FIFO(x) (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */ -#define GISR1_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */ - -/* Group Interrupt Status Register 2 (Device) */ -#define GISR2_WAKEUP (1 << 10) /* Device waked up */ -#define GISR2_IDLE (1 << 9) /* Device idle */ -#define GISR2_DMAERR (1 << 8) /* DMA error */ -#define GISR2_DMAFIN (1 << 7) /* DMA finished */ -#define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GISR2_RESET (1 << 0) /* Reset Interrupt */ - -/* Receive Zero-Length-Packet Register */ -#define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */ - -/* Transfer Zero-Length-Packet Register */ -#define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */ - -/* ISOC Error/Abort Status Register */ -#define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */ - -/* IN Endpoint Register */ -#define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */ -#define IEP_TNRHB(x) (((x) & 0x03) << 13) \ - /* Transaction Number for High-Bandwidth EP(ISOC) */ -#define IEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define IEP_STALL (1 << 11) /* Stall */ -#define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* OUT Endpoint Register */ -#define OEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define OEP_STALL (1 << 11) /* Stall */ -#define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* Endpoint Map Register (EP1 ~ EP4) */ -#define EPMAP14_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 0) -#define EPMAP14_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 4) -#define EPMAP14_SET(ep, in, out) \ - do { \ - EPMAP14_SET_IN(ep, in); \ - EPMAP14_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */ - -/* Endpoint Map Register (EP5 ~ EP8) */ -#define EPMAP58_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 0) -#define EPMAP58_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 4) -#define EPMAP58_SET(ep, in, out) \ - do { \ - EPMAP58_SET_IN(ep, in); \ - EPMAP58_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */ - -/* FIFO Map Register */ -#define FIFOMAP_BIDIR (2 << 4) -#define FIFOMAP_IN (1 << 4) -#define FIFOMAP_OUT (0 << 4) -#define FIFOMAP_DIR_MASK 0x30 -#define FIFOMAP_EP(x) ((x) & 0x0f) -#define FIFOMAP_EP_MASK 0x0f -#define FIFOMAP_CFG_MASK 0x3f -#define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */ -#define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Configuration Register */ -#define FIFOCFG_EN (1 << 5) -#define FIFOCFG_BLKSZ_1024 (1 << 4) -#define FIFOCFG_BLKSZ_512 (0 << 4) -#define FIFOCFG_3BLK (2 << 2) -#define FIFOCFG_2BLK (1 << 2) -#define FIFOCFG_1BLK (0 << 2) -#define FIFOCFG_NBLK_MASK 3 -#define FIFOCFG_NBLK_SHIFT 2 -#define FIFOCFG_INTR (3 << 0) -#define FIFOCFG_BULK (2 << 0) -#define FIFOCFG_ISOC (1 << 0) -#define FIFOCFG_RSVD (0 << 0) /* Reserved */ -#define FIFOCFG_TYPE_MASK 3 -#define FIFOCFG_TYPE_SHIFT 0 -#define FIFOCFG_CFG_MASK 0x3f -#define FIFOCFG(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Control Status Register */ -#define FIFOCSR_RESET (1 << 12) /* FIFO Reset */ -#define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */ - -/* DMA Target FIFO Register */ -#define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */ -#define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */ - -/* DMA Control Register */ -#define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */ -#define DMACTRL_LEN_SHIFT 8 -#define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */ -#define DMACTRL_ABORT (1 << 3) /* DMA abort */ -#define DMACTRL_IO2IO (1 << 2) /* IO to IO */ -#define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */ -#define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */ -#define DMACTRL_START (1 << 0) /* DMA start */ - -#endif diff --git a/qemu/roms/u-boot/include/usb/fusbh200.h b/qemu/roms/u-boot/include/usb/fusbh200.h deleted file mode 100644 index e2d855365..000000000 --- a/qemu/roms/u-boot/include/usb/fusbh200.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FUSBH200_H -#define _FUSBH200_H - -struct fusbh200_regs { - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ - uint32_t rsvd[2]; - uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ - uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ - uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ -}; - -/* EOF & Async. Schedule Sleep Timer Register */ -#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ -#define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ -#define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* Bus Monitor Control Status Register */ -#define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ -#define BMCSR_SPD_LOW (1 << 9) -#define BMCSR_SPD_FULL (0 << 9) -#define BMCSR_SPD_MASK (3 << 9) -#define BMCSR_SPD_SHIFT 9 -#define BMCSR_SPD(x) ((x >> 9) & 0x03) -#define BMCSR_VBUS (1 << 8) /* VBUS Valid */ -#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ -#define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ -#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ -#define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ -#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ -#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ -#define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ -#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ -#define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ - -/* Bus Monitor Interrupt Status Register */ -/* Bus Monitor Interrupt Enable Register */ -#define BMISR_DMAERR (1 << 4) /* DMA error */ -#define BMISR_DMA (1 << 3) /* DMA complete */ -#define BMISR_DEVRM (1 << 2) /* device removed */ -#define BMISR_OVD (1 << 1) /* over-current detected */ -#define BMISR_VBUSERR (1 << 0) /* VBUS error */ - -#endif diff --git a/qemu/roms/u-boot/include/usb/lin_gadget_compat.h b/qemu/roms/u-boot/include/usb/lin_gadget_compat.h deleted file mode 100644 index a25e9d9ef..000000000 --- a/qemu/roms/u-boot/include/usb/lin_gadget_compat.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2011 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - * - * This is a Linux kernel compatibility layer for USB Gadget - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __LIN_COMPAT_H__ -#define __LIN_COMPAT_H__ - -#include <linux/compat.h> - -/* common */ -#define spin_lock_init(...) -#define spin_lock(...) -#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0) -#define spin_unlock(...) -#define spin_unlock_irqrestore(lock, flags) do {flags = 0; } while (0) -#define disable_irq(...) -#define enable_irq(...) - -#define mutex_init(...) -#define mutex_lock(...) -#define mutex_unlock(...) - -#define GFP_KERNEL 0 - -#define IRQ_HANDLED 1 - -#define ENOTSUPP 524 /* Operation is not supported */ - -#define BITS_PER_BYTE 8 -#define BITS_TO_LONGS(nr) \ - DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#define DECLARE_BITMAP(name, bits) \ - unsigned long name[BITS_TO_LONGS(bits)] - -#define small_const_nbits(nbits) \ - (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG) - -static inline void bitmap_zero(unsigned long *dst, int nbits) -{ - if (small_const_nbits(nbits)) - *dst = 0UL; - else { - int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); - memset(dst, 0, len); - } -} - -#define dma_cache_maint(addr, size, mode) cache_flush() -void cache_flush(void); - -#endif /* __LIN_COMPAT_H__ */ diff --git a/qemu/roms/u-boot/include/usb/mpc8xx_udc.h b/qemu/roms/u-boot/include/usb/mpc8xx_udc.h deleted file mode 100644 index 9906c75f6..000000000 --- a/qemu/roms/u-boot/include/usb/mpc8xx_udc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit - * bodonoghue@codehermit.ie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <commproc.h> - -/* Mode Register */ -#define USMOD_EN 0x01 -#define USMOD_HOST 0x02 -#define USMOD_TEST 0x04 -#define USMOD_SFTE 0x08 -#define USMOD_RESUME 0x40 -#define USMOD_LSS 0x80 - -/* Endpoint Registers */ -#define USEP_RHS_NORM 0x00 -#define USEP_RHS_IGNORE 0x01 -#define USEP_RHS_NAK 0x02 -#define USEP_RHS_STALL 0x03 - -#define USEP_THS_NORM 0x00 -#define USEP_THS_IGNORE 0x04 -#define USEP_THS_NAK 0x08 -#define USEP_THS_STALL 0x0C - -#define USEP_RTE 0x10 -#define USEP_MF 0x20 - -#define USEP_TM_CONTROL 0x00 -#define USEP_TM_INT 0x100 -#define USEP_TM_BULK 0x200 -#define USEP_TM_ISO 0x300 - -/* Command Register */ -#define USCOM_EP0 0x00 -#define USCOM_EP1 0x01 -#define USCOM_EP2 0x02 -#define USCOM_EP3 0x03 - -#define USCOM_FLUSH 0x40 -#define USCOM_STR 0x80 - -/* Event Register */ -#define USB_E_RXB 0x0001 -#define USB_E_TXB 0x0002 -#define USB_E_BSY 0x0004 -#define USB_E_SOF 0x0008 -#define USB_E_TXE1 0x0010 -#define USB_E_TXE2 0x0020 -#define USB_E_TXE3 0x0040 -#define USB_E_TXE4 0x0080 -#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4) -#define USB_E_IDLE 0x0100 -#define USB_E_RESET 0x0200 - -/* Mask Register */ -#define USBS_IDLE 0x01 - -/* RX Buffer Descriptor */ -#define RX_BD_OV 0x02 -#define RX_BD_CR 0x04 -#define RX_BD_AB 0x08 -#define RX_BD_NO 0x10 -#define RX_BD_PID_DATA0 0x00 -#define RX_BD_PID_DATA1 0x40 -#define RX_BD_PID_SETUP 0x80 -#define RX_BD_F 0x400 -#define RX_BD_L 0x800 -#define RX_BD_I 0x1000 -#define RX_BD_W 0x2000 -#define RX_BD_E 0x8000 - -/* Useful masks */ -#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP) -#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL) -#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK) -#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF) - -/* TX Buffer Descriptor */ -#define TX_BD_UN 0x02 -#define TX_BD_TO 0x04 -#define TX_BD_NO_PID 0x00 -#define TX_BD_PID_DATA0 0x80 -#define TX_BD_PID_DATA1 0xC0 -#define TX_BD_CNF 0x200 -#define TX_BD_TC 0x400 -#define TX_BD_L 0x800 -#define TX_BD_I 0x1000 -#define TX_BD_W 0x2000 -#define TX_BD_R 0x8000 - -/* Implementation specific defines */ - -#define EP_MIN_PACKET_SIZE 0x08 -#define MAX_ENDPOINTS 0x04 -#define FIFO_SIZE 0x10 -#define EP_MAX_PKT FIFO_SIZE -#define TX_RING_SIZE 0x04 -#define RX_RING_SIZE 0x06 -#define USB_MAX_PKT 0x40 -#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80 -#define TOGGLE_RX_PID(x) x^= 0x40 -#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */ -#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */ - -#define PROFF_USB 0x00000000 -#define CPM_USB_BASE 0x00000A00 - -/* UDC device defines */ -#define EP0_MAX_PACKET_SIZE EP_MAX_PKT - -#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE -#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE - -struct mpc8xx_ep { - struct urb * urb; - unsigned char pid; - unsigned char sc; - volatile cbd_t * prx; -}; - -typedef struct mpc8xx_usb{ - char usmod; /* Mode Register */ - char usaddr; /* Slave Address Register */ - char uscom; /* Command Register */ - char res1; /* Reserved */ - ushort usep[4]; - ulong res2; /* Reserved */ - ushort usber; /* Event Register */ - ushort res3; /* Reserved */ - ushort usbmr; /* Mask Register */ - char res4; /* Reserved */ - char usbs; /* Status Register */ - char res5[8]; /* Reserved */ -}usb_t; - -typedef struct mpc8xx_parameter_ram{ - ushort ep0ptr; /* Endpoint Pointer Register 0 */ - ushort ep1ptr; /* Endpoint Pointer Register 1 */ - ushort ep2ptr; /* Endpoint Pointer Register 2 */ - ushort ep3ptr; /* Endpoint Pointer Register 3 */ - uint rstate; /* Receive state */ - uint rptr; /* Receive internal data pointer */ - ushort frame_n; /* Frame number */ - ushort rbcnt; /* Receive byte count */ - uint rtemp; /* Receive temp cp use only */ - uint rxusb; /* Rx Data Temp */ - ushort rxuptr; /* Rx microcode return address temp */ -}usb_pram_t; - -typedef struct endpoint_parameter_block_pointer{ - ushort rbase; /* RxBD base address */ - ushort tbase; /* TxBD base address */ - char rfcr; /* Rx Function code */ - char tfcr; /* Tx Function code */ - ushort mrblr; /* Maximum Receive Buffer Length */ - ushort rbptr; /* RxBD pointer Next Buffer Descriptor */ - ushort tbptr; /* TxBD pointer Next Buffer Descriptor */ - ulong tstate; /* Transmit internal state */ - ulong tptr; /* Transmit internal data pointer */ - ushort tcrc; /* Transmit temp CRC */ - ushort tbcnt; /* Transmit internal bye count */ - ulong ttemp; /* Tx temp */ - ushort txuptr; /* Tx microcode return address */ - ushort res1; /* Reserved */ -}usb_epb_t; - -typedef enum mpc8xx_udc_state{ - STATE_NOT_READY, - STATE_ERROR, - STATE_READY, -}mpc8xx_udc_state_t; - diff --git a/qemu/roms/u-boot/include/usb/omap1510_udc.h b/qemu/roms/u-boot/include/usb/omap1510_udc.h deleted file mode 100644 index adfbf5499..000000000 --- a/qemu/roms/u-boot/include/usb/omap1510_udc.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2003 - * Gerry Hamel, geh@ti.com, Texas Instruments - * - * Based on - * linux/drivers/usb/device/bi/omap.h - * Register definitions for TI OMAP1510 USB bus interface driver - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __USBDCORE_OMAP1510_H__ -#define __USBDCORE_OMAP1510_H__ - - -/* - * 13.2 MPU Register Map - */ - -/* Table 13-1. USB Function Module Registers (endpoint) */ -#define UDC_BASE 0xFFFB4000 -#define UDC_OFFSET(offset) (UDC_BASE + (offset)) -#define UDC_REV UDC_OFFSET(0x0) /* Revision */ -#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */ -#define UDC_DATA UDC_OFFSET(0x08) /* Data */ -#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */ -#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */ -#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */ -#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */ -#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */ -#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */ -#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */ -#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */ -#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */ -#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */ -#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */ -#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */ - -/* IRQ_EN register fields */ -#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */ -#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */ -#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */ -#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */ -#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */ - -/* IRQ_SRC register fields */ -#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */ -#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */ -#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */ -#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */ -#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */ -#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */ -#define UDC_DS_Chg (1 << 3) /* Device state changed */ -#define UDC_Setup (1 << 2) /* Setup transaction */ -#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */ -#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */ - -/* DEVSTAT register fields, 14.2.9 */ -#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */ -#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */ -#define UDC_SUS (1 << 4) /* Suspended state */ -#define UDC_CFG (1 << 3) /* Configured state */ -#define UDC_ADD (1 << 2) /* Addressed state */ -#define UDC_DEF (1 << 1) /* Default state */ -#define UDC_ATT (1 << 0) /* Attached state */ - -/* SYSCON1 register fields */ -#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */ -#define UDC_Nak_En (1 << 4) /* NAK enable */ -#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */ -#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */ -#define UDC_Pullup_En (1 << 0) /* External pullup enabled */ - -/* SYSCON2 register fields */ -#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */ -#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */ -#define UDC_Dev_Cfg (1 << 3) /* Device configured */ -#define UDC_Clr_Cfg (1 << 2) /* Clear configured */ - -/* - * Select and enable endpoints - */ - -/* Table 13-1. USB Function Module Registers (endpoint configuration) */ -#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */ -#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */ -#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */ -#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4) -#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */ -#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4) - -/* EP_NUM register fields */ -#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */ -#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */ -#define UDC_EP_Dir (1 << 4) /* Endpoint direction */ - -/* CTRL register fields */ -#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */ -#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */ -#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */ -#define UDC_Clr_EP (1 << 1) /* Clear endpoint */ -#define UDC_Reset_EP (1 << 0) /* Reset endpoint */ - -/* STAT_FLG register fields */ -#define UDC_Miss_In (1 << 14) -#define UDC_Data_Flush (1 << 13) -#define UDC_ISO_Err (1 << 12) -#define UDC_ISO_FIFO_Empty (1 << 9) -#define UDC_ISO_FIFO_Full (1 << 8) -#define UDC_EP_Halted (1 << 6) -#define UDC_STALL (1 << 5) -#define UDC_NAK (1 << 4) -#define UDC_ACK (1 << 3) -#define UDC_FIFO_En (1 << 2) -#define UDC_Non_ISO_FIFO_Empty (1 << 1) -#define UDC_Non_ISO_FIFO_Full (1 << 0) - -/* EPn_RX register fields */ -#define UDC_EPn_RX_Valid (1 << 15) /* valid */ -#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */ -#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */ - -/* EPn_TX register fields */ -#define UDC_EPn_TX_Valid (1 << 15) /* valid */ -#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */ -#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */ - -#define EP0_PACKETSIZE 0x40 - -/* physical to logical endpoint mapping - * Physical endpoints are an index into device->bus->endpoint_array. - * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in - * the USB specification. - * - * physical ep logical ep direction endpoint_address - * 0 0 IN and OUT 0x00 - * 1 to 15 1 to 15 OUT 0x01 to 0x0f - * 16 to 30 1 to 15 IN 0x81 to 0x8f - */ -#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80)) -#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a)) - -/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */ -#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17) - -/* Other registers (may be) related to USB */ - -#define CLOCK_CTRL (0xFFFE0830) -#define APLL_CTRL (0xFFFE084C) -#define DPLL_CTRL (0xFFFE083C) -#define SOFT_REQ (0xFFFE0834) -#define STATUS_REQ (0xFFFE0840) - -/* FUNC_MUX_CTRL_0 bits related to USB */ -#define UDC_VBUS_CTRL (1 << 19) -#define UDC_VBUS_MODE (1 << 18) - -/* OMAP Endpoint parameters */ -#define UDC_OUT_PACKET_SIZE 64 -#define UDC_IN_PACKET_SIZE 64 -#define UDC_INT_PACKET_SIZE 16 -#define UDC_BULK_PACKET_SIZE 16 - -#define UDC_INT_ENDPOINT 5 -#define UDC_OUT_ENDPOINT 2 -#define UDC_IN_ENDPOINT 1 - -#endif diff --git a/qemu/roms/u-boot/include/usb/pxa27x_udc.h b/qemu/roms/u-boot/include/usb/pxa27x_udc.h deleted file mode 100644 index 7eaa00030..000000000 --- a/qemu/roms/u-boot/include/usb/pxa27x_udc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * PXA27x register declarations and HCD data structures - * - * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it> - * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __PXA270X_UDC_H__ -#define __PXA270X_UDC_H__ - -#include <asm/byteorder.h> - -/* Endpoint 0 states */ -#define EP0_IDLE 0 -#define EP0_IN_DATA 1 -#define EP0_OUT_DATA 2 -#define EP0_XFER_COMPLETE 3 - - -/* Endpoint parameters */ -#define MAX_ENDPOINTS 4 - -#define EP0_MAX_PACKET_SIZE 16 - -#define UDC_OUT_ENDPOINT 0x02 -#define UDC_IN_ENDPOINT 0x01 -#define UDC_INT_ENDPOINT 0x05 - -#endif diff --git a/qemu/roms/u-boot/include/usb/s3c_udc.h b/qemu/roms/u-boot/include/usb/s3c_udc.h deleted file mode 100644 index 70e48f88e..000000000 --- a/qemu/roms/u-boot/include/usb/s3c_udc.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * drivers/usb/gadget/s3c_udc.h - * Samsung S3C on-chip full/high speed USB device controllers - * Copyright (C) 2005 for Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __S3C_USB_GADGET -#define __S3C_USB_GADGET - -#include <asm/errno.h> -#include <linux/sizes.h> -#include <linux/usb/ch9.h> -#include <linux/usb/gadget.h> -#include <linux/list.h> -#include <usb/lin_gadget_compat.h> - -#define PHY0_SLEEP (1 << 5) - -/*-------------------------------------------------------------------------*/ -/* DMA bounce buffer size, 16K is enough even for mass storage */ -#define DMA_BUFFER_SIZE (16*SZ_1K) - -#define EP0_FIFO_SIZE 64 -#define EP_FIFO_SIZE 512 -#define EP_FIFO_SIZE2 1024 -/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */ -#define S3C_MAX_ENDPOINTS 4 -#define S3C_MAX_HW_ENDPOINTS 16 - -#define WAIT_FOR_SETUP 0 -#define DATA_STATE_XMIT 1 -#define DATA_STATE_NEED_ZLP 2 -#define WAIT_FOR_OUT_STATUS 3 -#define DATA_STATE_RECV 4 -#define WAIT_FOR_COMPLETE 5 -#define WAIT_FOR_OUT_COMPLETE 6 -#define WAIT_FOR_IN_COMPLETE 7 -#define WAIT_FOR_NULL_COMPLETE 8 - -#define TEST_J_SEL 0x1 -#define TEST_K_SEL 0x2 -#define TEST_SE0_NAK_SEL 0x3 -#define TEST_PACKET_SEL 0x4 -#define TEST_FORCE_ENABLE_SEL 0x5 - -/* ************************************************************************* */ -/* IO - */ - -enum ep_type { - ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt -}; - -struct s3c_ep { - struct usb_ep ep; - struct s3c_udc *dev; - - const struct usb_endpoint_descriptor *desc; - struct list_head queue; - unsigned long pio_irqs; - int len; - void *dma_buf; - - u8 stopped; - u8 bEndpointAddress; - u8 bmAttributes; - - enum ep_type ep_type; - int fifo_num; -}; - -struct s3c_request { - struct usb_request req; - struct list_head queue; -}; - -struct s3c_udc { - struct usb_gadget gadget; - struct usb_gadget_driver *driver; - - struct s3c_plat_otg_data *pdata; - - int ep0state; - struct s3c_ep ep[S3C_MAX_ENDPOINTS]; - - unsigned char usb_address; - - unsigned req_pending:1, req_std:1; -}; - -extern struct s3c_udc *the_controller; - -#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN) -#define ep_index(EP) ((EP)->bEndpointAddress&0xF) -#define ep_maxpacket(EP) ((EP)->ep.maxpacket) - -extern void otg_phy_init(struct s3c_udc *dev); -extern void otg_phy_off(struct s3c_udc *dev); - -extern void s3c_udc_ep_set_stall(struct s3c_ep *ep); -extern int s3c_udc_probe(struct s3c_plat_otg_data *pdata); - -struct s3c_plat_otg_data { - int (*phy_control)(int on); - unsigned int regs_phy; - unsigned int regs_otg; - unsigned int usb_phy_ctrl; - unsigned int usb_flags; -}; -#endif diff --git a/qemu/roms/u-boot/include/usb/udc.h b/qemu/roms/u-boot/include/usb/udc.h deleted file mode 100644 index 1f545ec1b..000000000 --- a/qemu/roms/u-boot/include/usb/udc.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef USB_UDC_H -#define USB_UDC_H - -#ifndef EP0_MAX_PACKET_SIZE -#define EP0_MAX_PACKET_SIZE 64 -#endif - -#ifndef EP_MAX_PACKET_SIZE -#define EP_MAX_PACKET_SIZE 64 -#endif - -#if !defined(CONFIG_PPC) && !defined(CONFIG_OMAP1510) -/* omap1510_udc.h and mpc8xx_udc.h will set these values */ -#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE -#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE -#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE -#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE -#endif - -#define UDC_BULK_HS_PACKET_SIZE 512 - -#ifndef UDC_INT_ENDPOINT -#define UDC_INT_ENDPOINT 1 -#endif - -#ifndef UDC_OUT_ENDPOINT -#define UDC_OUT_ENDPOINT 2 -#endif - -#ifndef UDC_IN_ENDPOINT -#define UDC_IN_ENDPOINT 3 -#endif - -/* function declarations */ -int udc_init(void); -void udc_irq(void); -int udc_endpoint_write(struct usb_endpoint_instance *endpoint); -void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *endpoint); -void udc_connect(void); -void udc_disconnect(void); -void udc_enable(struct usb_device_instance *device); -void udc_disable(void); -void udc_startup_events(struct usb_device_instance *device); - -/* Flow control */ -void udc_set_nak(int epid); -void udc_unset_nak(int epid); - -#endif diff --git a/qemu/roms/u-boot/include/usb/ulpi.h b/qemu/roms/u-boot/include/usb/ulpi.h deleted file mode 100644 index 99166c44a..000000000 --- a/qemu/roms/u-boot/include/usb/ulpi.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Generic ULPI interface. - * - * Copyright (C) 2011 Jana Rapava <fermata7@gmail.com> - * Copyright (C) 2011 CompuLab, Ltd. <www.compulab.co.il> - * - * Authors: Jana Rapava <fermata7@gmail.com> - * Igor Grinberg <grinberg@compulab.co.il> - * - * Register offsets taken from: - * linux/include/linux/usb/ulpi.h - * - * Original Copyrights follow: - * Copyright (C) 2010 Nokia Corporation - * - * This software is distributed under the terms of the GNU General - * Public License ("GPL") as published by the Free Software Foundation, - * version 2 of that License. - */ - -#ifndef __USB_ULPI_H__ -#define __USB_ULPI_H__ - -#define ULPI_ERROR (1 << 8) /* overflow from any register value */ - -#ifndef CONFIG_USB_ULPI_TIMEOUT -#define CONFIG_USB_ULPI_TIMEOUT 1000 /* timeout in us */ -#endif - -/* - * ulpi view port address and - * Port_number that can be passed. - * Any additional data to be passed can - * be extended from this structure - */ -struct ulpi_viewport { - u32 viewport_addr; - u32 port_num; -}; - -/* - * Initialize the ULPI transciever and check the interface integrity. - * @ulpi_vp - structure containing ULPI viewport data - * - * returns 0 on success, ULPI_ERROR on failure. - */ -int ulpi_init(struct ulpi_viewport *ulpi_vp); - -/* - * Select transceiver speed. - * @speed - ULPI_FC_HIGH_SPEED, ULPI_FC_FULL_SPEED (default), - * ULPI_FC_LOW_SPEED, ULPI_FC_FS4LS - * returns 0 on success, ULPI_ERROR on failure. - */ -int ulpi_select_transceiver(struct ulpi_viewport *ulpi_vp, unsigned speed); - -/* - * Enable/disable VBUS. - * @ext_power - external VBUS supply is used (default is false) - * @ext_indicator - external VBUS over-current indicator is used - * - * returns 0 on success, ULPI_ERROR on failure. - */ -int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power); - -/* - * Configure VBUS indicator - * @external - external VBUS over-current indicator is used - * @passthru - disables ANDing of internal VBUS comparator - * with external VBUS input - * @complement - inverts the external VBUS input - */ -int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external, - int passthru, int complement); - -/* - * Enable/disable pull-down resistors on D+ and D- USB lines. - * - * returns 0 on success, ULPI_ERROR on failure. - */ -int ulpi_set_pd(struct ulpi_viewport *ulpi_vp, int enable); - -/* - * Select OpMode. - * @opmode - ULPI_FC_OPMODE_NORMAL (default), ULPI_FC_OPMODE_NONDRIVING, - * ULPI_FC_OPMODE_DISABLE_NRZI, ULPI_FC_OPMODE_NOSYNC_NOEOP - * - * returns 0 on success, ULPI_ERROR on failure. - */ -int ulpi_opmode_sel(struct ulpi_viewport *ulpi_vp, unsigned opmode); - -/* - * Switch to Serial Mode. - * @smode - ULPI_IFACE_6_PIN_SERIAL_MODE or ULPI_IFACE_3_PIN_SERIAL_MODE - * - * returns 0 on success, ULPI_ERROR on failure. - * - * Notes: - * Switches immediately to Serial Mode. - * To return from Serial Mode, STP line needs to be asserted. - */ -int ulpi_serial_mode_enable(struct ulpi_viewport *ulpi_vp, unsigned smode); - -/* - * Put PHY into low power mode. - * - * returns 0 on success, ULPI_ERROR on failure. - * - * Notes: - * STP line must be driven low to keep the PHY in suspend. - * To resume the PHY, STP line needs to be asserted. - */ -int ulpi_suspend(struct ulpi_viewport *ulpi_vp); - -/* - * Reset the transceiver. ULPI interface and registers are not affected. - * - * returns 0 on success, ULPI_ERROR on failure. - */ -int ulpi_reset(struct ulpi_viewport *ulpi_vp); - - -/* ULPI access methods below must be implemented for each ULPI viewport. */ - -/* - * Write to the ULPI PHY register via the viewport. - * @reg - the ULPI register (one of the fields in struct ulpi_regs). - * @value - the value - only 8 lower bits are used, others ignored. - * - * returns 0 on success, ULPI_ERROR on failure. - */ -int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value); - -/* - * Read the ULPI PHY register content via the viewport. - * @reg - the ULPI register (one of the fields in struct ulpi_regs). - * - * returns register content on success, ULPI_ERROR on failure. - */ -u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg); - -/* - * Wait for the reset to complete. - * The Link must not attempt to access the PHY until the reset has - * completed and DIR line is de-asserted. - */ -int ulpi_reset_wait(struct ulpi_viewport *ulpi_vp); - -/* Access Extended Register Set (indicator) */ -#define ACCESS_EXT_REGS_OFFSET 0x2f /* read-write */ -/* Vendor-specific */ -#define VENDOR_SPEC_OFFSET 0x30 - -/* - * Extended Register Set - * - * Addresses 0x00-0x3F map directly to Immediate Register Set. - * Addresses 0x40-0x7F are reserved. - * Addresses 0x80-0xff are vendor-specific. - */ -#define EXT_VENDOR_SPEC_OFFSET 0x80 - -/* ULPI registers, bits and offsets definitions */ -struct ulpi_regs { - /* Vendor ID and Product ID: 0x00 - 0x03 Read-only */ - u8 vendor_id_low; - u8 vendor_id_high; - u8 product_id_low; - u8 product_id_high; - /* Function Control: 0x04 - 0x06 Read */ - u8 function_ctrl; /* 0x04 Write */ - u8 function_ctrl_set; /* 0x05 Set */ - u8 function_ctrl_clear; /* 0x06 Clear */ - /* Interface Control: 0x07 - 0x09 Read */ - u8 iface_ctrl; /* 0x07 Write */ - u8 iface_ctrl_set; /* 0x08 Set */ - u8 iface_ctrl_clear; /* 0x09 Clear */ - /* OTG Control: 0x0A - 0x0C Read */ - u8 otg_ctrl; /* 0x0A Write */ - u8 otg_ctrl_set; /* 0x0B Set */ - u8 otg_ctrl_clear; /* 0x0C Clear */ - /* USB Interrupt Enable Rising: 0x0D - 0x0F Read */ - u8 usb_ie_rising; /* 0x0D Write */ - u8 usb_ie_rising_set; /* 0x0E Set */ - u8 usb_ie_rising_clear; /* 0x0F Clear */ - /* USB Interrupt Enable Falling: 0x10 - 0x12 Read */ - u8 usb_ie_falling; /* 0x10 Write */ - u8 usb_ie_falling_set; /* 0x11 Set */ - u8 usb_ie_falling_clear; /* 0x12 Clear */ - /* USB Interrupt Status: 0x13 Read-only */ - u8 usb_int_status; - /* USB Interrupt Latch: 0x14 Read-only with auto-clear */ - u8 usb_int_latch; - /* Debug: 0x15 Read-only */ - u8 debug; - /* Scratch Register: 0x16 - 0x18 Read */ - u8 scratch; /* 0x16 Write */ - u8 scratch_set; /* 0x17 Set */ - u8 scratch_clear; /* 0x18 Clear */ - /* - * Optional Carkit registers: - * Carkit Control: 0x19 - 0x1B Read - */ - u8 carkit_ctrl; /* 0x19 Write */ - u8 carkit_ctrl_set; /* 0x1A Set */ - u8 carkit_ctrl_clear; /* 0x1B Clear */ - /* Carkit Interrupt Delay: 0x1C Read, Write */ - u8 carkit_int_delay; - /* Carkit Interrupt Enable: 0x1D - 0x1F Read */ - u8 carkit_ie; /* 0x1D Write */ - u8 carkit_ie_set; /* 0x1E Set */ - u8 carkit_ie_clear; /* 0x1F Clear */ - /* Carkit Interrupt Status: 0x20 Read-only */ - u8 carkit_int_status; - /* Carkit Interrupt Latch: 0x21 Read-only with auto-clear */ - u8 carkit_int_latch; - /* Carkit Pulse Control: 0x22 - 0x24 Read */ - u8 carkit_pulse_ctrl; /* 0x22 Write */ - u8 carkit_pulse_ctrl_set; /* 0x23 Set */ - u8 carkit_pulse_ctrl_clear; /* 0x24 Clear */ - /* - * Other optional registers: - * Transmit Positive Width: 0x25 Read, Write - */ - u8 transmit_pos_width; - /* Transmit Negative Width: 0x26 Read, Write */ - u8 transmit_neg_width; - /* Receive Polarity Recovery: 0x27 Read, Write */ - u8 recv_pol_recovery; - /* - * Addresses 0x28 - 0x2E are reserved, so we use offsets - * for immediate registers with higher addresses - */ -}; - -/* - * Register Bits - */ - -/* Function Control */ -#define ULPI_FC_XCVRSEL_MASK (3 << 0) -#define ULPI_FC_HIGH_SPEED (0 << 0) -#define ULPI_FC_FULL_SPEED (1 << 0) -#define ULPI_FC_LOW_SPEED (2 << 0) -#define ULPI_FC_FS4LS (3 << 0) -#define ULPI_FC_TERMSELECT (1 << 2) -#define ULPI_FC_OPMODE_MASK (3 << 3) -#define ULPI_FC_OPMODE_NORMAL (0 << 3) -#define ULPI_FC_OPMODE_NONDRIVING (1 << 3) -#define ULPI_FC_OPMODE_DISABLE_NRZI (2 << 3) -#define ULPI_FC_OPMODE_NOSYNC_NOEOP (3 << 3) -#define ULPI_FC_RESET (1 << 5) -#define ULPI_FC_SUSPENDM (1 << 6) - -/* Interface Control */ -#define ULPI_IFACE_6_PIN_SERIAL_MODE (1 << 0) -#define ULPI_IFACE_3_PIN_SERIAL_MODE (1 << 1) -#define ULPI_IFACE_CARKITMODE (1 << 2) -#define ULPI_IFACE_CLOCKSUSPENDM (1 << 3) -#define ULPI_IFACE_AUTORESUME (1 << 4) -#define ULPI_IFACE_EXTVBUS_COMPLEMENT (1 << 5) -#define ULPI_IFACE_PASSTHRU (1 << 6) -#define ULPI_IFACE_PROTECT_IFC_DISABLE (1 << 7) - -/* OTG Control */ -#define ULPI_OTG_ID_PULLUP (1 << 0) -#define ULPI_OTG_DP_PULLDOWN (1 << 1) -#define ULPI_OTG_DM_PULLDOWN (1 << 2) -#define ULPI_OTG_DISCHRGVBUS (1 << 3) -#define ULPI_OTG_CHRGVBUS (1 << 4) -#define ULPI_OTG_DRVVBUS (1 << 5) -#define ULPI_OTG_DRVVBUS_EXT (1 << 6) -#define ULPI_OTG_EXTVBUSIND (1 << 7) - -/* - * USB Interrupt Enable Rising, - * USB Interrupt Enable Falling, - * USB Interrupt Status and - * USB Interrupt Latch - */ -#define ULPI_INT_HOST_DISCONNECT (1 << 0) -#define ULPI_INT_VBUS_VALID (1 << 1) -#define ULPI_INT_SESS_VALID (1 << 2) -#define ULPI_INT_SESS_END (1 << 3) -#define ULPI_INT_IDGRD (1 << 4) - -/* Debug */ -#define ULPI_DEBUG_LINESTATE0 (1 << 0) -#define ULPI_DEBUG_LINESTATE1 (1 << 1) - -/* Carkit Control */ -#define ULPI_CARKIT_CTRL_CARKITPWR (1 << 0) -#define ULPI_CARKIT_CTRL_IDGNDDRV (1 << 1) -#define ULPI_CARKIT_CTRL_TXDEN (1 << 2) -#define ULPI_CARKIT_CTRL_RXDEN (1 << 3) -#define ULPI_CARKIT_CTRL_SPKLEFTEN (1 << 4) -#define ULPI_CARKIT_CTRL_SPKRIGHTEN (1 << 5) -#define ULPI_CARKIT_CTRL_MICEN (1 << 6) - -/* Carkit Interrupt Enable */ -#define ULPI_CARKIT_INT_EN_IDFLOAT_RISE (1 << 0) -#define ULPI_CARKIT_INT_EN_IDFLOAT_FALL (1 << 1) -#define ULPI_CARKIT_INT_EN_CARINTDET (1 << 2) -#define ULPI_CARKIT_INT_EN_DP_RISE (1 << 3) -#define ULPI_CARKIT_INT_EN_DP_FALL (1 << 4) - -/* Carkit Interrupt Status and Latch */ -#define ULPI_CARKIT_INT_IDFLOAT (1 << 0) -#define ULPI_CARKIT_INT_CARINTDET (1 << 1) -#define ULPI_CARKIT_INT_DP (1 << 2) - -/* Carkit Pulse Control*/ -#define ULPI_CARKIT_PLS_CTRL_TXPLSEN (1 << 0) -#define ULPI_CARKIT_PLS_CTRL_RXPLSEN (1 << 1) -#define ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2) -#define ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN (1 << 3) - - -#endif /* __USB_ULPI_H__ */ |