4 files changed, 0 insertions, 313 deletions

diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/Makefile b/qemu/roms/u-boot/board/samsung/smdkc100/Makefile
deleted file mode 100644
index 0bcf4e5de..000000000
--- a/qemu/roms/u-boot/board/samsung/smdkc100/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= smdkc100.o
-obj-$(CONFIG_SAMSUNG_ONENAND)	+= onenand.o
-obj-y	+= lowlevel_init.o
diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S b/qemu/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S
deleted file mode 100644
index 65e6b7a73..000000000
--- a/qemu/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/power.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- */
-
-	.globl lowlevel_init
-lowlevel_init:
-	mov	r9, lr
-
-	/* r5 has always zero */
-	mov	r5, #0
-
-	ldr	r8, =S5PC100_GPIO_BASE
-
-	/* Disable Watchdog */
-	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
-	orr	r0, r0, #0x0
-	str	r5, [r0]
-
-	/* setting SRAM */
-	ldr	r0, =S5PC100_SROMC_BASE
-	ldr	r1, =0x9
-	str	r1, [r0]
-
-	/* S5PC100 has 3 groups of interrupt sources */
-	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
-	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
-	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
-
-	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
-	mvn	r3, #0x0
-	str	r3, [r0, #0x14]				@INTENCLEAR
-	str	r3, [r1, #0x14]				@INTENCLEAR
-	str	r3, [r2, #0x14]				@INTENCLEAR
-
-	/* Set all interrupts as IRQ */
-	str	r5, [r0, #0xc]				@INTSELECT
-	str	r5, [r1, #0xc]				@INTSELECT
-	str	r5, [r2, #0xc]				@INTSELECT
-
-	/* Pending Interrupt Clear */
-	str	r5, [r0, #0xf00]			@INTADDRESS
-	str	r5, [r1, #0xf00]			@INTADDRESS
-	str	r5, [r2, #0xf00]			@INTADDRESS
-
-	/* for UART */
-	bl uart_asm_init
-
-	/* for TZPC */
-	bl tzpc_asm_init
-
-1:
-	mov	lr, r9
-	mov	pc, lr
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
-	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
-
-	/* Set Clock divider */
-	ldr	r1, =0x00011110
-	str	r1, [r8, #0x304]
-	ldr	r1, =0x1
-	str	r1, [r8, #0x308]
-	ldr	r1, =0x00011301
-	str	r1, [r8, #0x300]
-
-	/* Set Lock Time */
-	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
-	str	r1, [r8, #0x000]		@ APLL_LOCK
-	str	r1, [r8, #0x004]		@ MPLL_LOCK
-	str	r1, [r8, #0x008]		@ EPLL_LOCK
-	str	r1, [r8, #0x00C]		@ HPLL_LOCK
-
-	/* APLL_CON */
-	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
-	str	r1, [r8, #0x100]
-	/* MPLL_CON */
-	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
-	str	r1, [r8, #0x104]
-	/* EPLL_CON */
-	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
-	str	r1, [r8, #0x108]
-	/* HPLL_CON */
-	ldr	r1, =0x80600603
-	str	r1, [r8, #0x10C]
-
-	/* Set Source Clock */
-	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
-	str	r1, [r8, #0x200]		@ CLK_SRC0
-
-	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
-	str	r1, [r8, #0x204]		@ CLK_SRC1
-
-	ldr	r1, =0x9000			@ ARMCLK/4
-	str	r1, [r8, #0x400]		@ CLK_OUT
-
-	/* wait at least 200us to stablize all clock */
-	mov	r2, #0x10000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	mov	pc, lr
-
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
-	mov	r0, r8
-	ldr	r1, =0x22222222
-	str	r1, [r0, #0x0]			@ GPA0_CON
-	ldr	r1, =0x00022222
-	str	r1, [r0, #0x20]			@ GPA1_CON
-
-	mov	pc, lr
-
-/*
- * tzpc_asm_init: Initialize TZPC
- */
-tzpc_asm_init:
-	ldr	r0, =0xE3800000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x804]
-	str	r1, [r0, #0x810]
-
-	ldr	r0, =0xE2800000
-	str	r1, [r0, #0x804]
-	str	r1, [r0, #0x810]
-	str	r1, [r0, #0x81C]
-
-	ldr	r0, =0xE2900000
-	str	r1, [r0, #0x804]
-	str	r1, [r0, #0x810]
-
-	mov	pc, lr
diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/onenand.c b/qemu/roms/u-boot/board/samsung/smdkc100/onenand.c
deleted file mode 100644
index 577c1a546..000000000
--- a/qemu/roms/u-boot/board/samsung/smdkc100/onenand.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/compat.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/onenand.h>
-#include <linux/mtd/samsung_onenand.h>
-
-#include <onenand_uboot.h>
-
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-void onenand_board_init(struct mtd_info *mtd)
-{
-	struct onenand_chip *this = mtd->priv;
-	struct s5pc100_clock *clk =
-			(struct s5pc100_clock *)samsung_get_base_clock();
-	struct samsung_onenand *onenand;
-	int value;
-
-	this->base = (void *)S5PC100_ONENAND_BASE;
-	onenand = (struct samsung_onenand *)this->base;
-
-	/* D0 Domain memory clock gating */
-	value = readl(&clk->gate_d01);
-	value &= ~(1 << 2);		/* CLK_ONENANDC */
-	value |= (1 << 2);
-	writel(value, &clk->gate_d01);
-
-	value = readl(&clk->src0);
-	value &= ~(1 << 24);		/* MUX_1nand: 0 from HCLKD0 */
-	value &= ~(1 << 20);		/* MUX_HREF: 0 from FIN_27M */
-	writel(value, &clk->src0);
-
-	value = readl(&clk->div1);
-	value &= ~(3 << 16);		/* PCLKD1_RATIO */
-	value |= (1 << 16);
-	writel(value, &clk->div1);
-
-	writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
-
-	while (!(readl(&onenand->int_err_stat) & RST_CMP))
-		continue;
-
-	writel(RST_CMP, &onenand->int_err_ack);
-
-	/*
-	 * Access_Clock [2:0]
-	 * 166 MHz, 134 Mhz : 3
-	 * 100 Mhz, 60 Mhz  : 2
-	 */
-	writel(0x3, &onenand->acc_clock);
-
-	writel(INT_ERR_ALL, &onenand->int_err_mask);
-	writel(1 << 0, &onenand->int_pin_en);	/* Enable */
-
-	value = readl(&onenand->int_err_mask);
-	value &= ~RDY_ACT;
-	writel(value, &onenand->int_err_mask);
-
-	s3c_onenand_init(mtd);
-}
diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/smdkc100.c b/qemu/roms/u-boot/board/samsung/smdkc100/smdkc100.c
deleted file mode 100644
index 860c851b2..000000000
--- a/qemu/roms/u-boot/board/samsung/smdkc100/smdkc100.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  Copyright (C) 2008-2009 Samsung Electronics
- *  Minkyu Kang <mk7.kang@samsung.com>
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sromc.h>
-#include <asm/arch/gpio.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-static void smc9115_pre_init(void)
-{
-	u32 smc_bw_conf, smc_bc_conf;
-
-	struct s5pc100_gpio *const gpio =
-		(struct s5pc100_gpio *)samsung_get_base_gpio();
-
-	/* gpio configuration GPK0CON */
-	s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
-
-	/* Ethernet needs bus width of 16 bits */
-	smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
-	smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
-			| SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
-			| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
-
-	/* Select and configure the SROMC bank */
-	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
-}
-
-int board_init(void)
-{
-	smc9115_pre_init();
-
-	gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	printf("Board:\tSMDKC100\n");
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}