diff options
Diffstat (limited to 'qemu/roms/u-boot/board/renesas')
63 files changed, 0 insertions, 11057 deletions
diff --git a/qemu/roms/u-boot/board/renesas/MigoR/Makefile b/qemu/roms/u-boot/board/renesas/MigoR/Makefile deleted file mode 100644 index b4691a116..000000000 --- a/qemu/roms/u-boot/board/renesas/MigoR/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# board/MigoR/Makefile -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := migo_r.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/MigoR/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/MigoR/lowlevel_init.S deleted file mode 100644 index 63ea70aa3..000000000 --- a/qemu/roms/u-boot/board/renesas/MigoR/lowlevel_init.S +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2007-2008 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/lowlevel_init.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> - -#include <asm/processor.h> -#include <asm/macro.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - write32 CCR_A, CCR_D ! Address of Cache Control Register - ! Instruction Cache Invalidate - - write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register - ! TI == TLB Invalidate bit - - write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 - - write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 - - write16 PFC_PULCR_A, PFC_PULCR_D - - write16 PFC_DRVCR_A, PFC_DRVCR_D - - write16 SBSCR_A, SBSCR_D - - write16 PSCR_A, PSCR_D - - write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) - ! 0xA507 -> timer_STOP / WDT_CLK = max - - write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) - ! 0x5A00 -> Clear - - write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) - ! 0xA504 -> timer_STOP / CLK = 500ms - - write32 DLLFRQ_A, DLLFRQ_D ! 20080115 - ! 20080115 - - write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register - ! 20080115 - - write32 CCR_A, CCR_D_2 ! Address of Cache Control Register - ! ?? - -bsc_init: - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5ABCR_A, CS5ABCR_D - - write32 CS5BBCR_A, CS5BBCR_D - - write32 CS6ABCR_A, CS6ABCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5AWCR_A, CS5AWCR_D - - write32 CS5BWCR_A, CS5BWCR_D - - write32 CS6AWCR_A, CS6AWCR_D - - ! SDRAM initialization - write32 SDCR_A, SDCR_D - - write32 SDWCR_A, SDWCR_D - - write32 SDPCR_A, SDPCR_D - - write32 RTCOR_A, RTCOR_D - - write32 RTCNT_A, RTCNT_D - - write32 RTCSR_A, RTCSR_D - - write32 RFCR_A, RFCR_D - - write8 SDMR3_A, SDMR3_D - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 4 - -CCR_A: .long CCR -MMUCR_A: .long MMUCR -MSTPCR0_A: .long MSTPCR0 -MSTPCR2_A: .long MSTPCR2 -PFC_PULCR_A: .long PULCR -PFC_DRVCR_A: .long DRVCR -SBSCR_A: .long SBSCR -PSCR_A: .long PSCR -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -PLLCR_A: .long PLLCR -DLLFRQ_A: .long DLLFRQ - -CCR_D: .long 0x00000800 -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff -PFC_PULCR_D: .long 0x6000 -PFC_DRVCR_D: .long 0x0464 -FRQCR_D: .long 0x07033639 -PLLCR_D: .long 0x00005000 -DLLFRQ_D: .long 0x000004F6 - -CMNCR_A: .long CMNCR -CMNCR_D: .long 0x0000001B -CS0BCR_A: .long CS0BCR -CS0BCR_D: .long 0x24920400 -CS4BCR_A: .long CS4BCR -CS4BCR_D: .long 0x00003400 -CS5ABCR_A: .long CS5ABCR -CS5ABCR_D: .long 0x24920400 -CS5BBCR_A: .long CS5BBCR -CS5BBCR_D: .long 0x24920400 -CS6ABCR_A: .long CS6ABCR -CS6ABCR_D: .long 0x24920400 - -CS0WCR_A: .long CS0WCR -CS0WCR_D: .long 0x00000380 -CS4WCR_A: .long CS4WCR -CS4WCR_D: .long 0x00110080 -CS5AWCR_A: .long CS5AWCR -CS5AWCR_D: .long 0x00000300 -CS5BWCR_A: .long CS5BWCR -CS5BWCR_D: .long 0x00000300 -CS6AWCR_A: .long CS6AWCR -CS6AWCR_D: .long 0x00000300 - -SDCR_A: .long SBSC_SDCR -SDCR_D: .long 0x80160809 -SDWCR_A: .long SBSC_SDWCR -SDWCR_D: .long 0x0014450C -SDPCR_A: .long SBSC_SDPCR -SDPCR_D: .long 0x00000087 -RTCOR_A: .long SBSC_RTCOR -RTCNT_A: .long SBSC_RTCNT -RTCNT_D: .long 0xA55A0012 -RTCOR_D: .long 0xA55A001C -RTCSR_A: .long SBSC_RTCSR -RFCR_A: .long SBSC_RFCR -RFCR_D: .long 0xA55A0221 -RTCSR_D: .long 0xA55A009a -SDMR3_A: .long 0xFE581180 -SDMR3_D: .long 0x0 - -SR_MASK_D: .long 0xEFFFFF0F - - .align 2 - -SBSCR_D: .word 0x0044 -PSCR_D: .word 0x0000 -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA504 -RWTCNT_D: .word 0x5A00 diff --git a/qemu/roms/u-boot/board/renesas/MigoR/migo_r.c b/qemu/roms/u-boot/board/renesas/MigoR/migo_r.c deleted file mode 100644 index fa2bf78cf..000000000 --- a/qemu/roms/u-boot/board/renesas/MigoR/migo_r.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/migo_r.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("BOARD: Renesas MigoR\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state (unsigned short value) -{ -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/qemu/roms/u-boot/board/renesas/ap325rxa/Makefile b/qemu/roms/u-boot/board/renesas/ap325rxa/Makefile deleted file mode 100644 index ff72de902..000000000 --- a/qemu/roms/u-boot/board/renesas/ap325rxa/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -######################################################################### -# -# Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -# -# board/ap325rxa/Makefile -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ap325rxa.o cpld-ap325rxa.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/ap325rxa/ap325rxa.c b/qemu/roms/u-boot/board/renesas/ap325rxa/ap325rxa.c deleted file mode 100644 index 518ad7b6a..000000000 --- a/qemu/roms/u-boot/board/renesas/ap325rxa/ap325rxa.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* PRI control register */ -#define PRPRICR5 0xFF800048 /* LMB */ -#define PRPRICR5_D 0x2a - -/* FPGA control */ -#define FPGA_NAND_CTL 0xB410020C -#define FPGA_NAND_RST 0x0008 -#define FPGA_NAND_INIT 0x0000 -#define FPGA_NAND_RST_WAIT 10000 - -/* I/O port data */ -#define PACR_D 0x0000 -#define PBCR_D 0x0000 -#define PCCR_D 0x1000 -#define PDCR_D 0x0000 -#define PECR_D 0x0410 -#define PFCR_D 0xffff -#define PGCR_D 0x0000 -#define PHCR_D 0x5011 -#define PJCR_D 0x4400 -#define PKCR_D 0x7c00 -#define PLCR_D 0x0000 -#define PMCR_D 0x0000 -#define PNCR_D 0x0000 -#define PQCR_D 0x0000 -#define PRCR_D 0x0000 -#define PSCR_D 0x0000 -#define PTCR_D 0x0010 -#define PUCR_D 0x0fff -#define PVCR_D 0xffff -#define PWCR_D 0x0000 -#define PXCR_D 0x7500 -#define PYCR_D 0x0000 -#define PZCR_D 0x5540 - -/* Pin Function Controler data */ -#define PSELA_D 0x1410 -#define PSELB_D 0x0140 -#define PSELC_D 0x0000 -#define PSELD_D 0x0400 - -/* I/O Buffer Hi-Z data */ -#define HIZCRA_D 0x0000 -#define HIZCRB_D 0x1000 -#define HIZCRC_D 0x0000 -#define HIZCRD_D 0x0000 - -/* Module select reg data */ -#define MSELCRA_D 0x0014 -#define MSELCRB_D 0x0018 - -/* Module Stop reg Data */ -#define MSTPCR2_D 0xFFD9F280 - -/* CPLD loader */ -extern void init_cpld(void); - -int checkboard(void) -{ - puts("BOARD: AP325RXA\n"); - return 0; -} - -int board_init(void) -{ - /* Pin Function Controler Init */ - outw(PSELA_D, PSELA); - outw(PSELB_D, PSELB); - outw(PSELC_D, PSELC); - outw(PSELD_D, PSELD); - - /* I/O Buffer Hi-Z Init */ - outw(HIZCRA_D, HIZCRA); - outw(HIZCRB_D, HIZCRB); - outw(HIZCRC_D, HIZCRC); - outw(HIZCRD_D, HIZCRD); - - /* Module select reg Init */ - outw(MSELCRA_D, MSELCRA); - outw(MSELCRB_D, MSELCRB); - - /* Module Stop reg Init */ - outl(MSTPCR2_D, MSTPCR2); - - /* I/O ports */ - outw(PACR_D, PACR); - outw(PBCR_D, PBCR); - outw(PCCR_D, PCCR); - outw(PDCR_D, PDCR); - outw(PECR_D, PECR); - outw(PFCR_D, PFCR); - outw(PGCR_D, PGCR); - outw(PHCR_D, PHCR); - outw(PJCR_D, PJCR); - outw(PKCR_D, PKCR); - outw(PLCR_D, PLCR); - outw(PMCR_D, PMCR); - outw(PNCR_D, PNCR); - outw(PQCR_D, PQCR); - outw(PRCR_D, PRCR); - outw(PSCR_D, PSCR); - outw(PTCR_D, PTCR); - outw(PUCR_D, PUCR); - outw(PVCR_D, PVCR); - outw(PWCR_D, PWCR); - outw(PXCR_D, PXCR); - outw(PYCR_D, PYCR); - outw(PZCR_D, PZCR); - - /* PRI control register Init */ - outl(PRPRICR5_D, PRPRICR5); - - /* cpld init */ - init_cpld(); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -void ide_set_reset(int idereset) -{ - outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ - udelay(FPGA_NAND_RST_WAIT); - outw(FPGA_NAND_INIT, FPGA_NAND_CTL); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/qemu/roms/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c b/qemu/roms/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c deleted file mode 100644 index 16fadcbca..000000000 --- a/qemu/roms/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c +++ /dev/null @@ -1,206 +0,0 @@ -/*************************************************************** - * Project: - * CPLD SlaveSerial Configuration via embedded microprocessor. - * - * Copyright info: - * - * This is free software; you can redistribute it and/or modify - * it as you like. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Description: - * - * This is the main source file that will allow a microprocessor - * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II, - * and Spartan-II devices via the SlaveSerial Configuration Mode. - * This code is discussed in Xilinx Application Note, XAPP502. - * - * History: - * 3-October-2001 MN/MP - Created - * 20-August-2008 Renesas Solutions - Modified to SH7723 - ****************************************************************/ - -#include <common.h> - -/* Serial */ -#define SCIF_BASE 0xffe00000 /* SCIF0 */ -#define SCSMR (vu_short *)(SCIF_BASE + 0x00) -#define SCBRR (vu_char *)(SCIF_BASE + 0x04) -#define SCSCR (vu_short *)(SCIF_BASE + 0x08) -#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C) -#define SC_SR (vu_short *)(SCIF_BASE + 0x10) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define RFCR (vu_long *)0xFE400020 - -#define SCSCR_INIT 0x0038 -#define SCSCR_CLR 0x0000 -#define SCFCR_INIT 0x0006 -#define SCSMR_INIT 0x0080 -#define RFCR_CLR 0xA400 -#define SCI_TD_E 0x0020 -#define SCI_TDRE_CLEAR 0x00df - -#define BPS_SETTING_VALUE 1 /* 12.5MHz */ -#define WAIT_RFCR_COUNTER 500 - -/* CPLD data size */ -#define CPLD_DATA_SIZE 169216 - -/* out */ -#define CPLD_PFC_ADR ((vu_short *)0xA4050112) - -#define CPLD_PROG_ADR ((vu_char *)0xA4050132) -#define CPLD_PROG_DAT 0x80 - -/* in */ -#define CPLD_INIT_ADR ((vu_char *)0xA4050132) -#define CPLD_INIT_DAT 0x40 -#define CPLD_DONE_ADR ((vu_char *)0xA4050132) -#define CPLD_DONE_DAT 0x20 - -#define HIZCRB ((vu_short *)0xA405015A) - -/* data */ -#define CPLD_NOMAL_START 0xA0A80000 -#define CPLD_SAFE_START 0xA0AC0000 -#define MODE_SW (vu_char *)0xA405012A - -static void init_cpld_loader(void) -{ - - *SCSCR = SCSCR_CLR; - *SCFCR = SCFCR_INIT; - *SCSMR = SCSMR_INIT; - - *SCBRR = BPS_SETTING_VALUE; - - *RFCR = RFCR_CLR; /* Refresh counter clear */ - - while (*RFCR < WAIT_RFCR_COUNTER) - ; - - *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ - /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ - *SCSCR = SCSCR_INIT; -} - -static int check_write_ready(void) -{ - u16 status = *SC_SR; - return status & SCI_TD_E; -} - -static void write_cpld_data(char ch) -{ - while (!check_write_ready()) - ; - - *SC_TDR = ch; - *SC_SR; - *SC_SR = SCI_TDRE_CLEAR; -} - -static int delay(void) -{ - int i; - int c = 0; - for (i = 0; i < 200; i++) { - c = *(volatile int *)0xa0000000; - } - return c; -} - -/*********************************************************************** - * - * Function: slave_serial - * - * Description: Initiates SlaveSerial Configuration. - * Calls ShiftDataOut() to output serial data - * - ***********************************************************************/ -static void slave_serial(void) -{ - int i; - unsigned char *flash; - - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - delay(); - - /* - * Toggle Program Pin by Toggling Program_OE bit - * This is accomplished by writing to the Program Register in the CPLD - * - * NOTE: The Program_OE bit should be driven high to bring the Virtex - * Program Pin low. Likewise, it should be driven low - * to bring the Virtex Program Pin to High-Z - */ - - *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */ - delay(); - - /* - * Bring Program High-Z - * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z - */ - - /* Program_OE bit Low brings the Virtex Program Pin to High Z: */ - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - - while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) - delay(); - - /* Begin Slave-Serial Configuration */ - flash = (unsigned char *)CPLD_NOMAL_START; - - for (i = 0; i < CPLD_DATA_SIZE; i++) - write_cpld_data(*flash++); -} - -/*********************************************************************** - * - * Function: check_done_bit - * - * Description: This function takes monitors the CPLD Input Register - * by checking the status of the DONE bit in that Register. - * By doing so, it monitors the Xilinx Virtex device's DONE - * Pin to see if configuration bitstream has been properly - * loaded - * - ***********************************************************************/ -static void check_done_bit(void) -{ - while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT)) - ; -} - -/*********************************************************************** - * - * Function: init_cpld - * - * Description: Begins Slave Serial configuration of Xilinx FPGA - * - ***********************************************************************/ -void init_cpld(void) -{ - /* Init serial device */ - init_cpld_loader(); - - if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */ - return; - - *HIZCRB = 0x0000; - *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ - - /* write CPLD data from NOR flash to device */ - slave_serial(); - - /* - * Monitor the DONE bit in the CPLD Input Register to see if - * configuration successful - */ - - check_done_bit(); -} diff --git a/qemu/roms/u-boot/board/renesas/ap325rxa/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/ap325rxa/lowlevel_init.S deleted file mode 100644 index ead5310a4..000000000 --- a/qemu/roms/u-boot/board/renesas/ap325rxa/lowlevel_init.S +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> - * - * board/ap325rxa/lowlevel_init.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - write16 DRVCRA_A, DRVCRA_D - - write16 DRVCRB_A, DRVCRB_D - - write16 RWTCSR_A, RWTCSR_D1 - - write16 RWTCNT_A, RWTCNT_D - - write16 RWTCSR_A, RWTCSR_D2 - - write32 FRQCR_A, FRQCR_D - - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5ABCR_A, CS5ABCR_D - - write32 CS5BBCR_A, CS5BBCR_D - - write32 CS6ABCR_A, CS6ABCR_D - - write32 CS6BBCR_A, CS6BBCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5AWCR_A, CS5AWCR_D - - write32 CS5BWCR_A, CS5BWCR_D - - write32 CS6AWCR_A, CS6AWCR_D - - write32 CS6BWCR_A, CS6BWCR_D - - write32 SBSC_SDCR_A, SBSC_SDCR_D1 - - write32 SBSC_SDWCR_A, SBSC_SDWCR_D - - write32 SBSC_SDPCR_A, SBSC_SDPCR_D - - write32 SBSC_RTCSR_A, SBSC_RTCSR_D - - write32 SBSC_RTCNT_A, SBSC_RTCNT_D - - write32 SBSC_RTCOR_A, SBSC_RTCOR_D - - write8 SBSC_SDMR3_A1, SBSC_SDMR3_D - - write8 SBSC_SDMR3_A2, SBSC_SDMR3_D - - mov.l SLEEP_CNT, r1 -2: tst r1, r1 - nop - bf/s 2b - dt r1 - - write8 SBSC_SDMR3_A3, SBSC_SDMR3_D - - write32 SBSC_SDCR_A, SBSC_SDCR_D2 - - write32 CCR_A, CCR_D - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 2 - -DRVCRA_A: .long DRVCRA -DRVCRB_A: .long DRVCRB -DRVCRA_D: .word 0x4555 -DRVCRB_D: .word 0x0005 - -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -RWTCSR_D1: .word 0xa507 -RWTCSR_D2: .word 0xa504 -RWTCNT_D: .word 0x5a00 -.align 2 -FRQCR_D: .long 0x0b04474a - -SBSC_SDCR_A: .long SBSC_SDCR -SBSC_SDWCR_A: .long SBSC_SDWCR -SBSC_SDPCR_A: .long SBSC_SDPCR -SBSC_RTCSR_A: .long SBSC_RTCSR -SBSC_RTCNT_A: .long SBSC_RTCNT -SBSC_RTCOR_A: .long SBSC_RTCOR -SBSC_SDMR3_A1: .long 0xfe510000 -SBSC_SDMR3_A2: .long 0xfe500242 -SBSC_SDMR3_A3: .long 0xfe5c0042 - -SBSC_SDCR_D1: .long 0x92810112 -SBSC_SDCR_D2: .long 0x92810912 -SBSC_SDWCR_D: .long 0x05162482 -SBSC_SDPCR_D: .long 0x00300087 -SBSC_RTCSR_D: .long 0xa55a0212 -SBSC_RTCNT_D: .long 0xa55a0000 -SBSC_RTCOR_D: .long 0xa55a0040 -SBSC_SDMR3_D: .long 0x00 - -CMNCR_A: .long CMNCR -CS0BCR_A: .long CS0BCR -CS4BCR_A: .long CS4BCR -CS5ABCR_A: .long CS5ABCR -CS5BBCR_A: .long CS5BBCR -CS6ABCR_A: .long CS6ABCR -CS6BBCR_A: .long CS6BBCR -CS0WCR_A: .long CS0WCR -CS4WCR_A: .long CS4WCR -CS5AWCR_A: .long CS5AWCR -CS5BWCR_A: .long CS5BWCR -CS6AWCR_A: .long CS6AWCR -CS6BWCR_A: .long CS6BWCR - -CMNCR_D: .long 0x00000013 -CS0BCR_D: .long 0x24920400 -CS4BCR_D: .long 0x24920400 -CS5ABCR_D: .long 0x24920400 -CS5BBCR_D: .long 0x7fff0600 -CS6ABCR_D: .long 0x24920400 -CS6BBCR_D: .long 0x24920600 -CS0WCR_D: .long 0x00000480 -CS4WCR_D: .long 0x00000480 -CS5AWCR_D: .long 0x00000380 -CS5BWCR_D: .long 0x00000080 -CS6AWCR_D: .long 0x00000300 -CS6BWCR_D: .long 0x00000540 - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090d - -SLEEP_CNT: .long 0x00000800 -SR_MASK_D: .long 0xEFFFFF0F diff --git a/qemu/roms/u-boot/board/renesas/ecovec/Makefile b/qemu/roms/u-boot/board/renesas/ecovec/Makefile deleted file mode 100644 index 943fa4760..000000000 --- a/qemu/roms/u-boot/board/renesas/ecovec/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := ecovec.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/ecovec/ecovec.c b/qemu/roms/u-boot/board/renesas/ecovec/ecovec.c deleted file mode 100644 index 2804d9133..000000000 --- a/qemu/roms/u-boot/board/renesas/ecovec/ecovec.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) 2009, 2011 Renesas Solutions Corp. - * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <i2c.h> -#include <netdev.h> - -/* USB power management register */ -#define UPONCR0 0xA40501D4 - -int checkboard(void) -{ - puts("BOARD: ecovec\n"); - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -static void debug_led(u8 led) -{ - /* PDGR[0-4] is debug LED */ - outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR); -} - -int board_late_init(void) -{ - u8 mac[6]; - char env_mac[17]; - - udelay(1000); - - /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/ - outw(inw(PLCR) & ~0xFFF0, PLCR); - outw(inw(PNCR) & ~0x000F, PNCR); - outw(inw(PXCR) & ~0x0FC0, PXCR); - outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB); - outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC); - outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE); - - debug_led(1 << 3); - - outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); - - i2c_set_bus_num(1); /* Use I2C 1 */ - - /* Read MAC address */ - i2c_read(0x50, 0x10, 0, mac, 6); - - /* Set MAC address */ - sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - setenv("ethaddr", env_mac); - - debug_led(0x0F); - - return 0; -} - -int board_init(void) -{ - - /* LED (PTG) */ - outw((inw(PGCR) & ~0xFF) | 0x55, PGCR); - outw((inw(HIZCRA) & ~0x02), HIZCRA); - - debug_led(1 << 0); - - /* SCIF0 (PTF, PTM) */ - outw(inw(PFCR) & ~0x30, PFCR); - outw(inw(PMCR) & ~0x0C, PMCR); - outw((inw(PSELA) & ~0x40) | 0x40, PSELA); - - debug_led(1 << 1); - - /* RMII (PTA) */ - outw((inw(PACR) & ~0x0C) | 0x04, PACR); - outb((inb(PADR) & ~0x02) | 0x02, PADR); - - debug_led(1 << 2); - - /* USB host */ - outw((inw(PBCR) & ~0x300) | 0x100, PBCR); - outb((inb(PBDR) & ~0x10) | 0x10, PBDR); - outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); - outw(0x0600, UPONCR0); - - debug_led(1 << 3); - - /* debug switch */ - outw((inw(PVCR) & ~0x03) | 0x02 , PVCR); - - return 0; -} diff --git a/qemu/roms/u-boot/board/renesas/ecovec/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/ecovec/lowlevel_init.S deleted file mode 100644 index e4c40c861..000000000 --- a/qemu/roms/u-boot/board/renesas/ecovec/lowlevel_init.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com> - * - * board/renesas/ecovec/lowlevel_init.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> -#include <configs/ecovec.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */ - mov.l PVDR_A, r1 - mov.l PVDR_D, r2 - mov.b @r1, r0 - tst r0, r2 - bt 1f - mov.l JUMP_A, r1 - jmp @r1 - nop - -1: - /* Disable watchdog */ - write16 RWTCSR_A, RWTCSR_D - - /* MMU Disable */ - write32 MMUCR_A, MMUCR_D - - /* Setup clocks */ - write32 PLLCR_A, PLLCR_D - write32 FRQCRA_A, FRQCRA_D - write32 FRQCRB_A, FRQCRB_D - - wait_timer TIMER_D - - write32 MMSELR_A, MMSELR_D - - /* Srtup BSC */ - write32 CMNCR_A, CMNCR_D - write32 CS0BCR_A, CS0BCR_D - write32 CS0WCR_A, CS0WCR_D - - wait_timer TIMER_D - - /* Setup SDRAM */ - write32 DBPDCNT0_A, DBPDCNT0_D0 - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBKIND_A, DBKIND_D - write32 DBCKECNT_A, DBCKECNT_D - - wait_timer TIMER_D - - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBMRCNT_A, DBMRCNT_D0 - write32 DBMRCNT_A, DBMRCNT_D1 - write32 DBMRCNT_A, DBMRCNT_D2 - write32 DBMRCNT_A, DBMRCNT_D3 - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBMRCNT_A, DBMRCNT_D4 - write32 DBMRCNT_A, DBMRCNT_D5 - write32 DBMRCNT_A, DBMRCNT_D6 - - wait_timer TIMER_D - - write32 DBEN_A, DBEN_D - write32 DBRFPDN1_A, DBRFPDN1_D - write32 DBRFPDN2_A, DBRFPDN2_D - write32 DBCMDCNT_A, DBCMDCNT_D0 - - - /* Dummy read */ - mov.l DUMMY_A ,r1 - synco - mov.l @r1, r0 - synco - - mov.l SDRAM_A ,r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBPDCNT0_A, DBPDCNT0_D1 - write32 DBRFPDN0_A, DBRFPDN0_D - - wait_timer TIMER_D - - write32 CCR_A, CCR_D - - stc sr, r0 - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - - .align 2 - -PVDR_A: .long PVDR -PVDR_D: .long 0x00000001 -JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR -TIMER_D: .long 64 -RWTCSR_A: .long RWTCSR -RWTCSR_D: .long 0x0000A507 -MMUCR_A: .long MMUCR -MMUCR_D: .long 0x00000004 -PLLCR_A: .long PLLCR -PLLCR_D: .long 0x00004000 -FRQCRA_A: .long FRQCRA -FRQCRA_D: .long 0x8E003508 -FRQCRB_A: .long FRQCRB -FRQCRB_D: .long 0x0 -MMSELR_A: .long MMSELR -MMSELR_D: .long 0xA5A50000 -CMNCR_A: .long CMNCR -CMNCR_D: .long 0x00000013 -CS0BCR_A: .long CS0BCR -CS0BCR_D: .long 0x11110400 -CS0WCR_A: .long CS0WCR -CS0WCR_D: .long 0x00000440 -DBPDCNT0_A: .long DBPDCNT0 -DBPDCNT0_D0: .long 0x00000181 -DBPDCNT0_D1: .long 0x00000080 -DBCONF_A: .long DBCONF -DBCONF_D: .long 0x015B0002 -DBTR0_A: .long DBTR0 -DBTR0_D: .long 0x03061502 -DBTR1_A: .long DBTR1 -DBTR1_D: .long 0x02020102 -DBTR2_A: .long DBTR2 -DBTR2_D: .long 0x01090305 -DBTR3_A: .long DBTR3 -DBTR3_D: .long 0x00000002 -DBKIND_A: .long DBKIND -DBKIND_D: .long 0x00000005 -DBCKECNT_A: .long DBCKECNT -DBCKECNT_D: .long 0x00000001 -DBCMDCNT_A: .long DBCMDCNT -DBCMDCNT_D0:.long 0x2 -DBCMDCNT_D1:.long 0x4 -DBMRCNT_A: .long DBMRCNT -DBMRCNT_D0: .long 0x00020000 -DBMRCNT_D1: .long 0x00030000 -DBMRCNT_D2: .long 0x00010040 -DBMRCNT_D3: .long 0x00000532 -DBMRCNT_D4: .long 0x00000432 -DBMRCNT_D5: .long 0x000103C0 -DBMRCNT_D6: .long 0x00010040 -DBEN_A: .long DBEN -DBEN_D: .long 0x01 -DBRFPDN0_A: .long DBRFPDN0 -DBRFPDN1_A: .long DBRFPDN1 -DBRFPDN2_A: .long DBRFPDN2 -DBRFPDN0_D: .long 0x00010000 -DBRFPDN1_D: .long 0x00000613 -DBRFPDN2_D: .long 0x238C003A -SDRAM_A: .long 0xa8000000 -DUMMY_A: .long 0x0c400000 -CCR_A: .long CCR -CCR_D: .long 0x0000090B -SR_MASK_D: .long 0xEFFFFF0F diff --git a/qemu/roms/u-boot/board/renesas/koelsch/Makefile b/qemu/roms/u-boot/board/renesas/koelsch/Makefile deleted file mode 100644 index b4d0183b3..000000000 --- a/qemu/roms/u-boot/board/renesas/koelsch/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# board/renesas/koelsch/Makefile -# -# Copyright (C) 2013 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0 -# - -obj-y := koelsch.o qos.o diff --git a/qemu/roms/u-boot/board/renesas/koelsch/koelsch.c b/qemu/roms/u-boot/board/renesas/koelsch/koelsch.c deleted file mode 100644 index 32d3b584b..000000000 --- a/qemu/roms/u-boot/board/renesas/koelsch/koelsch.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * board/renesas/koelsch/koelsch.c - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -#include <common.h> -#include <malloc.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/rmobile.h> -#include <netdev.h> -#include <miiphy.h> -#include <i2c.h> -#include "qos.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define s_init_wait(cnt) \ - ({ \ - u32 i = 0x10000 * cnt; \ - while (i > 0) \ - i--; \ - }) - - -#define dbpdrgd_check(bsc) \ - ({ \ - while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \ - ; \ - }) - -#if defined(CONFIG_NORFLASH) -static void bsc_init(void) -{ - struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE; - struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE; - - /* LBSC */ - writel(0x00000020, &lbsc->cs0ctrl); - writel(0x00000020, &lbsc->cs1ctrl); - writel(0x00002020, &lbsc->ecs0ctrl); - writel(0x00002020, &lbsc->ecs1ctrl); - - writel(0x077F077F, &lbsc->cswcr0); - writel(0x077F077F, &lbsc->cswcr1); - writel(0x077F077F, &lbsc->ecswcr0); - writel(0x077F077F, &lbsc->ecswcr1); - - /* DBSC3 */ - s_init_wait(10); - - writel(0x0000A55A, &dbsc3_0->dbpdlck); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x80000000, &dbsc3_0->dbpdrgd); - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000006, &dbsc3_0->dbpdrga); - writel(0x0001C000, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FD2480, &dbsc3_0->dbpdrgd); - - writel(0x00000010, &dbsc3_0->dbpdrga); - writel(0xF004649B, &dbsc3_0->dbpdrgd); - - writel(0x0000000F, &dbsc3_0->dbpdrga); - writel(0x00181EE4, &dbsc3_0->dbpdrgd); - - writel(0x0000000E, &dbsc3_0->dbpdrga); - writel(0x33C03812, &dbsc3_0->dbpdrgd); - - writel(0x00000003, &dbsc3_0->dbpdrga); - writel(0x0300C481, &dbsc3_0->dbpdrgd); - - writel(0x00000007, &dbsc3_0->dbkind); - writel(0x10030A02, &dbsc3_0->dbconf0); - writel(0x00000001, &dbsc3_0->dbphytype); - writel(0x00000000, &dbsc3_0->dbbl); - writel(0x0000000B, &dbsc3_0->dbtr0); - writel(0x00000008, &dbsc3_0->dbtr1); - writel(0x00000000, &dbsc3_0->dbtr2); - writel(0x0000000B, &dbsc3_0->dbtr3); - writel(0x000C000B, &dbsc3_0->dbtr4); - writel(0x00000027, &dbsc3_0->dbtr5); - writel(0x0000001C, &dbsc3_0->dbtr6); - writel(0x00000005, &dbsc3_0->dbtr7); - writel(0x00000018, &dbsc3_0->dbtr8); - writel(0x00000008, &dbsc3_0->dbtr9); - writel(0x0000000C, &dbsc3_0->dbtr10); - writel(0x00000009, &dbsc3_0->dbtr11); - writel(0x00000012, &dbsc3_0->dbtr12); - writel(0x000000D0, &dbsc3_0->dbtr13); - writel(0x00140005, &dbsc3_0->dbtr14); - writel(0x00050004, &dbsc3_0->dbtr15); - writel(0x70233005, &dbsc3_0->dbtr16); - writel(0x000C0000, &dbsc3_0->dbtr17); - writel(0x00000300, &dbsc3_0->dbtr18); - writel(0x00000040, &dbsc3_0->dbtr19); - writel(0x00000001, &dbsc3_0->dbrnk0); - writel(0x00020001, &dbsc3_0->dbadj0); - writel(0x20082008, &dbsc3_0->dbadj2); - writel(0x00020002, &dbsc3_0->dbwt0cnf0); - writel(0x0000000F, &dbsc3_0->dbwt0cnf4); - - writel(0x00000015, &dbsc3_0->dbpdrga); - writel(0x00000D70, &dbsc3_0->dbpdrgd); - - writel(0x00000016, &dbsc3_0->dbpdrga); - writel(0x00000006, &dbsc3_0->dbpdrgd); - - writel(0x00000017, &dbsc3_0->dbpdrga); - writel(0x00000018, &dbsc3_0->dbpdrgd); - - writel(0x00000012, &dbsc3_0->dbpdrga); - writel(0x9D5CBB66, &dbsc3_0->dbpdrgd); - - writel(0x00000013, &dbsc3_0->dbpdrga); - writel(0x1A868300, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FDB6C0, &dbsc3_0->dbpdrgd); - - writel(0x00000014, &dbsc3_0->dbpdrga); - writel(0x300214D8, &dbsc3_0->dbpdrgd); - - writel(0x0000001A, &dbsc3_0->dbpdrga); - writel(0x930035C7, &dbsc3_0->dbpdrgd); - - writel(0x00000060, &dbsc3_0->dbpdrga); - writel(0x330657B2, &dbsc3_0->dbpdrgd); - - writel(0x00000011, &dbsc3_0->dbpdrga); - writel(0x1000040B, &dbsc3_0->dbpdrgd); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000071, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x2100FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - - writel(0x110000DB, &dbsc3_0->dbcmd); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000181, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x0000FE01, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000000, &dbsc3_0->dbbs0cnt1); - writel(0x01004C20, &dbsc3_0->dbcalcnf); - writel(0x014000AA, &dbsc3_0->dbcaltr); - writel(0x00000140, &dbsc3_0->dbrfcnf0); - writel(0x00081860, &dbsc3_0->dbrfcnf1); - writel(0x00010000, &dbsc3_0->dbrfcnf2); - writel(0x00000001, &dbsc3_0->dbrfen); - writel(0x00000001, &dbsc3_0->dbacen); -} -#else -#define bsc_init() do {} while (0) -#endif /* CONFIG_NORFLASH */ - -void s_init(void) -{ - struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE; - struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE; - - /* Watchdog init */ - writel(0xA5A5A500, &rwdt->rwtcsra); - writel(0xA5A5A500, &swdt->swtcsra); - - /* QoS */ - qos_init(); - - /* BSC */ - bsc_init(); -} - -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 -#define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C -#define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 -#define ETHER_MSTP813 (1 << 13) - -#define PMMR 0xE6060000 -#define GPSR4 0xE6060014 -#define IPSR14 0xE6060058 - -#define set_guard_reg(addr, mask, value) \ -{ \ - u32 val; \ - val = (readl(addr) & ~(mask)) | (value); \ - writel(~val, PMMR); \ - writel(val, addr); \ -} - -#define mstp_setbits(type, addr, saddr, set) \ - out_##type((saddr), in_##type(addr) | (set)) -#define mstp_clrbits(type, addr, saddr, clear) \ - out_##type((saddr), in_##type(addr) & ~(clear)) -#define mstp_setbits_le32(addr, saddr, set) \ - mstp_setbits(le32, addr, saddr, set) -#define mstp_clrbits_le32(addr, saddr, clear) \ - mstp_clrbits(le32, addr, saddr, clear) - -int board_early_init_f(void) -{ - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - -#if defined(CONFIG_NORFLASH) - /* SCIF0 */ - set_guard_reg(GPSR4, 0x34000000, 0x00000000); - set_guard_reg(IPSR14, 0x00000FC7, 0x00000481); - set_guard_reg(GPSR4, 0x00000000, 0x34000000); -#endif - - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - return 0; -} - -void arch_preboot_os(void) -{ - /* Disable TMU0 */ - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); -} - -/* LSI pin pull-up control */ -#define PUPR5 0xe6060114 -#define PUPR5_ETH 0x3FFC0000 -#define PUPR5_ETH_MAGIC (1 << 27) -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100; - - /* Init PFC controller */ - r8a7791_pinmux_init(); - - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REFCLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ0, NULL); - - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); - gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); - - gpio_direction_output(GPIO_GP_5_22, 0); - mdelay(20); - gpio_set_value(GPIO_GP_5_22, 1); - udelay(1); - - return 0; -} - -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SH_ETHER - int ret = -ENODEV; - u32 val; - unsigned char enetaddr[6]; - - ret = sh_eth_initialize(bis); - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); - - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); - - return ret; -#else - return 0; -#endif -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} - -/* koelsch has KSZ8041NL/RNL */ -#define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 -#define PHY_LED_MODE_ACK 0x4000 -int board_phy_config(struct phy_device *phydev) -{ - int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); - ret &= ~PHY_LED_MODE; - ret |= PHY_LED_MODE_ACK; - ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); - - return 0; -} - -const struct rmobile_sysinfo sysinfo = { - CONFIG_RMOBILE_BOARD_STRING -}; - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE; - gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE; -} - -int board_late_init(void) -{ - return 0; -} - -void reset_cpu(ulong addr) -{ - u8 val; - - i2c_set_bus_num(2); /* PowerIC connected to ch2 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); -} diff --git a/qemu/roms/u-boot/board/renesas/koelsch/qos.c b/qemu/roms/u-boot/board/renesas/koelsch/qos.c deleted file mode 100644 index 7f88f7da8..000000000 --- a/qemu/roms/u-boot/board/renesas/koelsch/qos.c +++ /dev/null @@ -1,1220 +0,0 @@ -/* - * board/renesas/koelsch/qos.c - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <asm/arch/rmobile.h> - -/* QoS version 0.23 */ - -enum { - DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, - DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, - DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, - DBSC3_15, - DBSC3_NR, -}; - -static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { - [DBSC3_00] = DBSC3_0_QOS_R0_BASE, - [DBSC3_01] = DBSC3_0_QOS_R1_BASE, - [DBSC3_02] = DBSC3_0_QOS_R2_BASE, - [DBSC3_03] = DBSC3_0_QOS_R3_BASE, - [DBSC3_04] = DBSC3_0_QOS_R4_BASE, - [DBSC3_05] = DBSC3_0_QOS_R5_BASE, - [DBSC3_06] = DBSC3_0_QOS_R6_BASE, - [DBSC3_07] = DBSC3_0_QOS_R7_BASE, - [DBSC3_08] = DBSC3_0_QOS_R8_BASE, - [DBSC3_09] = DBSC3_0_QOS_R9_BASE, - [DBSC3_10] = DBSC3_0_QOS_R10_BASE, - [DBSC3_11] = DBSC3_0_QOS_R11_BASE, - [DBSC3_12] = DBSC3_0_QOS_R12_BASE, - [DBSC3_13] = DBSC3_0_QOS_R13_BASE, - [DBSC3_14] = DBSC3_0_QOS_R14_BASE, - [DBSC3_15] = DBSC3_0_QOS_R15_BASE, -}; - -static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { - [DBSC3_00] = DBSC3_0_QOS_W0_BASE, - [DBSC3_01] = DBSC3_0_QOS_W1_BASE, - [DBSC3_02] = DBSC3_0_QOS_W2_BASE, - [DBSC3_03] = DBSC3_0_QOS_W3_BASE, - [DBSC3_04] = DBSC3_0_QOS_W4_BASE, - [DBSC3_05] = DBSC3_0_QOS_W5_BASE, - [DBSC3_06] = DBSC3_0_QOS_W6_BASE, - [DBSC3_07] = DBSC3_0_QOS_W7_BASE, - [DBSC3_08] = DBSC3_0_QOS_W8_BASE, - [DBSC3_09] = DBSC3_0_QOS_W9_BASE, - [DBSC3_10] = DBSC3_0_QOS_W10_BASE, - [DBSC3_11] = DBSC3_0_QOS_W11_BASE, - [DBSC3_12] = DBSC3_0_QOS_W12_BASE, - [DBSC3_13] = DBSC3_0_QOS_W13_BASE, - [DBSC3_14] = DBSC3_0_QOS_W14_BASE, - [DBSC3_15] = DBSC3_0_QOS_W15_BASE, -}; - -static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = { - [DBSC3_00] = DBSC3_1_QOS_R0_BASE, - [DBSC3_01] = DBSC3_1_QOS_R1_BASE, - [DBSC3_02] = DBSC3_1_QOS_R2_BASE, - [DBSC3_03] = DBSC3_1_QOS_R3_BASE, - [DBSC3_04] = DBSC3_1_QOS_R4_BASE, - [DBSC3_05] = DBSC3_1_QOS_R5_BASE, - [DBSC3_06] = DBSC3_1_QOS_R6_BASE, - [DBSC3_07] = DBSC3_1_QOS_R7_BASE, - [DBSC3_08] = DBSC3_1_QOS_R8_BASE, - [DBSC3_09] = DBSC3_1_QOS_R9_BASE, - [DBSC3_10] = DBSC3_1_QOS_R10_BASE, - [DBSC3_11] = DBSC3_1_QOS_R11_BASE, - [DBSC3_12] = DBSC3_1_QOS_R12_BASE, - [DBSC3_13] = DBSC3_1_QOS_R13_BASE, - [DBSC3_14] = DBSC3_1_QOS_R14_BASE, - [DBSC3_15] = DBSC3_1_QOS_R15_BASE, -}; - -static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = { - [DBSC3_00] = DBSC3_1_QOS_W0_BASE, - [DBSC3_01] = DBSC3_1_QOS_W1_BASE, - [DBSC3_02] = DBSC3_1_QOS_W2_BASE, - [DBSC3_03] = DBSC3_1_QOS_W3_BASE, - [DBSC3_04] = DBSC3_1_QOS_W4_BASE, - [DBSC3_05] = DBSC3_1_QOS_W5_BASE, - [DBSC3_06] = DBSC3_1_QOS_W6_BASE, - [DBSC3_07] = DBSC3_1_QOS_W7_BASE, - [DBSC3_08] = DBSC3_1_QOS_W8_BASE, - [DBSC3_09] = DBSC3_1_QOS_W9_BASE, - [DBSC3_10] = DBSC3_1_QOS_W10_BASE, - [DBSC3_11] = DBSC3_1_QOS_W11_BASE, - [DBSC3_12] = DBSC3_1_QOS_W12_BASE, - [DBSC3_13] = DBSC3_1_QOS_W13_BASE, - [DBSC3_14] = DBSC3_1_QOS_W14_BASE, - [DBSC3_15] = DBSC3_1_QOS_W15_BASE, -}; - -void qos_init(void) -{ - int i; - struct r8a7791_s3c *s3c; - struct r8a7791_s3c_qos *s3c_qos; - struct r8a7791_dbsc3_qos *qos_addr; - struct r8a7791_mxi *mxi; - struct r8a7791_mxi_qos *mxi_qos; - struct r8a7791_axi_qos *axi_qos; - - /* DBSC DBADJ2 */ - writel(0x20042004, DBSC3_0_DBADJ2); - - /* S3C -QoS */ - s3c = (struct r8a7791_s3c *)S3C_BASE; - writel(0x00FF1B1D, &s3c->s3cadsplcr); - writel(0x1F0D0C0C, &s3c->s3crorr); - writel(0x1F0D0C0A, &s3c->s3cworr); - - /* QoS Control Registers */ - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI0_BASE; - writel(0x00890089, &s3c_qos->s3cqos0); - writel(0x20960010, &s3c_qos->s3cqos1); - writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); - writel(0x00002032, &s3c_qos->s3cqos4); - writel(0x20960010, &s3c_qos->s3cqos5); - writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); - writel(0x00002032, &s3c_qos->s3cqos8); - - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI1_BASE; - writel(0x00890089, &s3c_qos->s3cqos0); - writel(0x20960010, &s3c_qos->s3cqos1); - writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); - writel(0x00002032, &s3c_qos->s3cqos4); - writel(0x20960010, &s3c_qos->s3cqos5); - writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); - writel(0x00002032, &s3c_qos->s3cqos8); - - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_MXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); - writel(0x20960020, &s3c_qos->s3cqos1); - writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA20DC, &s3c_qos->s3cqos3); - writel(0x00002032, &s3c_qos->s3cqos4); - writel(0x20960020, &s3c_qos->s3cqos5); - writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA20DC, &s3c_qos->s3cqos7); - writel(0x00002032, &s3c_qos->s3cqos8); - - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); - writel(0x20960020, &s3c_qos->s3cqos1); - writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA20FA, &s3c_qos->s3cqos3); - writel(0x00002032, &s3c_qos->s3cqos4); - writel(0x20960020, &s3c_qos->s3cqos5); - writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA20FA, &s3c_qos->s3cqos7); - writel(0x00002032, &s3c_qos->s3cqos8); - - /* DBSC -QoS */ - /* DBSC0 - Read */ - for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; - writel(0x00000002, &qos_addr->dblgcnt); - writel(0x00002096, &qos_addr->dbtmval0); - writel(0x00002064, &qos_addr->dbtmval1); - writel(0x00002032, &qos_addr->dbtmval2); - writel(0x00001FB0, &qos_addr->dbtmval3); - writel(0x00000001, &qos_addr->dbrqctr); - writel(0x00002078, &qos_addr->dbthres0); - writel(0x0000204B, &qos_addr->dbthres1); - writel(0x00001FE7, &qos_addr->dbthres2); - writel(0x00000001, &qos_addr->dblgqon); - } - - /* DBSC0 - Write */ - for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; - writel(0x00000002, &qos_addr->dblgcnt); - writel(0x000020EB, &qos_addr->dbtmval0); - writel(0x0000206E, &qos_addr->dbtmval1); - writel(0x00002050, &qos_addr->dbtmval2); - writel(0x0000203A, &qos_addr->dbtmval3); - writel(0x00000001, &qos_addr->dbrqctr); - writel(0x00002078, &qos_addr->dbthres0); - writel(0x0000205A, &qos_addr->dbthres1); - writel(0x0000203C, &qos_addr->dbthres2); - writel(0x00000001, &qos_addr->dblgqon); - } - - /* DBSC1 - Read */ - for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_r_qos_addr[i]; - writel(0x00000002, &qos_addr->dblgcnt); - writel(0x00002096, &qos_addr->dbtmval0); - writel(0x00002064, &qos_addr->dbtmval1); - writel(0x00002032, &qos_addr->dbtmval2); - writel(0x00001FB0, &qos_addr->dbtmval3); - writel(0x00000001, &qos_addr->dbrqctr); - writel(0x00002078, &qos_addr->dbthres0); - writel(0x0000204B, &qos_addr->dbthres1); - writel(0x00001FE7, &qos_addr->dbthres2); - writel(0x00000001, &qos_addr->dblgqon); - } - - /* DBSC1 - Write */ - for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_w_qos_addr[i]; - writel(0x00000002, &qos_addr->dblgcnt); - writel(0x000020EB, &qos_addr->dbtmval0); - writel(0x0000206E, &qos_addr->dbtmval1); - writel(0x00002050, &qos_addr->dbtmval2); - writel(0x0000203A, &qos_addr->dbtmval3); - writel(0x00000001, &qos_addr->dbrqctr); - writel(0x00002078, &qos_addr->dbthres0); - writel(0x0000205A, &qos_addr->dbthres1); - writel(0x0000203C, &qos_addr->dbthres2); - writel(0x00000001, &qos_addr->dblgqon); - } - - /* CCI-400 -QoS */ - writel(0x20001000, CCI_400_MAXOT_1); - writel(0x20001000, CCI_400_MAXOT_2); - writel(0x0000000C, CCI_400_QOSCNTL_1); - writel(0x0000000C, CCI_400_QOSCNTL_2); - - /* MXI -QoS */ - /* Transaction Control (MXI) */ - mxi = (struct r8a7791_mxi *)MXI_BASE; - writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); - writel(0x00780080, &mxi->mxsaar0); - writel(0x02000800, &mxi->mxsaar1); - - /* QoS Control (MXI) */ - mxi_qos = (struct r8a7791_mxi_qos *)MXI_QOS_BASE; - writel(0x0000000C, &mxi_qos->vspdu0); - writel(0x0000000C, &mxi_qos->vspdu1); - writel(0x0000000D, &mxi_qos->du0); - writel(0x0000000D, &mxi_qos->du1); - - /* AXI -QoS */ - /* Transaction Control (MXI) */ - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SYX64TO128_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AVB_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020A6, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_G2D_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020A6, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002021, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002037, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX0_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX1_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX2_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_LBS_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000214C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUDS_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUM_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS0_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS1_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002021, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002021, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_PCI_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000214C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_RTX_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020A6, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020A6, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB20_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB21_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB22_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB30_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000214C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AX2M_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CC50_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002029, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CCI_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CS_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_DDM_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020A6, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_ETH_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MPXM_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000214C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000214C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_TRAB_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020A6, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (RT-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_DBG_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDM_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002299, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDS_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002029, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RTX64TO128_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_STPRO_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002029, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SY2RT_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (MP-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ADSP_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002037, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS0_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS1_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MLP_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MMUMP_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPU_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002053, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPUC_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000206E, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (SYS-AXI256) */ - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_AXI128TO256_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_SYX_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MPX_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MXI_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (CCI-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS0_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_SYX2_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUDS_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUM_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MXI_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS1_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUMP_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (Media-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXR_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x000020DC, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x000020AA, &axi_qos->qosthres0); - writel(0x00002032, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXW_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x000020DC, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x000020AA, &axi_qos->qosthres0); - writel(0x00002032, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002190, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VIN0W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0R_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0W_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1R_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1W_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0R_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002063, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0W_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002063, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002073, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002073, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002073, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002073, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VPC0R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002073, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); -} diff --git a/qemu/roms/u-boot/board/renesas/koelsch/qos.h b/qemu/roms/u-boot/board/renesas/koelsch/qos.h deleted file mode 100644 index 9a6c0461b..000000000 --- a/qemu/roms/u-boot/board/renesas/koelsch/qos.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef __QOS_H__ -#define __QOS_H__ - -void qos_init(void); - -#endif diff --git a/qemu/roms/u-boot/board/renesas/lager/Makefile b/qemu/roms/u-boot/board/renesas/lager/Makefile deleted file mode 100644 index 034c6f8c0..000000000 --- a/qemu/roms/u-boot/board/renesas/lager/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# board/renesas/lager/Makefile -# -# Copyright (C) 2013 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0 -# - -obj-y := lager.o qos.o diff --git a/qemu/roms/u-boot/board/renesas/lager/lager.c b/qemu/roms/u-boot/board/renesas/lager/lager.c deleted file mode 100644 index ad5289a23..000000000 --- a/qemu/roms/u-boot/board/renesas/lager/lager.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * board/renesas/lager/lager.c - * This file is lager board support. - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <malloc.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/rmobile.h> -#include <miiphy.h> -#include <i2c.h> -#include "qos.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define s_init_wait(cnt) \ - ({ \ - u32 i = 0x10000 * cnt; \ - while (i > 0) \ - i--; \ - }) - -#define dbpdrgd_check(bsc) \ - ({ \ - while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \ - ; \ - }) - -#if defined(CONFIG_NORFLASH) -static void bsc_init(void) -{ - struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE; - struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE; - - /* LBSC */ - writel(0x00000020, &lbsc->cs0ctrl); - writel(0x00000020, &lbsc->cs1ctrl); - writel(0x00002020, &lbsc->ecs0ctrl); - writel(0x00002020, &lbsc->ecs1ctrl); - - writel(0x077F077F, &lbsc->cswcr0); - writel(0x077F077F, &lbsc->cswcr1); - writel(0x077F077F, &lbsc->ecswcr0); - writel(0x077F077F, &lbsc->ecswcr1); - - /* DBSC3 */ - s_init_wait(10); - - writel(0x0000A55A, &dbsc3_0->dbpdlck); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x80000000, &dbsc3_0->dbpdrgd); - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000006, &dbsc3_0->dbpdrga); - writel(0x0001C000, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FD2480, &dbsc3_0->dbpdrgd); - - writel(0x00000010, &dbsc3_0->dbpdrga); - writel(0xF004649B, &dbsc3_0->dbpdrgd); - - writel(0x0000000F, &dbsc3_0->dbpdrga); - writel(0x00181EE4, &dbsc3_0->dbpdrgd); - - writel(0x0000000E, &dbsc3_0->dbpdrga); - writel(0x33C03812, &dbsc3_0->dbpdrgd); - - writel(0x00000003, &dbsc3_0->dbpdrga); - writel(0x0300C481, &dbsc3_0->dbpdrgd); - - writel(0x00000007, &dbsc3_0->dbkind); - writel(0x10030A02, &dbsc3_0->dbconf0); - writel(0x00000001, &dbsc3_0->dbphytype); - writel(0x00000000, &dbsc3_0->dbbl); - writel(0x0000000B, &dbsc3_0->dbtr0); - writel(0x00000008, &dbsc3_0->dbtr1); - writel(0x00000000, &dbsc3_0->dbtr2); - writel(0x0000000B, &dbsc3_0->dbtr3); - writel(0x000C000B, &dbsc3_0->dbtr4); - writel(0x00000027, &dbsc3_0->dbtr5); - writel(0x0000001C, &dbsc3_0->dbtr6); - writel(0x00000005, &dbsc3_0->dbtr7); - writel(0x00000018, &dbsc3_0->dbtr8); - writel(0x00000008, &dbsc3_0->dbtr9); - writel(0x0000000C, &dbsc3_0->dbtr10); - writel(0x00000009, &dbsc3_0->dbtr11); - writel(0x00000012, &dbsc3_0->dbtr12); - writel(0x000000D0, &dbsc3_0->dbtr13); - writel(0x00140005, &dbsc3_0->dbtr14); - writel(0x00050004, &dbsc3_0->dbtr15); - writel(0x70233005, &dbsc3_0->dbtr16); - writel(0x000C0000, &dbsc3_0->dbtr17); - writel(0x00000300, &dbsc3_0->dbtr18); - writel(0x00000040, &dbsc3_0->dbtr19); - writel(0x00000001, &dbsc3_0->dbrnk0); - writel(0x00020001, &dbsc3_0->dbadj0); - writel(0x20082008, &dbsc3_0->dbadj2); - writel(0x00020002, &dbsc3_0->dbwt0cnf0); - writel(0x0000000F, &dbsc3_0->dbwt0cnf4); - - writel(0x00000015, &dbsc3_0->dbpdrga); - writel(0x00000D70, &dbsc3_0->dbpdrgd); - - writel(0x00000016, &dbsc3_0->dbpdrga); - writel(0x00000006, &dbsc3_0->dbpdrgd); - - writel(0x00000017, &dbsc3_0->dbpdrga); - writel(0x00000018, &dbsc3_0->dbpdrgd); - - writel(0x00000012, &dbsc3_0->dbpdrga); - writel(0x9D5CBB66, &dbsc3_0->dbpdrgd); - - writel(0x00000013, &dbsc3_0->dbpdrga); - writel(0x1A868300, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FDB6C0, &dbsc3_0->dbpdrgd); - - writel(0x00000014, &dbsc3_0->dbpdrga); - writel(0x300214D8, &dbsc3_0->dbpdrgd); - - writel(0x0000001A, &dbsc3_0->dbpdrga); - writel(0x930035C7, &dbsc3_0->dbpdrgd); - - writel(0x00000060, &dbsc3_0->dbpdrga); - writel(0x330657B2, &dbsc3_0->dbpdrgd); - - writel(0x00000011, &dbsc3_0->dbpdrga); - writel(0x1000040B, &dbsc3_0->dbpdrgd); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000071, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x2100FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - - writel(0x110000DB, &dbsc3_0->dbcmd); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000181, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x0000FE01, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000000, &dbsc3_0->dbbs0cnt1); - writel(0x01004C20, &dbsc3_0->dbcalcnf); - writel(0x014000AA, &dbsc3_0->dbcaltr); - writel(0x00000140, &dbsc3_0->dbrfcnf0); - writel(0x00081860, &dbsc3_0->dbrfcnf1); - writel(0x00010000, &dbsc3_0->dbrfcnf2); - writel(0x00000001, &dbsc3_0->dbrfen); - writel(0x00000001, &dbsc3_0->dbacen); -} -#else -#define bsc_init() do {} while (0) -#endif /* CONFIG_NORFLASH */ - -void s_init(void) -{ - struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE; - struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE; - - /* Watchdog init */ - writel(0xA5A5A500, &rwdt->rwtcsra); - writel(0xA5A5A500, &swdt->swtcsra); - - /* QoS(Quality-of-Service) Init */ - qos_init(); - - /* BSC init */ - bsc_init(); -} - -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 -#define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C -#define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 -#define ETHER_MSTP813 (1 << 13) - -#define PMMR 0xE6060000 -#define GPSR4 0xE6060014 -#define IPSR14 0xE6060058 - -#define set_guard_reg(addr, mask, value) \ -{ \ - u32 val; \ - val = (readl(addr) & ~(mask)) | (value); \ - writel(~val, PMMR); \ - writel(val, addr); \ -} - -#define mstp_setbits(type, addr, saddr, set) \ - out_##type((saddr), in_##type(addr) | (set)) -#define mstp_clrbits(type, addr, saddr, clear) \ - out_##type((saddr), in_##type(addr) & ~(clear)) -#define mstp_setbits_le32(addr, saddr, set) \ - mstp_setbits(le32, addr, saddr, set) -#define mstp_clrbits_le32(addr, saddr, clear) \ - mstp_clrbits(le32, addr, saddr, clear) - -int board_early_init_f(void) -{ - /* TMU0 */ - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - -#if defined(CONFIG_NORFLASH) - /* SCIF0 */ - set_guard_reg(GPSR4, 0x34000000, 0x00000000); - set_guard_reg(IPSR14, 0x00000FC7, 0x00000481); - set_guard_reg(GPSR4, 0x00000000, 0x34000000); -#endif - - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - return 0; -} - -void arch_preboot_os(void) -{ - /* Disable TMU0 */ - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); -} - -DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_LAGER; - /* adress of boot parameters */ - gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100; - - /* Init PFC controller */ - r8a7790_pinmux_init(); - - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REF_CLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_MAGIC, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ0, NULL); - - gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ - gpio_direction_output(GPIO_GP_5_31, 0); - mdelay(20); - gpio_set_value(GPIO_GP_5_31, 1); - udelay(1); - - return 0; -} - -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) -{ - int ret = -ENODEV; - -#ifdef CONFIG_SH_ETHER - u32 val; - unsigned char enetaddr[6]; - - ret = sh_eth_initialize(bis); - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); - - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); - -#endif - - return ret; -} - -/* lager has KSZ8041NL/RNL */ -#define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 -#define PHY_LED_MODE_ACK 0x4000 -int board_phy_config(struct phy_device *phydev) -{ - int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); - ret &= ~PHY_LED_MODE; - ret |= PHY_LED_MODE_ACK; - ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} - -const struct rmobile_sysinfo sysinfo = { - CONFIG_RMOBILE_BOARD_STRING -}; - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE; - gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE; -} - -int board_late_init(void) -{ - return 0; -} - -void reset_cpu(ulong addr) -{ - u8 val; - - i2c_set_bus_num(3); /* PowerIC connected to ch3 */ - i2c_init(400000, 0); - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); -} diff --git a/qemu/roms/u-boot/board/renesas/lager/qos.c b/qemu/roms/u-boot/board/renesas/lager/qos.c deleted file mode 100644 index b88511a32..000000000 --- a/qemu/roms/u-boot/board/renesas/lager/qos.c +++ /dev/null @@ -1,1119 +0,0 @@ -/* - * board/renesas/lager/qos.c - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <asm/arch/rmobile.h> - -/* QoS version 0.954 */ - -enum { - DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04, - DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09, - DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14, - DBSC3_R15, - DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04, - DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09, - DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14, - DBSC3_W15, - DBSC3_NR, -}; - -static const u32 dbsc3_qos_addr[DBSC3_NR] = { - [DBSC3_R00] = DBSC3_0_QOS_R0_BASE, - [DBSC3_R01] = DBSC3_0_QOS_R1_BASE, - [DBSC3_R02] = DBSC3_0_QOS_R2_BASE, - [DBSC3_R03] = DBSC3_0_QOS_R3_BASE, - [DBSC3_R04] = DBSC3_0_QOS_R4_BASE, - [DBSC3_R05] = DBSC3_0_QOS_R5_BASE, - [DBSC3_R06] = DBSC3_0_QOS_R6_BASE, - [DBSC3_R07] = DBSC3_0_QOS_R7_BASE, - [DBSC3_R08] = DBSC3_0_QOS_R8_BASE, - [DBSC3_R09] = DBSC3_0_QOS_R9_BASE, - [DBSC3_R10] = DBSC3_0_QOS_R10_BASE, - [DBSC3_R11] = DBSC3_0_QOS_R11_BASE, - [DBSC3_R12] = DBSC3_0_QOS_R12_BASE, - [DBSC3_R13] = DBSC3_0_QOS_R13_BASE, - [DBSC3_R14] = DBSC3_0_QOS_R14_BASE, - [DBSC3_R15] = DBSC3_0_QOS_R15_BASE, - [DBSC3_W00] = DBSC3_0_QOS_W0_BASE, - [DBSC3_W01] = DBSC3_0_QOS_W1_BASE, - [DBSC3_W02] = DBSC3_0_QOS_W2_BASE, - [DBSC3_W03] = DBSC3_0_QOS_W3_BASE, - [DBSC3_W04] = DBSC3_0_QOS_W4_BASE, - [DBSC3_W05] = DBSC3_0_QOS_W5_BASE, - [DBSC3_W06] = DBSC3_0_QOS_W6_BASE, - [DBSC3_W07] = DBSC3_0_QOS_W7_BASE, - [DBSC3_W08] = DBSC3_0_QOS_W8_BASE, - [DBSC3_W09] = DBSC3_0_QOS_W9_BASE, - [DBSC3_W10] = DBSC3_0_QOS_W10_BASE, - [DBSC3_W11] = DBSC3_0_QOS_W11_BASE, - [DBSC3_W12] = DBSC3_0_QOS_W12_BASE, - [DBSC3_W13] = DBSC3_0_QOS_W13_BASE, - [DBSC3_W14] = DBSC3_0_QOS_W14_BASE, - [DBSC3_W15] = DBSC3_0_QOS_W15_BASE, -}; - -void qos_init(void) -{ - int i; - struct r8a7790_s3c *s3c; - struct r8a7790_s3c_qos *s3c_qos; - struct r8a7790_dbsc3_qos *qos_addr; - struct r8a7790_mxi *mxi; - struct r8a7790_mxi_qos *mxi_qos; - struct r8a7790_axi_qos *axi_qos; - - /* DBSC DBADJ2 */ - writel(0x20042004, DBSC3_0_DBADJ2); - - /* S3C -QoS */ - s3c = (struct r8a7790_s3c *)S3C_BASE; - writel(0x80FF1C1E, &s3c->s3cadsplcr); - writel(0x1F060505, &s3c->s3crorr); - writel(0x1F020100, &s3c->s3cworr); - - /* QoS Control Registers */ - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE; - writel(0x00800080, &s3c_qos->s3cqos0); - writel(0x22000010, &s3c_qos->s3cqos1); - writel(0x22002200, &s3c_qos->s3cqos2); - writel(0x2F002200, &s3c_qos->s3cqos3); - writel(0x2F002F00, &s3c_qos->s3cqos4); - writel(0x22000010, &s3c_qos->s3cqos5); - writel(0x22002200, &s3c_qos->s3cqos6); - writel(0x2F002200, &s3c_qos->s3cqos7); - writel(0x2F002F00, &s3c_qos->s3cqos8); - - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE; - writel(0x00800080, &s3c_qos->s3cqos0); - writel(0x22000010, &s3c_qos->s3cqos1); - writel(0x22002200, &s3c_qos->s3cqos2); - writel(0x2F002200, &s3c_qos->s3cqos3); - writel(0x2F002F00, &s3c_qos->s3cqos4); - writel(0x22000010, &s3c_qos->s3cqos5); - writel(0x22002200, &s3c_qos->s3cqos6); - writel(0x2F002200, &s3c_qos->s3cqos7); - writel(0x2F002F00, &s3c_qos->s3cqos8); - - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE; - writel(0x80918099, &s3c_qos->s3cqos0); - writel(0x20410010, &s3c_qos->s3cqos1); - writel(0x200A2023, &s3c_qos->s3cqos2); - writel(0x20502001, &s3c_qos->s3cqos3); - writel(0x00002032, &s3c_qos->s3cqos4); - writel(0x20410FFF, &s3c_qos->s3cqos5); - writel(0x200A2023, &s3c_qos->s3cqos6); - writel(0x20502001, &s3c_qos->s3cqos7); - writel(0x20142032, &s3c_qos->s3cqos8); - - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE; - - writel(0x00810089, &s3c_qos->s3cqos0); - writel(0x20410001, &s3c_qos->s3cqos1); - writel(0x200A2023, &s3c_qos->s3cqos2); - writel(0x20502001, &s3c_qos->s3cqos3); - writel(0x00002032, &s3c_qos->s3cqos4); - writel(0x20410FFF, &s3c_qos->s3cqos5); - writel(0x200A2023, &s3c_qos->s3cqos6); - writel(0x20502001, &s3c_qos->s3cqos7); - writel(0x20142032, &s3c_qos->s3cqos8); - - writel(0x00200808, &s3c->s3carcr11); - - /* DBSC -QoS */ - /* DBSC0 - Read/Write */ - for (i = DBSC3_R00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i]; - writel(0x00000203, &qos_addr->dblgcnt); - writel(0x00002064, &qos_addr->dbtmval0); - writel(0x00002048, &qos_addr->dbtmval1); - writel(0x00002032, &qos_addr->dbtmval2); - writel(0x00002019, &qos_addr->dbtmval3); - writel(0x00000001, &qos_addr->dbrqctr); - writel(0x00002019, &qos_addr->dbthres0); - writel(0x00002019, &qos_addr->dbthres1); - writel(0x00002019, &qos_addr->dbthres2); - writel(0x00000000, &qos_addr->dblgqon); - } - /* CCI-400 -QoS */ - writel(0x20001000, CCI_400_MAXOT_1); - writel(0x20001000, CCI_400_MAXOT_2); - writel(0x0000000C, CCI_400_QOSCNTL_1); - writel(0x0000000C, CCI_400_QOSCNTL_2); - - /* MXI -QoS */ - /* Transaction Control (MXI) */ - mxi = (struct r8a7790_mxi *)MXI_BASE; - writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); - writel(0x00B800C0, &mxi->mxsaar0); - writel(0x02000800, &mxi->mxsaar1); - writel(0x00200000, &mxi->mxs3cracr); - writel(0x00200000, &mxi->mxs3cwacr); - writel(0x00200000, &mxi->mxaxiracr); - writel(0x00200000, &mxi->mxaxiwacr); - - /* QoS Control (MXI) */ - mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE; - writel(0x0000000C, &mxi_qos->vspdu0); - writel(0x0000000C, &mxi_qos->vspdu1); - writel(0x0000000D, &mxi_qos->du0); - writel(0x0000000D, &mxi_qos->du1); - - /* AXI -QoS */ - /* Transaction Control (MXI) */ - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200A, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200A, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002002, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002004, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002002, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002002, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200A, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200A, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002005, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002005, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002005, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (RT-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002005, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002003, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (MP-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002002, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200D, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (SYS-AXI256) */ - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (CCI-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE; - writel(0x00000002, &axi_qos->qosconf); - writel(0x0000200F, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002001, &axi_qos->qosctset0); - writel(0x00002009, &axi_qos->qosctset1); - writel(0x00002003, &axi_qos->qosctset2); - writel(0x00002003, &axi_qos->qosctset3); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - /* QoS Register (Media-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002018, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x0000200C, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000001, &axi_qos->qosqon); - - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE; - writel(0x00000001, &axi_qos->qosconf); - writel(0x00002007, &axi_qos->qosctset0); - writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002006, &axi_qos->qosthres0); - writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); - writel(0x00000000, &axi_qos->qosqon); -} diff --git a/qemu/roms/u-boot/board/renesas/lager/qos.h b/qemu/roms/u-boot/board/renesas/lager/qos.h deleted file mode 100644 index 9a6c0461b..000000000 --- a/qemu/roms/u-boot/board/renesas/lager/qos.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef __QOS_H__ -#define __QOS_H__ - -void qos_init(void); - -#endif diff --git a/qemu/roms/u-boot/board/renesas/r0p7734/Makefile b/qemu/roms/u-boot/board/renesas/r0p7734/Makefile deleted file mode 100644 index 1f24d9296..000000000 --- a/qemu/roms/u-boot/board/renesas/r0p7734/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := r0p7734.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/r0p7734/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/r0p7734/lowlevel_init.S deleted file mode 100644 index 62668a76b..000000000 --- a/qemu/roms/u-boot/board/renesas/r0p7734/lowlevel_init.S +++ /dev/null @@ -1,593 +0,0 @@ -/* - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2011 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> - -#include <asm/processor.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - /* WDT */ - write32 WDTCSR_A, WDTCSR_D - - /* MMU */ - write32 MMUCR_A, MMUCR_D - - write32 FRQCR2_A, FRQCR2_D - write32 FRQCR0_A, FRQCR0_D - - write32 CS0CTRL_A, CS0CTRL_D - write32 CS1CTRL_A, CS1CTRL_D - write32 CS0CTRL2_A, CS0CTRL2_D - - write32 CSPWCR0_A, CSPWCR0_D - write32 CSPWCR1_A, CSPWCR1_D - write32 CS1GDST_A, CS1GDST_D - - # clock mode check - mov.l MODEMR, r1 - mov.l @r1, r0 - and #6, r0 /* Check 1 and 2 bit.*/ - cmp/eq #2, r0 /* 0x02 is 533Mhz mode */ - bt init_lbsc_533 - -init_lbsc_400: - - write32 CSWCR0_A, CSWCR0_D_400 - write32 CSWCR1_A, CSWCR1_D - - bra init_dbsc3_400_pad - nop - - .align 2 - -MODEMR: .long 0xFFCC0020 -WDTCSR_A: .long 0xFFCC0004 -WDTCSR_D: .long 0xA5000000 -MMUCR_A: .long 0xFF000010 -MMUCR_D: .long 0x00000004 - -FRQCR2_A: .long 0xFFC80008 -FRQCR2_D: .long 0x00000000 -FRQCR0_A: .long 0xFFC80000 -FRQCR0_D: .long 0xCF000001 - -CS0CTRL_A: .long 0xFF800200 -CS0CTRL_D: .long 0x00000020 -CS1CTRL_A: .long 0xFF800204 -CS1CTRL_D: .long 0x00000020 - -CS0CTRL2_A: .long 0xFF800220 -CS0CTRL2_D: .long 0x00004000 - -CSPWCR0_A: .long 0xFF800280 -CSPWCR0_D: .long 0x00000000 -CSPWCR1_A: .long 0xFF800284 -CSPWCR1_D: .long 0x00000000 -CS1GDST_A: .long 0xFF8002C0 -CS1GDST_D: .long 0x00000011 - -init_lbsc_533: - - write32 CSWCR0_A, CSWCR0_D_533 - write32 CSWCR1_A, CSWCR1_D - - bra init_dbsc3_533_pad - nop - - .align 2 - -CSWCR0_A: .long 0xFF800230 -CSWCR0_D_533: .long 0x01120104 -CSWCR0_D_400: .long 0x02120114 -/* CSWCR0_D_400: .long 0x01160116 */ -CSWCR1_A: .long 0xFF800234 -CSWCR1_D: .long 0x077F077F -/* CSWCR1_D_400: .long 0x00120012 */ - -init_dbsc3_400_pad: - - write32 DBPDCNT3_A, DBPDCNT3_D - wait_timer WAIT_200US_400 - - write32 DBPDCNT0_A, DBPDCNT0_D_400 - write32 DBPDCNT3_A, DBPDCNT3_D0 - write32 DBPDCNT1_A, DBPDCNT1_D - - write32 DBPDCNT3_A, DBPDCNT3_D1 - wait_timer WAIT_32MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D2 - wait_timer WAIT_100US_400 - - write32 DBPDCNT3_A, DBPDCNT3_D3 - wait_timer WAIT_16MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D4 - wait_timer WAIT_200US_400 - - write32 DBPDCNT3_A, DBPDCNT3_D5 - wait_timer WAIT_1MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D6 - wait_timer WAIT_10KMCLK - - bra init_dbsc3_ctrl_400 - nop - - .align 2 - -init_dbsc3_533_pad: - - write32 DBPDCNT3_A, DBPDCNT3_D - wait_timer WAIT_200US_533 - - write32 DBPDCNT0_A, DBPDCNT0_D_533 - write32 DBPDCNT3_A, DBPDCNT3_D0 - write32 DBPDCNT1_A, DBPDCNT1_D - - write32 DBPDCNT3_A, DBPDCNT3_D1 - wait_timer WAIT_32MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D2 - wait_timer WAIT_100US_533 - - write32 DBPDCNT3_A, DBPDCNT3_D3 - wait_timer WAIT_16MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D4 - wait_timer WAIT_200US_533 - - write32 DBPDCNT3_A, DBPDCNT3_D5 - wait_timer WAIT_1MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D6 - wait_timer WAIT_10KMCLK - - bra init_dbsc3_ctrl_533 - nop - - .align 2 - -WAIT_200US_400: .long 40000 -WAIT_200US_533: .long 53300 -WAIT_100US_400: .long 20000 -WAIT_100US_533: .long 26650 -WAIT_32MCLK: .long 32 -WAIT_16MCLK: .long 16 -WAIT_1MCLK: .long 1 -WAIT_10KMCLK: .long 10000 - -DBPDCNT0_A: .long 0xFE800200 -DBPDCNT0_D_533: .long 0x00010245 -DBPDCNT0_D_400: .long 0x00010235 -DBPDCNT1_A: .long 0xFE800204 -DBPDCNT1_D: .long 0x00000014 -DBPDCNT3_A: .long 0xFE80020C -DBPDCNT3_D: .long 0x80000000 -DBPDCNT3_D0: .long 0x800F0000 -DBPDCNT3_D1: .long 0x800F1000 -DBPDCNT3_D2: .long 0x820F1000 -DBPDCNT3_D3: .long 0x860F1000 -DBPDCNT3_D4: .long 0x870F1000 -DBPDCNT3_D5: .long 0x870F3000 -DBPDCNT3_D6: .long 0x870F7000 - -init_dbsc3_ctrl_400: - - write32 DBKIND_A, DBKIND_D - write32 DBCONF_A, DBCONF_D - - write32 DBTR0_A, DBTR0_D_400 - write32 DBTR1_A, DBTR1_D_400 - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D_400 - write32 DBTR4_A, DBTR4_D_400 - write32 DBTR5_A, DBTR5_D_400 - write32 DBTR6_A, DBTR6_D_400 - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D_400 - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D_400 - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D_400 - write32 DBTR13_A, DBTR13_D_400 - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D_400 - write32 DBTR17_A, DBTR17_D_400 - write32 DBTR18_A, DBTR18_D_400 - - write32 DBBL_A, DBBL_D - write32 DBRNK0_A, DBRNK0_D - - write32 DBCMD_A, DBCMD_D0_400 - write32 DBCMD_A, DBCMD_D1 - write32 DBCMD_A, DBCMD_D2 - write32 DBCMD_A, DBCMD_D3 - write32 DBCMD_A, DBCMD_D4 - write32 DBCMD_A, DBCMD_D5_400 - write32 DBCMD_A, DBCMD_D6 - write32 DBCMD_A, DBCMD_D7 - write32 DBCMD_A, DBCMD_D8 - write32 DBCMD_A, DBCMD_D9_400 - write32 DBCMD_A, DBCMD_D10 - write32 DBCMD_A, DBCMD_D11 - write32 DBCMD_A, DBCMD_D12 - - write32 DBBS0CNT1_A, DBBS0CNT1_D - write32 DBPDNCNF_A, DBPDNCNF_D - - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D_400 - write32 DBRFCNF2_A, DBRFCNF2_D - write32 DBRFEN_A, DBRFEN_D - write32 DBACEN_A, DBACEN_D - write32 DBACEN_A, DBACEN_D - - /* Dummy read */ - mov.l DBWAIT_A, r1 - synco - mov.l @r1, r0 - synco - - /* Dummy read */ - mov.l SDRAM_A, r1 - synco - mov.l @r1, r0 - synco - - /* need sleep 186A0 */ - - bra init_pfc_sh7734 - nop - - .align 2 - -init_dbsc3_ctrl_533: - - write32 DBKIND_A, DBKIND_D - write32 DBCONF_A, DBCONF_D - - write32 DBTR0_A, DBTR0_D_533 - write32 DBTR1_A, DBTR1_D_533 - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D_533 - write32 DBTR4_A, DBTR4_D_533 - write32 DBTR5_A, DBTR5_D_533 - write32 DBTR6_A, DBTR6_D_533 - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D_533 - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D_533 - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D_533 - write32 DBTR13_A, DBTR13_D_533 - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D_533 - write32 DBTR17_A, DBTR17_D_533 - write32 DBTR18_A, DBTR18_D_533 - - write32 DBBL_A, DBBL_D - write32 DBRNK0_A, DBRNK0_D - - write32 DBCMD_A, DBCMD_D0_533 - write32 DBCMD_A, DBCMD_D1 - write32 DBCMD_A, DBCMD_D2 - write32 DBCMD_A, DBCMD_D3 - write32 DBCMD_A, DBCMD_D4 - write32 DBCMD_A, DBCMD_D5_533 - write32 DBCMD_A, DBCMD_D6 - write32 DBCMD_A, DBCMD_D7 - write32 DBCMD_A, DBCMD_D8 - write32 DBCMD_A, DBCMD_D9_533 - write32 DBCMD_A, DBCMD_D10 - write32 DBCMD_A, DBCMD_D11 - write32 DBCMD_A, DBCMD_D12 - - write32 DBBS0CNT1_A, DBBS0CNT1_D - write32 DBPDNCNF_A, DBPDNCNF_D - - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D_533 - write32 DBRFCNF2_A, DBRFCNF2_D - write32 DBRFEN_A, DBRFEN_D - write32 DBACEN_A, DBACEN_D - write32 DBACEN_A, DBACEN_D - - /* Dummy read */ - mov.l DBWAIT_A, r1 - synco - mov.l @r1, r0 - synco - - /* Dummy read */ - mov.l SDRAM_A, r1 - synco - mov.l @r1, r0 - synco - - /* need sleep 186A0 */ - - bra init_pfc_sh7734 - nop - - .align 2 - -DBKIND_A: .long 0xFE800020 -DBKIND_D: .long 0x00000005 -DBCONF_A: .long 0xFE800024 -DBCONF_D: .long 0x0D030A01 - -DBTR0_A: .long 0xFE800040 -DBTR0_D_533:.long 0x00000004 -DBTR0_D_400:.long 0x00000003 -DBTR1_A: .long 0xFE800044 -DBTR1_D_533:.long 0x00000003 -DBTR1_D_400:.long 0x00000002 -DBTR2_A: .long 0xFE800048 -DBTR2_D: .long 0x00000000 -DBTR3_A: .long 0xFE800050 -DBTR3_D_533:.long 0x00000004 -DBTR3_D_400:.long 0x00000003 - -DBTR4_A: .long 0xFE800054 -DBTR4_D_533:.long 0x00050004 -DBTR4_D_400:.long 0x00050003 - -DBTR5_A: .long 0xFE800058 -DBTR5_D_533:.long 0x0000000F -DBTR5_D_400:.long 0x0000000B - -DBTR6_A: .long 0xFE80005C -DBTR6_D_533:.long 0x0000000B -DBTR6_D_400:.long 0x00000008 - -DBTR7_A: .long 0xFE800060 -DBTR7_D: .long 0x00000002 /* common value */ - -DBTR8_A: .long 0xFE800064 -DBTR8_D_533:.long 0x0000000D -DBTR8_D_400:.long 0x0000000A - -DBTR9_A: .long 0xFE800068 -DBTR9_D: .long 0x00000002 /* common value */ - -DBTR10_A: .long 0xFE80006C -DBTR10_D_533:.long 0x00000004 -DBTR10_D_400:.long 0x00000003 - -DBTR11_A: .long 0xFE800070 -DBTR11_D: .long 0x00000008 /* common value */ - -DBTR12_A: .long 0xFE800074 -DBTR12_D_533:.long 0x00000009 -DBTR12_D_400:.long 0x00000008 - -DBTR13_A: .long 0xFE800078 -DBTR13_D_533:.long 0x00000022 -DBTR13_D_400:.long 0x0000001A - -DBTR14_A: .long 0xFE80007C -DBTR14_D: .long 0x00070002 /* common value */ - -DBTR15_A: .long 0xFE800080 -DBTR15_D: .long 0x00000003 /* common value */ - -DBTR16_A: .long 0xFE800084 -DBTR16_D_533:.long 0x120A1001 -DBTR16_D_400:.long 0x12091001 - -DBTR17_A: .long 0xFE800088 -DBTR17_D_533:.long 0x00040000 -DBTR17_D_400:.long 0x00030000 - -DBTR18_A: .long 0xFE80008C -DBTR18_D_533:.long 0x02010200 -DBTR18_D_400:.long 0x02000207 - -DBBL_A: .long 0xFE8000B0 -DBBL_D: .long 0x00000000 - -DBRNK0_A: .long 0xFE800100 -DBRNK0_D: .long 0x00000001 - -DBCMD_A: .long 0xFE800018 -DBCMD_D0_533: .long 0x1100006B -DBCMD_D0_400: .long 0x11000050 -DBCMD_D1: .long 0x0B000000 /* common value */ -DBCMD_D2: .long 0x2A004000 /* common value */ -DBCMD_D3: .long 0x2B006000 /* common value */ -DBCMD_D4: .long 0x29002004 /* common value */ -DBCMD_D5_533: .long 0x28000743 -DBCMD_D5_400: .long 0x28000533 -DBCMD_D6: .long 0x0B000000 /* common value */ -DBCMD_D7: .long 0x0C000000 /* common value */ -DBCMD_D8: .long 0x0C000000 /* common value */ -DBCMD_D9_533: .long 0x28000643 -DBCMD_D9_400: .long 0x28000433 -DBCMD_D10: .long 0x000000C8 /* common value */ -DBCMD_D11: .long 0x29002384 /* common value */ -DBCMD_D12: .long 0x29002004 /* common value */ - -DBBS0CNT1_A: .long 0xFE800304 -DBBS0CNT1_D: .long 0x00000000 -DBPDNCNF_A: .long 0xFE800180 -DBPDNCNF_D: .long 0x00000200 - -DBRFCNF0_A: .long 0xFE8000E0 -DBRFCNF0_D: .long 0x000001FF -DBRFCNF1_A: .long 0xFE8000E4 -DBRFCNF1_D_533: .long 0x00000805 -DBRFCNF1_D_400: .long 0x00000618 - -DBRFCNF2_A: .long 0xFE8000E8 -DBRFCNF2_D: .long 0x00000000 - -DBRFEN_A: .long 0xFE800014 -DBRFEN_D: .long 0x00000001 - -DBACEN_A: .long 0xFE800010 -DBACEN_D: .long 0x00000001 - -DBWAIT_A: .long 0xFE80001C -SDRAM_A: .long 0x0C000000 - -init_pfc_sh7734: - write32 PFC_PMMR_A, PFC_PMMR_MODESEL1 - write32 PFC_MODESEL1_A, PFC_MODESEL1_D - - write32 PFC_PMMR_A, PFC_PMMR_MODESEL2 - write32 PFC_MODESEL2_A, PFC_MODESEL2_D - - write32 PFC_PMMR_A, PFC_PMMR_IPSR3 - write32 PFC_IPSR3_A, PFC_IPSR3_D - - write32 PFC_PMMR_A, PFC_PMMR_IPSR4 - write32 PFC_IPSR4_A, PFC_IPSR4_D - - write32 PFC_PMMR_A, PFC_PMMR_IPSR11 - write32 PFC_IPSR11_A, PFC_IPSR11_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR0 - write32 PFC_GPSR0_A, PFC_GPSR0_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR1 - write32 PFC_GPSR1_A, PFC_GPSR1_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR2 - write32 PFC_GPSR2_A, PFC_GPSR2_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR3 - write32 PFC_GPSR3_A, PFC_GPSR3_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR4 - write32 PFC_GPSR4_A, PFC_GPSR4_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR5 - write32 PFC_GPSR5_A, PFC_GPSR5_D - - /* sleep 186A0 */ - - write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D - write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D - write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D - write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D - write32 GPIO4_INOUTSEL4_A, GPIO4_INOUTSEL4_D - write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D - - write32 CCR_A, CCR_D - - stc sr, r0 - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - nop - - .align 2 - -PFC_PMMR_A: .long 0xFFFC0000 - -/* MODESEL - * 28: Select IEBUS Group B - */ -PFC_MODESEL1_A: .long 0xFFFC004C -PFC_MODESEL1_D: .long 0x10000000 -PFC_PMMR_MODESEL1: .long 0xEFFFFFFF - -/* MODESEL - * 9: Select SCIF3 Group B - * 7: Select SCIF2 Group B - * 4: Select SCIF1 Group B - */ -PFC_MODESEL2_A: .long 0xFFFC0050 -PFC_MODESEL2_D: .long 0x00000290 -PFC_PMMR_MODESEL2: .long 0xFFFFFD6F - -# Enable functios -# SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A, -# EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A, -# SD1_CD_A, TX3_B, RX3_B, CS1, D15 -PFC_IPSR3_A: .long 0xFFFC0028 -PFC_IPSR3_D: .long 0x09209248 -PFC_PMMR_IPSR3: .long 0xF6DF6DB7 - -# Enable functios -# RMII0_MDIO_A , RMII0_MDC_A, -# RMII0_CRS_DV_A, RMII0_RX_ER_A, -# RMII0_TXD_EN_A, MII0_RXD1_A -PFC_IPSR4_A: .long 0xFFFC002C -PFC_IPSR4_D: .long 0x0001B6DB -PFC_PMMR_IPSR4: .long 0xFFFE4924 - -# Enable functios -# DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B, -# IETX_B, TX0_A, RMII0_TXD0_A, -# RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1 -PFC_IPSR11_A: .long 0xFFFC0048 -PFC_IPSR11_D: .long 0x002C89B0 -PFC_PMMR_IPSR11:.long 0xFFD3764F - -PFC_GPSR0_A: .long 0xFFFC0004 -PFC_GPSR0_D: .long 0xFFFFFFFF -PFC_PMMR_GPSR0: .long 0x00000000 - -PFC_GPSR1_A: .long 0xFFFC0008 -PFC_GPSR1_D: .long 0x7FBF7FFF -PFC_PMMR_GPSR1: .long 0x80408000 - -PFC_GPSR2_A: .long 0xFFFC000C -PFC_GPSR2_D: .long 0xBFC07EDF -PFC_PMMR_GPSR2: .long 0x403F8120 - -PFC_GPSR3_A: .long 0xFFFC0010 -PFC_GPSR3_D: .long 0xFFFFFFFF -PFC_PMMR_GPSR3: .long 0x00000000 - -PFC_GPSR4_A: .long 0xFFFC0014 -#if 0 /* orig */ -PFC_GPSR4_D: .long 0xFFFFFFFF -PFC_PMMR_GPSR4: .long 0x00000000 -#else -PFC_GPSR4_D: .long 0xFBFFFFFF -PFC_PMMR_GPSR4: .long 0x04000000 -#endif - -PFC_GPSR5_A: .long 0xFFFC0018 -PFC_GPSR5_D: .long 0x00000C01 -PFC_PMMR_GPSR5: .long 0xFFFFF3FE - -I2C_ICCR2_A: .long 0xFFC70001 -I2C_ICCR2_D: .long 0x00 -I2C_ICCR2_D1: .long 0x20 - -GPIO2_INOUTSEL1_A: .long 0xFFC41004 -GPIO2_INOUTSEL1_D: .long 0x80408000 -GPIO1_OUTDT1_A: .long 0xFFC41008 /* bit15: LED4, bit22: LED5 */ -GPIO1_OUTDT1_D: .long 0x80408000 -GPIO2_INOUTSEL2_A: .long 0xFFC42004 -GPIO2_INOUTSEL2_D: .long 0x40000120 -GPIO2_OUTDT2_A: .long 0xFFC42008 -GPIO2_OUTDT2_D: .long 0x40000120 -GPIO4_INOUTSEL4_A: .long 0xFFC44004 -GPIO4_INOUTSEL4_D: .long 0x04000000 -GPIO4_OUTDT4_A: .long 0xFFC44008 -GPIO4_OUTDT4_D: .long 0x04000000 - -CCR_A: .long 0xFF00001C -CCR_D: .long 0x0000090B -SR_MASK_D: .long 0xEFFFFF0F diff --git a/qemu/roms/u-boot/board/renesas/r0p7734/r0p7734.c b/qemu/roms/u-boot/board/renesas/r0p7734/r0p7734.c deleted file mode 100644 index 5687ad476..000000000 --- a/qemu/roms/u-boot/board/renesas/r0p7734/r0p7734.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2011 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define MODEMR (0xFFCC0020) -#define MODEMR_MASK (0x6) -#define MODEMR_533MHZ (0x2) - -int checkboard(void) -{ - u32 r = readl(MODEMR); - if ((r & MODEMR_MASK) & MODEMR_533MHZ) - puts("CPU Clock: 533MHz\n"); - else - puts("CPU Clock: 400MHz\n"); - - puts("BOARD: Renesas Technology Corp. R0P7734C00000RZ\n"); - return 0; -} - -#define MSTPSR1 (0xFFC80044) -#define MSTPCR1 (0xFFC80034) -#define MSTPSR1_GETHER (1 << 14) - -int board_init(void) -{ -#if defined(CONFIG_SH_ETHER) - u32 r = readl(MSTPSR1); - if (r & MSTPSR1_GETHER) - writel((r & ~MSTPSR1_GETHER), MSTPCR1); -#endif - - return 0; -} - -int board_late_init(void) -{ - u8 mac[6]; - - /* Read Mac Address and set*/ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); - - /* Read MAC address */ - i2c_read(0x50, 0x10, 0, mac, 6); - - if (is_valid_ether_addr(mac)) - eth_setenv_enetaddr("ethaddr", mac); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - - return 0; -} - -#ifdef CONFIG_SMC911X -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - return rc; -} -#endif diff --git a/qemu/roms/u-boot/board/renesas/r2dplus/Makefile b/qemu/roms/u-boot/board/renesas/r2dplus/Makefile deleted file mode 100644 index acffb6d31..000000000 --- a/qemu/roms/u-boot/board/renesas/r2dplus/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2007,2008 -# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := r2dplus.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/r2dplus/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/r2dplus/lowlevel_init.S deleted file mode 100644 index f3392f097..000000000 --- a/qemu/roms/u-boot/board/renesas/r2dplus/lowlevel_init.S +++ /dev/null @@ -1,118 +0,0 @@ -/* - * modified from SH-IPL+g (init-r0p751rlc0011rl.S) - * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz) - * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -*/ - -#include <config.h> -#include <version.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - .text - .align 2 - -lowlevel_init: - - write32 CCR_A, CCR_D_D - - write32 MMUCR_A, MMUCR_D - - write32 BCR1_A, BCR1_D - - write16 BCR2_A, BCR2_D - - write16 BCR3_A, BCR3_D - - write32 BCR4_A, BCR4_D - - write32 WCR1_A, WCR1_D - - write32 WCR2_A, WCR2_D - - write32 WCR3_A, WCR3_D - - write16 PCR_A, PCR_D - - write16 LED_A, LED_D - - write32 MCR_A, MCR_D1 - - write16 RTCNT_A, RTCNT_D - - write16 RTCOR_A, RTCOR_D - - write16 RFCR_A, RFCR_D - - write16 RTCSR_A, RTCSR_D - - write8 SDMR3_A, SDMR3_D0 - - /* Wait DRAM refresh 30 times */ - mov.l RFCR_A, r1 - mov #30, r3 -1: - mov.w @r1, r0 - extu.w r0, r2 - cmp/hi r3, r2 - bf 1b - - write32 MCR_A, MCR_D2 - - write8 SDMR3_A, SDMR3_D1 - - write32 IRLMASK_A, IRLMASK_D - - write32 CCR_A, CCR_D_E - - rts - nop - - .align 2 -CCR_A: .long CCR /* Cache Control Register */ -CCR_D_D: .long 0x0808 /* Flush the cache, disable */ -CCR_D_E: .long 0x8000090B - -FRQCR_A: .long FRQCR /* FRQCR Address */ -FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ -BCR1_A: .long BCR1 /* BCR1 Address */ -BCR1_D: .long 0x00180008 -BCR2_A: .long BCR2 /* BCR2 Address */ -BCR2_D: .long 0xabe8 -BCR3_A: .long BCR3 /* BCR3 Address */ -BCR3_D: .long 0x0000 -BCR4_A: .long BCR4 /* BCR4 Address */ -BCR4_D: .long 0x00000010 -WCR1_A: .long WCR1 /* WCR1 Address */ -WCR1_D: .long 0x33343333 -WCR2_A: .long WCR2 /* WCR2 Address */ -WCR2_D: .long 0xcff86fbf -WCR3_A: .long WCR3 /* WCR3 Address */ -WCR3_D: .long 0x07777707 -LED_A: .long 0x04000036 /* LED Address */ -LED_D: .long 0xFF /* LED Data */ -RTCNT_A: .long RTCNT /* RTCNT Address */ -RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ -.align 2 -RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .word 0xA534 /* RTCOR Write Code */ -.align 2 -RTCSR_A: .long RTCSR /* RTCSR Address */ -RTCSR_D: .word 0xA510 /* RTCSR Write Code */ -.align 2 -SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ -SDMR3_D0: .long 0x55 -SDMR3_D1: .long 0x00 -MCR_A: .long MCR /* MCR Address */ -MCR_D1: .long 0x081901F4 /* MRSET:'0' */ -MCR_D2: .long 0x481901F4 /* MRSET:'1' */ -RFCR_A: .long RFCR /* RFCR Address */ -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ -PCR_A: .long PCR /* PCR Address */ -PCR_D: .long 0x0000 -MMUCR_A: .long MMUCR /* MMUCCR Address */ -MMUCR_D: .long 0x00000000 /* MMUCCR Data */ -IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */ -IRLMASK_D: .long 0x00000000 /* IRLMASK Data */ diff --git a/qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c b/qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c deleted file mode 100644 index 249c35f3a..000000000 --- a/qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2007,2008 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ide.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("BOARD: Renesas Solutions R2D Plus\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -int board_late_init(void) -{ - return 0; -} - -#define FPGA_BASE 0xA4000000 -#define FPGA_CFCTL (FPGA_BASE + 0x04) -#define CFCTL_EN (0x432) -#define FPGA_CFPOW (FPGA_BASE + 0x06) -#define CFPOW_ON (0x02) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) -#define CFCDINTCLR_EN (0x01) - -void ide_set_reset(int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) { - outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */ - outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */ - outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */ - } -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7751_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/qemu/roms/u-boot/board/renesas/r7780mp/Makefile b/qemu/roms/u-boot/board/renesas/r7780mp/Makefile deleted file mode 100644 index 8dab4358c..000000000 --- a/qemu/roms/u-boot/board/renesas/r7780mp/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# -# board/r7780mp/Makefile -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := r7780mp.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/r7780mp/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/r7780mp/lowlevel_init.S deleted file mode 100644 index 471af1d96..000000000 --- a/qemu/roms/u-boot/board/renesas/r7780mp/lowlevel_init.S +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * - * u-boot/board/r7780mp/lowlevel_init.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write32 CCR_A, CCR_D /* Address of Cache Control Register */ - /* Instruction Cache Invalidate */ - - write32 FRQCR_A, FRQCR_D /* Frequency control register */ - - /* pin_multi_setting */ - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1 - - write32 BBG_PMSR1_A, BBG_PMSR1_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2 - - write32 BBG_PMSR2_A, BBG_PMSR2_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3 - - write32 BBG_PMSR3_A, BBG_PMSR3_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4 - - write32 BBG_PMSR4_A, BBG_PMSR4_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG - - write32 BBG_PMSRG_A, BBG_PMSRG_D - - /* cpg_setting */ - write32 FRQCR_A, FRQCR_D - - write32 DLLCSR_A, DLLCSR_D - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* wait 200us */ - mov.l REPEAT0_R3, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - /* bsc_setting */ - write32 MMSELR_A, MMSELR_D - - write32 BCR_A, BCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS1BCR_A, CS1BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5BCR_A, CS5BCR_D - - write32 CS6BCR_A, CS6BCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS1WCR_A, CS1WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5WCR_A, CS5WCR_D - - write32 CS6WCR_A, CS6WCR_D - - write32 CS5PCR_A, CS5PCR_D - - write32 CS6PCR_A, CS6PCR_D - - /* ddr_setting */ - /* wait 200us */ - mov.l REPEAT0_R3, r3 - mov #0, r2 -repeat1: - add #1, r2 - cmp/hs r3, r2 - bf repeat1 - nop - - mov.l MIM_U_A, r0 - mov.l MIM_U_D, r1 - synco - mov.l r1, @r0 - synco - - mov.l MIM_L_A, r0 - mov.l MIM_L_D0, r1 - synco - mov.l r1, @r0 - synco - - mov.l STR_L_A, r0 - mov.l STR_L_D, r1 - synco - mov.l r1, @r0 - synco - - mov.l SDR_L_A, r0 - mov.l SDR_L_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D0, r1 - synco - mov.l r1, @r0 - synco - - mov.l SCR_L_A, r0 - mov.l SCR_L_D1, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l EMRS_A, r0 - mov.l EMRS_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l MRS1_A, r0 - mov.l MRS1_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D2, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D3, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D4, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l MRS2_A, r0 - mov.l MRS2_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D5, r1 - synco - mov.l r1, @r0 - synco - - /* wait 200us */ - mov.l REPEAT0_R1, r3 - mov #0, r2 -repeat2: - add #1, r2 - cmp/hs r3, r2 - bf repeat2 - - synco - - mov.l MIM_L_A, r0 - mov.l MIM_L_D1, r1 - synco - mov.l r1, @r0 - synco - - rts - nop - .align 4 - -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA507 -RWTCNT_D: .word 0x5A00 - .align 2 - -BBG_PMMR_A: .long 0xFF800010 -BBG_PMSR1_A: .long 0xFF800014 -BBG_PMSR2_A: .long 0xFF800018 -BBG_PMSR3_A: .long 0xFF80001C -BBG_PMSR4_A: .long 0xFF800020 -BBG_PMSRG_A: .long 0xFF800024 - -BBG_PMMR_D_PMSR1: .long 0xffffbffd -BBG_PMSR1_D: .long 0x00004002 -BBG_PMMR_D_PMSR2: .long 0xfc21a7ff -BBG_PMSR2_D: .long 0x03de5800 -BBG_PMMR_D_PMSR3: .long 0xfffffff8 -BBG_PMSR3_D: .long 0x00000007 -BBG_PMMR_D_PMSR4: .long 0xdffdfff9 -BBG_PMSR4_D: .long 0x20020006 -BBG_PMMR_D_PMSRG: .long 0xffffffff -BBG_PMSRG_D: .long 0x00000000 - -FRQCR_A: .long FRQCR -DLLCSR_A: .long 0xffc40010 -FRQCR_D: .long 0x40233035 -DLLCSR_D: .long 0x00000000 - -/* for DDR-SDRAM */ -MIM_U_A: .long MIM_1 -MIM_L_A: .long MIM_2 -SCR_U_A: .long SCR_1 -SCR_L_A: .long SCR_2 -STR_U_A: .long STR_1 -STR_L_A: .long STR_2 -SDR_U_A: .long SDR_1 -SDR_L_A: .long SDR_2 - -EMRS_A: .long 0xFEC02000 -MRS1_A: .long 0xFEC00B08 -MRS2_A: .long 0xFEC00308 - -MIM_U_D: .long 0x00004000 -MIM_L_D0: .long 0x03e80009 -MIM_L_D1: .long 0x03e80209 -SCR_L_D0: .long 0x3 -SCR_L_D1: .long 0x2 -SCR_L_D2: .long 0x2 -SCR_L_D3: .long 0x4 -SCR_L_D4: .long 0x4 -SCR_L_D5: .long 0x0 -STR_L_D: .long 0x000f0000 -SDR_L_D: .long 0x00000400 -EMRS_D: .long 0x0 -MRS1_D: .long 0x0 -MRS2_D: .long 0x0 - -/* Cache Controller */ -CCR_A: .long CCR -MMUCR_A: .long MMUCR -RWTCNT_A: .long WTCNT - -CCR_D: .long 0x0000090b -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff - -/* local Bus State Controller */ -MMSELR_A: .long MMSELR -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS1BCR_A: .long CS1BCR -CS2BCR_A: .long CS2BCR -CS4BCR_A: .long CS4BCR -CS5BCR_A: .long CS5BCR -CS6BCR_A: .long CS6BCR -CS0WCR_A: .long CS0WCR -CS1WCR_A: .long CS1WCR -CS2WCR_A: .long CS2WCR -CS4WCR_A: .long CS4WCR -CS5WCR_A: .long CS5WCR -CS6WCR_A: .long CS6WCR -CS5PCR_A: .long CS5PCR -CS6PCR_A: .long CS6PCR - -MMSELR_D: .long 0xA5A50003 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777770 -CS4BCR_D: .long 0x77777770 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777770 -CS0WCR_D: .long 0x00020006 -CS1WCR_D: .long 0x00232304 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x00101006 -CS6WCR_D: .long 0x77777703 -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 - -REPEAT0_R3: .long 0x00002000 -REPEAT0_R1: .long 0x0000200 diff --git a/qemu/roms/u-boot/board/renesas/r7780mp/r7780mp.c b/qemu/roms/u-boot/board/renesas/r7780mp/r7780mp.c deleted file mode 100644 index 783352d47..000000000 --- a/qemu/roms/u-boot/board/renesas/r7780mp/r7780mp.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ide.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <netdev.h> -#include "r7780mp.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ -#if defined(CONFIG_R7780MP) - puts("BOARD: Renesas Solutions R7780MP\n"); -#else - puts("BOARD: Renesas Solutions R7780RP\n"); -#endif - return 0; -} - -int board_init(void) -{ - /* SCIF Enable */ - writew(0x0, PHCR); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ - -} - -void ide_set_reset(int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) { - writew(0x432, FPGA_CFCTL); -#if defined(CONFIG_R7780MP) - writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); -#else - writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); -#endif - writew(0x01, FPGA_CFCDINTCLR); - } -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - /* return >= 0 if a chip is found, the board's AX88796L is n2k-based */ - return ne2k_register() + pci_eth_init(bis); -} diff --git a/qemu/roms/u-boot/board/renesas/r7780mp/r7780mp.h b/qemu/roms/u-boot/board/renesas/r7780mp/r7780mp.h deleted file mode 100644 index 110268935..000000000 --- a/qemu/roms/u-boot/board/renesas/r7780mp/r7780mp.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2007 Nobuhiro Iwamatsu - * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - * - * u-boot/board/r7780mp/r7780mp.h - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _BOARD_R7780MP_R7780MP_H_ -#define _BOARD_R7780MP_R7780MP_H_ - -/* R7780MP's FPGA register map */ -#define FPGA_BASE 0xa4000000 -#define FPGA_IRLMSK (FPGA_BASE + 0x00) -#define FPGA_IRLMON (FPGA_BASE + 0x02) -#define FPGA_IRLPRI1 (FPGA_BASE + 0x04) -#define FPGA_IRLPRI2 (FPGA_BASE + 0x06) -#define FPGA_IRLPRI3 (FPGA_BASE + 0x08) -#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) -#define FPGA_RSTCTL (FPGA_BASE + 0x0C) -#define FPGA_PCIBD (FPGA_BASE + 0x0E) -#define FPGA_PCICD (FPGA_BASE + 0x10) -#define FPGA_EXTGIO (FPGA_BASE + 0x16) -#define FPGA_IVDRMON (FPGA_BASE + 0x18) -#define FPGA_IVDRCR (FPGA_BASE + 0x1A) -#define FPGA_OBLED (FPGA_BASE + 0x1C) -#define FPGA_OBSW (FPGA_BASE + 0x1E) -#define FPGA_TPCTL (FPGA_BASE + 0x100) -#define FPGA_TPDCKCTL (FPGA_BASE + 0x102) -#define FPGA_TPCLR (FPGA_BASE + 0x104) -#define FPGA_TPXPOS (FPGA_BASE + 0x106) -#define FPGA_TPYPOS (FPGA_BASE + 0x108) -#define FPGA_DBSW (FPGA_BASE + 0x200) -#define FPGA_VERSION (FPGA_BASE + 0x700) -#define FPGA_CFCTL (FPGA_BASE + 0x300) -#define FPGA_CFPOW (FPGA_BASE + 0x302) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) -#define FPGA_PMR (FPGA_BASE + 0x900) - -#endif /* _BOARD_R7780RP_R7780RP_H_ */ diff --git a/qemu/roms/u-boot/board/renesas/rsk7203/Makefile b/qemu/roms/u-boot/board/renesas/rsk7203/Makefile deleted file mode 100644 index 16acfaf40..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7203/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# Copyright (C) 2008 Renesas Solutions Corp. -# -# u-boot/board/rsk7203/Makefile -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := rsk7203.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/rsk7203/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/rsk7203/lowlevel_init.S deleted file mode 100644 index c8494ccf3..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7203/lowlevel_init.S +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <config.h> -#include <version.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Cache setting */ - write32 CCR1_A ,CCR1_D - - /* ConfigurePortPins */ - write16 PECRL3_A, PECRL3_D - - write16 PCCRL4_A, PCCRL4_D0 - - write16 PECRL4_A, PECRL4_D0 - - write16 PEIORL_A, PEIORL_D0 - - write16 PCIORL_A, PCIORL_D - - write16 PFCRH2_A, PFCRH2_D - - write16 PFCRH3_A, PFCRH3_D - - write16 PFCRH1_A, PFCRH1_D - - write16 PFIORH_A, PFIORH_D - - write16 PECRL1_A, PECRL1_D0 - - write16 PEIORL_A, PEIORL_D1 - - /* Configure Operating Frequency */ - write16 WTCSR_A, WTCSR_D0 - - write16 WTCSR_A, WTCSR_D1 - - write16 WTCNT_A, WTCNT_D - - /* Set clock mode*/ - write16 FRQCR_A, FRQCR_D - - /* Configure Bus And Memory */ -init_bsc_cs0: - write16 PCCRL4_A, PCCRL4_D1 - - write16 PECRL1_A, PECRL1_D1 - - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS0WCR_A, CS0WCR_D - -init_bsc_cs1: - write16 PECRL4_A, PECRL4_D1 - - write32 CS1WCR_A, CS1WCR_D - -init_sdram: - write16 PCCRL2_A, PCCRL2_D - - write16 PCCRL4_A, PCCRL4_D2 - - write16 PCCRL1_A, PCCRL1_D - - write16 PCCRL3_A, PCCRL3_D - - write32 CS3BCR_A, CS3BCR_D - - write32 CS3WCR_A, CS3WCR_D - - write32 SDCR_A, SDCR_D - - write32 RTCOR_A, RTCOR_D - - write32 RTCSR_A, RTCSR_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B -PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .word 0x0000 -.align 2 -PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .word 0x0000 -.align 2 -PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .word 0x0000 -.align 2 -PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .word 0x1C00 -PEIORL_D1: .word 0x1C02 -PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .word 0x4000 -.align 2 -PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .word 0x0000 -.align 2 -PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .word 0x0000 -.align 2 -PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .word 0x0000 -.align 2 -PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .word 0x0729 -.align 2 -PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .word 0x0033 -.align 2 - - -WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .word 0xA518 -WTCSR_D1: .word 0xA51D -WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .word 0x5A84 -.align 2 -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x0104 -.align 2 - -PCCRL4_D1: .word 0x0010 -PECRL1_D1: .word 0x0133 - -CMNCR_A: .long 0xFFFC0000 -CMNCR_D: .long 0x00001810 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x10000400 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .word 0x0100 -.align 2 -CS1WCR_A: .long 0xFFFC002C -CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .word 0x0011 -.align 2 -PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .word 0x0011 -.align 2 -PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .word 0x1111 -.align 2 -PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .word 0x1010 -.align 2 -PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .word 0x0011 -.align 2 -PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .word 0x00011 -.align 2 -PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .word 0x1111 -.align 2 -PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .word 0x1000 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x00002892 -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000809 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0041 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xa55a0010 - -SDRAM_MODE: .long 0xFFFC5040 -REPEAT_D: .long 0x00009C40 diff --git a/qemu/roms/u-boot/board/renesas/rsk7203/rsk7203.c b/qemu/roms/u-boot/board/renesas/rsk7203/rsk7203.c deleted file mode 100644 index 8800371b0..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7203/rsk7203.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * u-boot/board/rsk7203/rsk7203.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("BOARD: Renesas Technology RSK7203\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC9118 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/qemu/roms/u-boot/board/renesas/rsk7264/Makefile b/qemu/roms/u-boot/board/renesas/rsk7264/Makefile deleted file mode 100644 index 7ada697c8..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7264/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2011 Renesas Electronics Europe Ltd. -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := rsk7264.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/rsk7264/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/rsk7264/lowlevel_init.S deleted file mode 100644 index 1a7d27d17..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7264/lowlevel_init.S +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Electronics Europe Ltd. - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on board/renesas/rsk7203/lowlevel_init.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <config.h> -#include <version.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Cache setting */ - write32 CCR1_A ,CCR1_D - - /* io_set_cpg */ - write8 STBCR3_A, STBCR3_D - write8 STBCR4_A, STBCR4_D - write8 STBCR5_A, STBCR5_D - write8 STBCR6_A, STBCR6_D - write8 STBCR7_A, STBCR7_D - write8 STBCR8_A, STBCR8_D - - /* ConfigurePortPins */ - - /* Leaving LED1 ON for sanity test */ - write16 PJCR1_A, PJCR1_D1 - write16 PJCR2_A, PJCR2_D - write16 PJIOR0_A, PJIOR0_D1 - write16 PJDR0_A, PJDR0_D - write16 PJPR0_A, PJPR0_D - - /* Configure EN_PIN & RS_PIN */ - write16 PGCR2_A, PGCR2_D - write16 PGIOR0_A, PGIOR0_D - - /* Configure the port pins connected to UART */ - write16 PJCR1_A, PJCR1_D2 - write16 PJIOR0_A, PJIOR0_D2 - - /* Configure Operating Frequency */ - write16 WTCSR_A, WTCSR_D0 - write16 WTCSR_A, WTCSR_D1 - write16 WTCNT_A, WTCNT_D - - /* Control of RESBANK */ - write16 IBNR_A, IBNR_D - /* Enable SCIF3 module */ - write16 STBCR4_A, STBCR4_D - - /* Set clock mode*/ - write16 FRQCR_A, FRQCR_D - - /* Configure Bus And Memory */ -init_bsc_cs0: - -pfc_settings: - write16 PCCR2_A, PCCR2_D - write16 PCCR1_A, PCCR1_D - write16 PCCR0_A, PCCR0_D - - write16 PBCR0_A, PBCR0_D - write16 PBCR1_A, PBCR1_D - write16 PBCR2_A, PBCR2_D - write16 PBCR3_A, PBCR3_D - write16 PBCR4_A, PBCR4_D - write16 PBCR5_A, PBCR5_D - - write16 PDCR0_A, PDCR0_D - write16 PDCR1_A, PDCR1_D - write16 PDCR2_A, PDCR2_D - write16 PDCR3_A, PDCR3_D - - write32 CS0WCR_A, CS0WCR_D - write32 CS0BCR_A, CS0BCR_D - -init_bsc_cs2: - write16 PJCR0_A, PJCR0_D - write32 CS2WCR_A, CS2WCR_D - -init_sdram: - write32 CS3BCR_A, CS3BCR_D - write32 CS3WCR_A, CS3WCR_D - write32 SDCR_A, SDCR_D - write32 RTCOR_A, RTCOR_D - write32 RTCSR_A, RTCSR_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x1003 -.align 2 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000002 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .word 0x0000 -.align 2 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000010 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 -STBCR7_A: .long 0xFFFE0418 -STBCR7_D: .long 0x0000002A -STBCR8_A: .long 0xFFFE041C -STBCR8_D: .long 0x0000007E -PJCR1_A: .long 0xFFFE390C -PJCR1_D1: .word 0x0000 -PJCR1_D2: .word 0x0022 -PJCR2_A: .long 0xFFFE390A -PJCR2_D: .word 0x0000 -.align 2 -PJIOR0_A: .long 0xFFFE3912 -PJIOR0_D1: .word 0x0FC0 -PJIOR0_D2: .word 0x0FE0 -PJDR0_A: .long 0xFFFE3916 -PJDR0_D: .word 0x0FBF -.align 2 -PJPR0_A: .long 0xFFFE391A -PJPR0_D: .long 0x00000FBF -PGCR2_A: .long 0xFFFE38CA -PGCR2_D: .word 0x0000 -.align 2 -PGIOR0_A: .long 0xFFFE38D2 -PGIOR0_D: .word 0x03F0 -.align 2 -WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .word 0x0000 -WTCSR_D1: .word 0x0000 -WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .word 0x0000 -.align 2 -PCCR0_A: .long 0xFFFE384E -PDCR0_A: .long 0xFFFE386E -PDCR1_A: .long 0xFFFE386C -PDCR2_A: .long 0xFFFE386A -PDCR3_A: .long 0xFFFE3868 -PBCR0_A: .long 0xFFFE382E -PBCR1_A: .long 0xFFFE382C -PBCR2_A: .long 0xFFFE382A -PBCR3_A: .long 0xFFFE3828 -PBCR4_A: .long 0xFFFE3826 -PBCR5_A: .long 0xFFFE3824 -PCCR0_D: .word 0x1111 -PDCR0_D: .word 0x1111 -PDCR1_D: .word 0x1111 -PDCR2_D: .word 0x1111 -PDCR3_D: .word 0x1111 -PBCR0_D: .word 0x1110 -PBCR1_D: .word 0x1111 -PBCR2_D: .word 0x1111 -PBCR3_D: .word 0x1111 -PBCR4_D: .word 0x1111 -PBCR5_D: .word 0x0111 -.align 2 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000B41 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x10000400 -PJCR0_A: .long 0xFFFE390E -PJCR0_D: .word 0x3300 -.align 2 -CS2WCR_A: .long 0xFFFC0030 -CS2WCR_D: .long 0x00000B01 -PCCR2_A: .long 0xFFFE384A -PCCR2_D: .word 0x0001 -.align 2 -PCCR1_A: .long 0xFFFE384C -PCCR1_D: .word 0x1111 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x0000288A -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000812 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0046 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xA55A0010 -IBNR_A: .long 0xFFFE080E -IBNR_D: .word 0x0000 -.align 2 -SDRAM_MODE: .long 0xFFFC5040 -REPEAT_D: .long 0x00000085 diff --git a/qemu/roms/u-boot/board/renesas/rsk7264/rsk7264.c b/qemu/roms/u-boot/board/renesas/rsk7264/rsk7264.c deleted file mode 100644 index d938b3a7b..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7264/rsk7264.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Electronics Europe Ltd. - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on u-boot/board/rsk7264/rsk7203.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("BOARD: Renesas Technology RSK7264\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC89218 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/qemu/roms/u-boot/board/renesas/rsk7269/Makefile b/qemu/roms/u-boot/board/renesas/rsk7269/Makefile deleted file mode 100644 index 0f053d8fa..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7269/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2012 Renesas Electronics Europe Ltd. -# Copyright (C) 2012 Phil Edworthy -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := rsk7269.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/rsk7269/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/rsk7269/lowlevel_init.S deleted file mode 100644 index a2b174bbc..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7269/lowlevel_init.S +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Electronics Europe Ltd. - * Copyright (C) 2012 Phil Edworthy - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on board/renesas/rsk7264/lowlevel_init.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <config.h> -#include <version.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Flush and enable caches (data cache in write-through mode) */ - write32 CCR1_A ,CCR1_D - - /* Disable WDT */ - write16 WTCSR_A, WTCSR_D - write16 WTCNT_A, WTCNT_D - - /* Disable Register Bank interrupts */ - write16 IBNR_A, IBNR_D - - /* Set clocks based on 13.225MHz xtal */ - write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */ - - /* Enable all peripherals */ - write8 STBCR3_A, STBCR3_D - write8 STBCR4_A, STBCR4_D - write8 STBCR5_A, STBCR5_D - write8 STBCR6_A, STBCR6_D - write8 STBCR7_A, STBCR7_D - write8 STBCR8_A, STBCR8_D - write8 STBCR9_A, STBCR9_D - write8 STBCR10_A, STBCR10_D - - /* SCIF7 and IIC2 */ - write16 PJCR3_A, PJCR3_D /* TXD7 */ - write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */ - - /* Configure bus (CS0) */ - write16 PFCR3_A, PFCR3_D /* A24 */ - write16 PFCR2_A, PFCR2_D /* A23 and CS1# */ - write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */ - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ - write32 CS0WCR_A, CS0WCR_D - write32 CS0BCR_A, CS0BCR_D - - /* Configure SDRAM (CS3) */ - write16 PCCR2_A, PCCR2_D /* CS3# */ - write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */ - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ - write32 CS3BCR_A, CS3BCR_D - write32 CS3WCR_A, CS3WCR_D - write32 SDCR_A, SDCR_D - write32 RTCOR_A, RTCOR_D - write32 RTCSR_A, RTCSR_D - - /* Configure ethernet (CS1) */ - write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */ - write16 PHCR0_A, PHCR0_D - write16 PFCR2_A, PFCR2_D /* CS1# */ - write32 CS1BCR_A, CS1BCR_D /* Big endian */ - write32 CS1WCR_A, CS1WCR_D /* 1 cycle */ - write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */ - write16 PJIOR1_A, PJIOR1_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B - -STBCR3_A: .long 0xFFFE0408 -STBCR4_A: .long 0xFFFE040C -STBCR5_A: .long 0xFFFE0410 -STBCR6_A: .long 0xFFFE0414 -STBCR7_A: .long 0xFFFE0418 -STBCR8_A: .long 0xFFFE041C -STBCR9_A: .long 0xFFFE0440 -STBCR10_A: .long 0xFFFE0444 -STBCR3_D: .long 0x0000001A -STBCR4_D: .long 0x00000000 -STBCR5_D: .long 0x00000000 -STBCR6_D: .long 0x00000000 -STBCR7_D: .long 0x00000012 -STBCR8_D: .long 0x00000009 -STBCR9_D: .long 0x00000000 -STBCR10_D: .long 0x00000010 - -WTCSR_A: .long 0xFFFE0000 -WTCNT_A: .long 0xFFFE0002 -WTCSR_D: .word 0xA518 -WTCNT_D: .word 0x5A00 - -IBNR_A: .long 0xFFFE080E -IBNR_D: .word 0x0000 -.align 2 -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x0015 -.align 2 - -PJCR3_A: .long 0xFFFE3908 -PJCR3_D: .word 0x5000 -.align 2 -PECR1_A: .long 0xFFFE388C -PECR1_D: .word 0x2011 -.align 2 - -PFCR3_A: .long 0xFFFE38A8 -PFCR2_A: .long 0xFFFE38AA -PBCR5_A: .long 0xFFFE3824 -PFCR3_D: .word 0x0010 -PFCR2_D: .word 0x0101 -PBCR5_D: .word 0x0111 -.align 2 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000341 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x00000400 - -PCCR2_A: .long 0xFFFE384A -PCCR1_A: .long 0xFFFE384C -PCCR0_A: .long 0xFFFE384E -PCCR2_D: .word 0x0001 -PCCR1_D: .word 0x1111 -PCCR0_D: .word 0x1111 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x00004912 -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000811 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0035 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xA55A0010 -.align 2 -SDRAM_MODE: .long 0xFFFC5460 -REPEAT_D: .long 0x000033F1 - -PHCR1_A: .long 0xFFFE38EC -PHCR0_A: .long 0xFFFE38EE -PHCR1_D: .word 0x2222 -PHCR0_D: .word 0x2222 -.align 2 -CS1BCR_A: .long 0xFFFC0008 -CS1BCR_D: .long 0x00000400 -CS1WCR_A: .long 0xFFFC002C -CS1WCR_D: .long 0x00000080 -PJDR1_A: .long 0xFFFE3914 -PJDR1_D: .word 0x0000 -.align 2 -PJIOR1_A: .long 0xFFFE3910 -PJIOR1_D: .word 0x8000 -.align 2 diff --git a/qemu/roms/u-boot/board/renesas/rsk7269/rsk7269.c b/qemu/roms/u-boot/board/renesas/rsk7269/rsk7269.c deleted file mode 100644 index ae32b6a6d..000000000 --- a/qemu/roms/u-boot/board/renesas/rsk7269/rsk7269.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Electronics Europe Ltd. - * Copyright (C) 2012 Phil Edworthy - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on u-boot/board/rsk7264/rsk7264.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("BOARD: Renesas RSK7269\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC89218 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/qemu/roms/u-boot/board/renesas/sh7752evb/Makefile b/qemu/roms/u-boot/board/renesas/sh7752evb/Makefile deleted file mode 100644 index 856af8138..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7752evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := sh7752evb.o spi-boot.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/sh7752evb/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/sh7752evb/lowlevel_init.S deleted file mode 100644 index 5643a697e..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7752evb/lowlevel_init.S +++ /dev/null @@ -1,447 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - /*------- GPIO -------*/ - write16 PDCR_A, PDCR_D ! SPI0 - write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1) - write16 PJCR_A, PJCR_D ! SCIF4 - write16 PTCR_A, PTCR_D ! STATUS - write16 PSEL1_A, PSEL1_D ! SPI0 - write16 PSEL2_A, PSEL2_D ! SPI0 - write16 PSEL5_A, PSEL5_D ! STATUS - - bra exit_gpio - nop - - .align 2 - -/*------- GPIO -------*/ -PDCR_A: .long 0xffec0006 -PGCR_A: .long 0xffec000c -PJCR_A: .long 0xffec0012 -PTCR_A: .long 0xffec0026 -PSEL1_A: .long 0xffec0072 -PSEL2_A: .long 0xffec0074 -PSEL5_A: .long 0xffec007a - -PDCR_D: .long 0x0000 -PGCR_D: .long 0x0004 -PJCR_D: .long 0x0000 -PTCR_D: .long 0x0000 -PSEL1_D: .long 0x0000 -PSEL2_D: .long 0x3000 -PSEL5_D: .long 0x0ffc - - .align 2 - -exit_gpio: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM (PC=0x5???????) or not. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DDR3IF is not necessary. - */ - bra exit_ddr - nop - -1: - /*------- Reset -------*/ - write32 MRSTCR0_A, MRSTCR0_D - write32 MRSTCR1_A, MRSTCR1_D - - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DDR3IF -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 4 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 5 */ - write32 DBKIND_A, DBKIND_D - - /* step 6 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ1_A, DBADJ1_D - write32 DBADJ2_A, DBADJ2_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - - bra exit_ddr - nop - - .align 2 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- Reset -------*/ -MRSTCR0_A: .long 0xffd50030 -MRSTCR0_D: .long 0xfe1ffe7f -MRSTCR1_A: .long 0xffd50034 -MRSTCR1_D: .long 0xfff3ffff - -/*------- DDR3IF -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ1_A: .long 0xfe8000c4 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000005 -DBTR8_D: .long 0x00000015 -DBTR9_D: .long 0x00000006 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x00000056 -DBTR14_D: .long 0x00000006 -DBTR15_D: .long 0x00000004 -DBTR16_D: .long 0x00150002 -DBTR17_D: .long 0x000c0017 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00000000 -DBADJ1_D: .long 0x00000000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x08001000 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 - - .align 2 -exit_ddr: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _stack_ilram, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_stack_ilram: .long 0xe5204000 - -1: - write32 CCR_A, CCR_D - - rts - nop - - .align 2 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/qemu/roms/u-boot/board/renesas/sh7752evb/sh7752evb.c b/qemu/roms/u-boot/board/renesas/sh7752evb/sh7752evb.c deleted file mode 100644 index 5eedbf8ce..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7752evb/sh7752evb.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi_flash.h> - -int checkboard(void) -{ - puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); - - return 0; -} - -static void init_gpio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - struct sermux_regs *sermux = SERMUX_BASE; - - /* GPIO */ - writew(0x0000, &gpio->pacr); /* GETHER */ - writew(0x0001, &gpio->pbcr); /* INTC */ - writew(0x0000, &gpio->pccr); /* PWMU, INTC */ - writew(0xeaff, &gpio->pecr); /* GPIO */ - writew(0x0000, &gpio->pfcr); /* WDT */ - writew(0x0000, &gpio->phcr); /* SPI1 */ - writew(0x0000, &gpio->picr); /* SDHI */ - writew(0x0003, &gpio->pkcr); /* SerMux */ - writew(0x0000, &gpio->plcr); /* SerMux */ - writew(0x0000, &gpio->pmcr); /* RIIC */ - writew(0x0000, &gpio->pncr); /* USB, SGPIO */ - writew(0x0000, &gpio->pocr); /* SGPIO */ - writew(0xd555, &gpio->pqcr); /* GPIO */ - writew(0x0000, &gpio->prcr); /* RIIC */ - writew(0x0000, &gpio->pscr); /* RIIC */ - writeb(0x00, &gpio->pudr); - writew(0x5555, &gpio->pucr); /* Debug LED */ - writew(0x0000, &gpio->pvcr); /* RSPI */ - writew(0x0000, &gpio->pwcr); /* EVC */ - writew(0x0000, &gpio->pxcr); /* LBSC */ - writew(0x0000, &gpio->pycr); /* LBSC */ - writew(0x0000, &gpio->pzcr); /* eMMC */ - writew(0xfe00, &gpio->psel0); - writew(0xff00, &gpio->psel3); - writew(0x771f, &gpio->psel4); - writew(0x00ff, &gpio->psel6); - writew(0xfc00, &gpio->psel7); - - writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void init_gether_mdio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); - writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - eth_parse_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} - -int board_init(void) -{ - init_gpio(); - set_pmb_on_board_init(); - - init_usb_phy(); - init_gether_mdio(); - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - - return 0; -} - -int board_mmc_init(bd_t *bis) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); - writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ - udelay(1); - writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ - udelay(200); - - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], - SH7752EVB_ETHERNET_MAC_SIZE); - mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Gigabit Ethernet */ - for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - setenv("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - setenv(env_string, mac_string); - } - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - - return 0; -} - -int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 3) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - printf("GETHERC ch%d = %s\n", i, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s", - argv[1], argv[2]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, - SH7752EVB_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase failed.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 3, 1, do_write_mac, - "write MAC address for GETHERC", - "[GETHERC ch0] [GETHERC ch1]\n" -); diff --git a/qemu/roms/u-boot/board/renesas/sh7752evb/spi-boot.c b/qemu/roms/u-boot/board/renesas/sh7752evb/spi-boot.c deleted file mode 100644 index 91565d44d..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7752evb/spi-boot.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License. See the file "COPYING.LIB" in the main - * directory of this archive for more details. - */ - -#include <common.h> - -#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE -#define CONFIG_SPI_ADDR 0x00000000 -#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN -#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SpiS0 0x02 -#define SPI_SSS 0x01 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - int timeout = 0x00100000; - - /* Make sure the last transaction is finalized */ - spi_write(0x00, CR3); - spi_write(0x02, CR1); - while (!(spi_read(CR4) & SPI_SpiS0)) { - if (timeout-- < 0) - break; - } - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); - - spi_write(0, SPIDMCOR); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(M25_READ, TBR); - spi_write((addr >> 16) & 0xFF, TBR); - spi_write((addr >> 8) & 0xFF, TBR); - spi_write(addr & 0xFF, TBR); - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; - - /* Nagate SP0-SS0 */ - spi_write(0, CR1); -} - -void __uses_spiboot2 spiboot_main(void) -{ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, - CONFIG_SPI_LENGTH); - - _start(); -} diff --git a/qemu/roms/u-boot/board/renesas/sh7752evb/u-boot.lds b/qemu/roms/u-boot/board/renesas/sh7752evb/u-boot.lds deleted file mode 100644 index 053df642e..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7752evb/u-boot.lds +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2012 - * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh4/start.o (.text)) - *(.spiboot1.text) - *(.spiboot2.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss (NOLOAD) : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/qemu/roms/u-boot/board/renesas/sh7753evb/Makefile b/qemu/roms/u-boot/board/renesas/sh7753evb/Makefile deleted file mode 100644 index f7c8e949f..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7753evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := sh7753evb.o spi-boot.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/sh7753evb/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/sh7753evb/lowlevel_init.S deleted file mode 100644 index 21987a51e..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7753evb/lowlevel_init.S +++ /dev/null @@ -1,416 +0,0 @@ -/* - * Copyright (C) 2013 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM (PC=0x5???????) or not. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DBSC3 is not necessary. - */ - bra exit_ddr - nop - -1: - /*------- Reset -------*/ - write32 MRSTCR0_A, MRSTCR0_D - write32 MRSTCR1_A, MRSTCR1_D - - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DBSC3 -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBKIND_A, DBKIND_D - - /* step 4 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ2_A, DBADJ2_D - - /* step 5 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 6 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - write32 DBPDNCNF_A, DBPDNCNF_D - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBCALTR_A, DBCALTR_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - - bra exit_ddr - nop - - .align 2 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- Reset -------*/ -MRSTCR0_A: .long 0xffd50030 -MRSTCR0_D: .long 0xfe1ffe7f -MRSTCR1_A: .long 0xffd50034 -MRSTCR1_D: .long 0xfff3ffff - -/*------- DBSC3 -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c -DBCALTR_A: .long 0xfe8000f8 -DBPDNCNF_A: .long 0xfe800180 - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000004 -DBTR8_D: .long 0x00000014 -DBTR9_D: .long 0x00000004 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x000000a0 -DBTR14_D: .long 0x00060006 -DBTR15_D: .long 0x00000003 -DBTR16_D: .long 0x00160002 -DBTR17_D: .long 0x000c0000 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00010000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x00081040 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 -DBCALTR_D: .long 0x08200820 -DBPDNCNF_D: .long 0x00000001 - - .align 2 -exit_ddr: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _stack_ilram, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_stack_ilram: .long 0xe5204000 - -1: - write32 CCR_A, CCR_D - - rts - nop - - .align 2 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/qemu/roms/u-boot/board/renesas/sh7753evb/sh7753evb.c b/qemu/roms/u-boot/board/renesas/sh7753evb/sh7753evb.c deleted file mode 100644 index 42b920fb3..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7753evb/sh7753evb.c +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi_flash.h> - -int checkboard(void) -{ - puts("BOARD: SH7753 EVB\n"); - - return 0; -} - -static void init_gpio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - struct sermux_regs *sermux = SERMUX_BASE; - - /* GPIO */ - writew(0x0000, &gpio->pacr); /* GETHER */ - writew(0x0001, &gpio->pbcr); /* INTC */ - writew(0x0000, &gpio->pccr); /* PWMU, INTC */ - writew(0x0000, &gpio->pdcr); /* SPI0 */ - writew(0xeaff, &gpio->pecr); /* GPIO */ - writew(0x0000, &gpio->pfcr); /* WDT */ - writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ - writew(0x0000, &gpio->phcr); /* SPI1 */ - writew(0x0000, &gpio->picr); /* SDHI */ - writew(0x0000, &gpio->pjcr); /* SCIF4 */ - writew(0x0003, &gpio->pkcr); /* SerMux */ - writew(0x0000, &gpio->plcr); /* SerMux */ - writew(0x0000, &gpio->pmcr); /* RIIC */ - writew(0x0000, &gpio->pncr); /* USB, SGPIO */ - writew(0x0000, &gpio->pocr); /* SGPIO */ - writew(0xd555, &gpio->pqcr); /* GPIO */ - writew(0x0000, &gpio->prcr); /* RIIC */ - writew(0x0000, &gpio->pscr); /* RIIC */ - writew(0x0000, &gpio->ptcr); /* STATUS */ - writeb(0x00, &gpio->pudr); - writew(0x5555, &gpio->pucr); /* Debug LED */ - writew(0x0000, &gpio->pvcr); /* RSPI */ - writew(0x0000, &gpio->pwcr); /* EVC */ - writew(0x0000, &gpio->pxcr); /* LBSC */ - writew(0x0000, &gpio->pycr); /* LBSC */ - writew(0x0000, &gpio->pzcr); /* eMMC */ - writew(0xfe00, &gpio->psel0); - writew(0x0000, &gpio->psel1); - writew(0x3000, &gpio->psel2); - writew(0xff00, &gpio->psel3); - writew(0x771f, &gpio->psel4); - writew(0x0ffc, &gpio->psel5); - writew(0x00ff, &gpio->psel6); - writew(0xfc00, &gpio->psel7); - - writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void init_gether_mdio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); - writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - eth_parse_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} - -int board_init(void) -{ - struct gether_control_regs *gether = GETHER_CONTROL_BASE; - - init_gpio(); - set_pmb_on_board_init(); - - /* Sets TXnDLY to B'010 */ - writel(0x00000202, &gether->gbecont); - - init_usb_phy(); - init_gether_mdio(); - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - - return 0; -} - -int board_mmc_init(bd_t *bis) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); - writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ - udelay(1); - writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ - udelay(200); - - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)], - SH7753EVB_ETHERNET_MAC_SIZE); - mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Gigabit Ethernet */ - for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - setenv("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - setenv(env_string, mac_string); - } - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - - return 0; -} - -int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 3) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - printf("GETHERC ch%d = %s\n", i, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s", - argv[1], argv[2]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, - SH7753EVB_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase failed.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 3, 1, do_write_mac, - "write MAC address for GETHERC", - "[GETHERC ch0] [GETHERC ch1]\n" -); diff --git a/qemu/roms/u-boot/board/renesas/sh7753evb/spi-boot.c b/qemu/roms/u-boot/board/renesas/sh7753evb/spi-boot.c deleted file mode 100644 index 21903d9c7..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7753evb/spi-boot.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (C) 2013 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#define CONFIG_SPI_ADDR 0x00000000 -#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000) -#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE) - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 -#define CR7 0xFE002038 -#define CR8 0xFE002040 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SpiS0 0x02 -#define SPI_SSS 0x01 - -/* CR7 */ -#define CR7_IDX_OR12 0x12 -#define OR12_ADDR32 0x00000001 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 -#define M25_READ_4BYTE 0x13 - -extern void bss_start(void); - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - int timeout = 0x00100000; - - /* Make sure the last transaction is finalized */ - spi_write(0x00, CR3); - spi_write(0x02, CR1); - while (!(spi_read(CR4) & SPI_SpiS0)) { - if (timeout-- < 0) - break; - } - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); - - spi_write(0, SPIDMCOR); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(CR7_IDX_OR12, CR7); - if (spi_read(CR8) & OR12_ADDR32) { - /* 4-bytes address mode */ - spi_write(M25_READ_4BYTE, TBR); - spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */ - } else { - /* 3-bytes address mode */ - spi_write(M25_READ, TBR); - } - spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */ - spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */ - spi_write(addr & 0xFF, TBR); /* ADDR7-0 */ - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; - - /* Nagate SP0-SS0 */ - spi_write(0, CR1); -} - -void __uses_spiboot2 spiboot_main(void) -{ - /* - * This code rounds len up for SPIWDMCNTR. We should set it to 0 in - * lower 5-bits. - */ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len); - - _start(); -} diff --git a/qemu/roms/u-boot/board/renesas/sh7753evb/u-boot.lds b/qemu/roms/u-boot/board/renesas/sh7753evb/u-boot.lds deleted file mode 100644 index 053df642e..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7753evb/u-boot.lds +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2012 - * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh4/start.o (.text)) - *(.spiboot1.text) - *(.spiboot2.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss (NOLOAD) : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/qemu/roms/u-boot/board/renesas/sh7757lcr/Makefile b/qemu/roms/u-boot/board/renesas/sh7757lcr/Makefile deleted file mode 100644 index 1fa3992e1..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7757lcr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := sh7757lcr.o spi-boot.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/sh7757lcr/README.sh7757lcr b/qemu/roms/u-boot/board/renesas/sh7757lcr/README.sh7757lcr deleted file mode 100644 index 3e9c1c1a1..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7757lcr/README.sh7757lcr +++ /dev/null @@ -1,77 +0,0 @@ -======================================== -Renesas R0P7757LC0030RL board -======================================== - -This board specification: -========================= - -The R0P7757LC0030RL(board config name:sh7757lcr) has the following device: - - - SH7757 (SH-4A) - - DDR3-SDRAM 256MB (with ECC) - - SPI ROM 8MB - - 2D Graphic controller - - Ethernet controller - - eMMC 2GB - - -configuration for This board: -============================= - -You can select the configuration as follows: - - - make sh7785lcr_config - - -This board specific command: -============================ - -This board has the following its specific command: - - - sh_g200 - - write_mac - - -1. sh_g200 - -If we run this command, SH4 can control the G200. -The default setting is that SH4 cannot control the G200. - - -2. write_mac - -You can write MAC address to SPI ROM. - - Usage 1) Write MAC address - - write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1] - - For example) - => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83 - *) We have to input the command as a single line - (without carriage return) - *) We have to reset after input the command. - - Usage 2) Show current data - - write_mac - - For example) - => write_mac - ETHERC ch0 = 00:00:87:6c:21:80 - ETHERC ch1 = 00:00:87:6c:21:81 - GETHERC ch0 = 00:00:87:6c:21:82 - GETHERC ch1 = 00:00:87:6c:21:83 - - -Update SPI ROM: -============================ - -1. Copy u-boot image to RAM area. -2. Probe SPI device. - => sf probe 0 - 8192 KiB M25P64 at 0:0 is now current device -3. Erase SPI ROM. - => sf erase 0 80000 -4. Write u-boot image to SPI ROM. - => sf write 0x89000000 0 80000 diff --git a/qemu/roms/u-boot/board/renesas/sh7757lcr/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/sh7757lcr/lowlevel_init.S deleted file mode 100644 index e4c5ea815..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7757lcr/lowlevel_init.S +++ /dev/null @@ -1,546 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - - /*------- GPIO -------*/ - write8 PGDR_A, PGDR_D /* eMMC power off */ - - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D - write16 PHCR_A, PHCR_D - write16 PICR_A, PICR_D - write16 PJCR_A, PJCR_D - write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D - write16 PMCR_A, PMCR_D - write16 PNCR_A, PNCR_D - write16 POCR_A, POCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D - write16 PSCR_A, PSCR_D - write16 PTCR_A, PTCR_D - write16 PUCR_A, PUCR_D - write16 PVCR_A, PVCR_D - write16 PWCR_A, PWCR_D - write16 PXCR_A, PXCR_D - write16 PYCR_A, PYCR_D - write16 PZCR_A, PZCR_D - write16 PSEL0_A, PSEL0_D - write16 PSEL1_A, PSEL1_D - write16 PSEL2_A, PSEL2_D - write16 PSEL3_A, PSEL3_D - write16 PSEL4_A, PSEL4_D - write16 PSEL5_A, PSEL5_D - write16 PSEL6_A, PSEL6_D - write16 PSEL7_A, PSEL7_D - write16 PSEL8_A, PSEL8_D - - bra exit_gpio - nop - - .align 4 - -/*------- GPIO -------*/ -PGDR_A: .long 0xffec0040 -PACR_A: .long 0xffec0000 -PBCR_A: .long 0xffec0002 -PCCR_A: .long 0xffec0004 -PDCR_A: .long 0xffec0006 -PECR_A: .long 0xffec0008 -PFCR_A: .long 0xffec000a -PGCR_A: .long 0xffec000c -PHCR_A: .long 0xffec000e -PICR_A: .long 0xffec0010 -PJCR_A: .long 0xffec0012 -PKCR_A: .long 0xffec0014 -PLCR_A: .long 0xffec0016 -PMCR_A: .long 0xffec0018 -PNCR_A: .long 0xffec001a -POCR_A: .long 0xffec001c -PQCR_A: .long 0xffec0020 -PRCR_A: .long 0xffec0022 -PSCR_A: .long 0xffec0024 -PTCR_A: .long 0xffec0026 -PUCR_A: .long 0xffec0028 -PVCR_A: .long 0xffec002a -PWCR_A: .long 0xffec002c -PXCR_A: .long 0xffec002e -PYCR_A: .long 0xffec0030 -PZCR_A: .long 0xffec0032 -PSEL0_A: .long 0xffec0070 -PSEL1_A: .long 0xffec0072 -PSEL2_A: .long 0xffec0074 -PSEL3_A: .long 0xffec0076 -PSEL4_A: .long 0xffec0078 -PSEL5_A: .long 0xffec007a -PSEL6_A: .long 0xffec007c -PSEL7_A: .long 0xffec0082 -PSEL8_A: .long 0xffec0084 - -PGDR_D: .long 0x80 -PACR_D: .long 0x0000 -PBCR_D: .long 0x0001 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x0000 -PICR_D: .long 0x0000 -PJCR_D: .long 0x0000 -PKCR_D: .long 0x0003 -PLCR_D: .long 0x0000 -PMCR_D: .long 0x0000 -PNCR_D: .long 0x0000 -POCR_D: .long 0x0000 -PQCR_D: .long 0xc000 -PRCR_D: .long 0x0000 -PSCR_D: .long 0x0000 -PTCR_D: .long 0x0000 -#if defined(CONFIG_SH7757_OFFSET_SPI) -PUCR_D: .long 0x0055 -#else -PUCR_D: .long 0x0000 -#endif -PVCR_D: .long 0x0000 -PWCR_D: .long 0x0000 -PXCR_D: .long 0x0000 -PYCR_D: .long 0x0000 -PZCR_D: .long 0x0000 -PSEL0_D: .long 0xfe00 -PSEL1_D: .long 0x0000 -PSEL2_D: .long 0x3000 -PSEL3_D: .long 0xff00 -PSEL4_D: .long 0x771f -PSEL5_D: .long 0x0ffc -PSEL6_D: .long 0x00ff -PSEL7_D: .long 0xfc00 -PSEL8_D: .long 0x0000 - - .align 2 - -exit_gpio: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM, PC is 0x8???????. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DDR3IF is not necessary. - */ - bra exit_ddr - nop - -1: - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DDR3IF -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 4 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 5 */ - write32 DBKIND_A, DBKIND_D - - /* step 6 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ1_A, DBADJ1_D - write32 DBADJ2_A, DBADJ2_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - -#if defined(CONFIG_SH7757LCR_DDR_ECC) - /* enable DDR-ECC */ - write32 ECD_ECDEN_A, ECD_ECDEN_D - write32 ECD_INTSR_A, ECD_INTSR_D - write32 ECD_SPACER_A, ECD_SPACER_D - write32 ECD_MCR_A, ECD_MCR_D -#endif - bra exit_ddr - nop - - .align 4 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- DDR3IF -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ1_A: .long 0xfe8000c4 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000005 -DBTR8_D: .long 0x00000015 -DBTR9_D: .long 0x00000006 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x00000056 -DBTR14_D: .long 0x00000006 -DBTR15_D: .long 0x00000004 -DBTR16_D: .long 0x00150002 -DBTR17_D: .long 0x000c0017 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00000000 -DBADJ1_D: .long 0x00000000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x08001000 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 - -/*------- DDR-ECC -------*/ -ECD_ECDEN_A: .long 0xffc1012c -ECD_ECDEN_D: .long 0x00000001 -ECD_INTSR_A: .long 0xfe900024 -ECD_INTSR_D: .long 0xffffffff -ECD_SPACER_A: .long 0xfe900018 -ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING -ECD_MCR_A: .long 0xfe900010 -ECD_MCR_D: .long 0x00000001 - - .align 2 -exit_ddr: - -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _bss_start, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_bss_start: .long bss_start - -1: - - write32 CCR_A, CCR_D - - rts - nop - - .align 4 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/qemu/roms/u-boot/board/renesas/sh7757lcr/sh7757lcr.c b/qemu/roms/u-boot/board/renesas/sh7757lcr/sh7757lcr.c deleted file mode 100644 index 1464f48b4..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7757lcr/sh7757lcr.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi_flash.h> - -int checkboard(void) -{ - puts("BOARD: R0P7757LC0030RL board\n"); - - return 0; -} - -static void init_gctrl(void) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - unsigned long graofst; - - graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; - writel(graofst | 0x20000f00, &gctrl->gracr3); -} - -static int init_pcie_bridge_from_spi(void *buf, size_t size) -{ - struct spi_flash *spi; - int ret; - unsigned long pcie_addr; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - if (is_sh7757_b0()) - pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0; - else - pcie_addr = SH7757LCR_PCIEBRG_ADDR; - - ret = spi_flash_read(spi, pcie_addr, size, buf); - if (ret) { - printf("%s: spi_flash read error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - return 0; -} - -static void init_pcie_bridge(void) -{ - struct pciebrg_regs *pciebrg = PCIEBRG_BASE; - struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; - int i; - unsigned char *data; - unsigned short tmp; - unsigned long pcie_size; - - if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) - return; - - if (is_sh7757_b0()) - pcie_size = SH7757LCR_PCIEBRG_SIZE_B0; - else - pcie_size = SH7757LCR_PCIEBRG_SIZE; - - data = malloc(pcie_size); - if (!data) { - printf("%s: malloc error.\n", __func__); - return; - } - if (init_pcie_bridge_from_spi(data, pcie_size)) { - free(data); - return; - } - - if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && - data[3] == 0xff) { - free(data); - printf("%s: skipped initialization\n", __func__); - return; - } - - writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ - writew(0x0000, &pciebrg->cp_ctrl); - writew(0x0000, &pciebrg->cp_addr); - - for (i = 0; i < pcie_size; i += 2) { - tmp = (data[i] << 8) | data[i + 1]; - writew(tmp, &pciebrg->cp_data); - } - - writew(0xa500, &pciebrg->ctrl_h8s); /* start */ - if (!is_sh7757_b0()) - writel(0x00000001, &pcie_setup->pbictl3); - - free(data); -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void set_mac_to_sh_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - eth_parse_enetaddr(mac_string, mac); - - if (!channel) - ether = ETHER0_MAC_BASE; - else - ether = ETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - eth_parse_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} - -int board_init(void) -{ - struct gether_control_regs *gether = GETHER_CONTROL_BASE; - - set_pmb_on_board_init(); - - /* enable RMII's MDIO (disable GRMII's MDIO) */ - writel(0x00030000, &gether->gbecont); - - init_gctrl(); - init_usb_phy(); - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - printf(" Physical address\n"); - printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n", - SH7757LCR_SDRAM_PHYS_TOP, - SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1); - printf(" 0x%08x - 0x%08x : No Access Area\n", - SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE, - SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1); - printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n", - SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2, - SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 + - SH7757LCR_SDRAM_DVC_SIZE - 1); - printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n", - SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET, - SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff); - - return 0; -} - -int board_mmc_init(bd_t *bis) -{ - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)], - SH7757LCR_ETHERNET_MAC_SIZE); - mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc error.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Fast Ethernet */ - for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - setenv("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - setenv(env_string, mac_string); - } - - set_mac_to_sh_eth_register(i, mac_string); - } - - /* Gigabit Ethernet */ - for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf); - sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH); - setenv(env_string, mac_string); - - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -static void init_pcie(void) -{ - struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; - struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE; - - writel(0x00000ff2, &pcie_setup->ladmsk0); - writel(0x00000001, &pcie_setup->barmap); - writel(0xffcaa000, &pcie_setup->lad0); - writel(0x00030000, &pcie_sysbus->endictl0); - writel(0x00000003, &pcie_sysbus->endictl1); - writel(0x00000004, &pcie_setup->pbictl2); -} - -static void finish_spiboot(void) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - /* - * SH7757 B0 does not use LBSC. - * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0. - * This setting is not cleared by manual reset, So we have to set it - * to 0. - */ - writel(0x00000000, &gctrl->spibootcan); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - init_pcie_bridge(); - init_pcie(); - finish_spiboot(); - - return 0; -} - -int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - unsigned long graofst; - - writel(0xfedcba98, &gctrl->wprotect); - graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; - writel(graofst | 0xa0000f00, &gctrl->gracr3); - - return 0; -} - -U_BOOT_CMD( - sh_g200, 1, 1, do_sh_g200, - "enable sh-g200", - "enable SH-G200 bus (disable PCIe-G200)" -); - -int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 5) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc error.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < 4; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i < 2) - printf(" ETHERC ch%d = %s\n", i, mac_string); - else - printf("GETHERC ch%d = %s\n", i-2, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s\t%s\t%s", - argv[1], argv[2], argv[3], argv[4]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, - SH7757LCR_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase error.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 5, 1, do_write_mac, - "write MAC address for ETHERC/GETHERC", - "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" -); diff --git a/qemu/roms/u-boot/board/renesas/sh7757lcr/spi-boot.c b/qemu/roms/u-boot/board/renesas/sh7757lcr/spi-boot.c deleted file mode 100644 index 71dcf5d44..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7757lcr/spi-boot.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License. See the file "COPYING.LIB" in the main - * directory of this archive for more details. - */ - -#include <common.h> - -#define CONFIG_RAM_BOOT_PHYS 0x4ef80000 -#if defined(CONFIG_SH7757_OFFSET_SPI) -#define CONFIG_SPI_ADDR 0x00010000 -#else -#define CONFIG_SPI_ADDR 0x00000000 -#endif -#define CONFIG_SPI_LENGTH 0x00030000 -#define CONFIG_RAM_BOOT 0x8ef80000 - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SSS 0x01 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - spi_write(0xfe, CR1); - - spi_write(0, SPIDMCOR); - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(M25_READ, TBR); - spi_write((addr >> 16) & 0xFF, TBR); - spi_write((addr >> 8) & 0xFF, TBR); - spi_write(addr & 0xFF, TBR); - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; -} - -void __uses_spiboot2 spiboot_main(void) -{ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, - CONFIG_SPI_LENGTH); - - _start(); -} diff --git a/qemu/roms/u-boot/board/renesas/sh7757lcr/u-boot.lds b/qemu/roms/u-boot/board/renesas/sh7757lcr/u-boot.lds deleted file mode 100644 index 4027fe3af..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7757lcr/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2011 - * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh4/start.o (.text)) - *(.spiboot1.text) - *(.spiboot2.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss (NOLOAD) : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/qemu/roms/u-boot/board/renesas/sh7763rdp/Makefile b/qemu/roms/u-boot/board/renesas/sh7763rdp/Makefile deleted file mode 100644 index cbf38bbc1..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7763rdp/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -# Copyright (C) 2007 Kenati Technologies, Inc. -# -# board/sh7763rdp/Makefile -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := sh7763rdp.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/sh7763rdp/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/sh7763rdp/lowlevel_init.S deleted file mode 100644 index e45fbbe9c..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7763rdp/lowlevel_init.S +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/lowlevel_init.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ - - write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ - - write32 WDTBST_A, WDTBST_D /* - * 0xFFCC0008 - * Watchdog Base Stop Time Register - */ - - write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ - /* Instruction Cache Invalidate */ - - write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ - /* TI == TLB Invalidate bit */ - - write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ - - write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ - - write32 RAMCR_A, RAMCR_D - - mov.l MMSELR_A, r1 - mov.l MMSELR_D, r0 - synco - mov.l r0, @r1 - - mov.l @r1, r2 /* execute two reads after setting MMSELR */ - mov.l @r1, r2 - synco - - /* issue memory read */ - mov.l DDRSD_START_A, r1 /* memory address to read*/ - mov.l @r1, r0 - synco - - write32 MIM8_A, MIM8_D - - write32 MIMC_A, MIMC_D1 - - write32 STRC_A, STRC_D - - write32 SDR4_A, SDR4_D - - write32 MIMC_A, MIMC_D2 - - nop - nop - nop - - write32 SCR4_A, SCR4_D3 - - write32 SCR4_A, SCR4_D2 - - write32 SDMR02000_A, SDMR02000_D - - write32 SDMR00B08_A, SDMR00B08_D - - write32 SCR4_A, SCR4_D2 - - write32 SCR4_A, SCR4_D4 - - nop - nop - nop - nop - - write32 SCR4_A, SCR4_D4 - - nop - nop - nop - nop - - write32 SDMR00308_A, SDMR00308_D - - write32 MIMC_A, MIMC_D3 - - mov.l SCR4_A, r1 - mov.l SCR4_D1, r0 - mov.l DELAY60_D, r3 - -delay_loop_60: - mov.l r0, @r1 - dt r3 - bf delay_loop_60 - nop - - write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ - -bsc_init: - write32 BCR_A, BCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS1BCR_A, CS1BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5BCR_A, CS5BCR_D - - write32 CS6BCR_A, CS6BCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS1WCR_A, CS1WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5WCR_A, CS5WCR_D - - write32 CS6WCR_A, CS6WCR_D - - write32 CS5PCR_A, CS5PCR_D - - write32 CS6PCR_A, CS6PCR_D - - mov.l DELAY200_D, r3 - -delay_loop_200: - dt r3 - bf delay_loop_200 - nop - - write16 PSEL0_A, PSEL0_D - - write16 PSEL1_A, PSEL1_D - - write32 ICR0_A, ICR0_D - - stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - nop - - .align 2 - -DELAY60_D: .long 60 -DELAY200_D: .long 17800 - -CCR_A: .long 0xFF00001C -MMUCR_A: .long 0xFF000010 -RAMCR_A: .long 0xFF000074 - -/* Low power mode control */ -MSTPCR0_A: .long 0xFFC80030 -MSTPCR1_A: .long 0xFFC80038 - -/* RWBT */ -WDTST_A: .long 0xFFCC0000 -WDTCSR_A: .long 0xFFCC0004 -WDTBST_A: .long 0xFFCC0008 - -/* BSC */ -MMSELR_A: .long 0xFE600020 -BCR_A: .long 0xFF801000 -CS0BCR_A: .long 0xFF802000 -CS1BCR_A: .long 0xFF802010 -CS2BCR_A: .long 0xFF802020 -CS4BCR_A: .long 0xFF802040 -CS5BCR_A: .long 0xFF802050 -CS6BCR_A: .long 0xFF802060 -CS0WCR_A: .long 0xFF802008 -CS1WCR_A: .long 0xFF802018 -CS2WCR_A: .long 0xFF802028 -CS4WCR_A: .long 0xFF802048 -CS5WCR_A: .long 0xFF802058 -CS6WCR_A: .long 0xFF802068 -CS5PCR_A: .long 0xFF802070 -CS6PCR_A: .long 0xFF802080 -DDRSD_START_A: .long 0xAC000000 - -/* INTC */ -ICR0_A: .long 0xFFD00000 - -/* DDR I/F */ -MIM8_A: .long 0xFE800008 -MIMC_A: .long 0xFE80000C -SCR4_A: .long 0xFE800014 -STRC_A: .long 0xFE80001C -SDR4_A: .long 0xFE800034 -SDMR00308_A: .long 0xFE900308 -SDMR00B08_A: .long 0xFE900B08 -SDMR02000_A: .long 0xFE902000 - -/* GPIO */ -PSEL0_A: .long 0xFFEF0070 -PSEL1_A: .long 0xFFEF0072 - -CCR_CACHE_ICI_D:.long 0x00000800 -CCR_CACHE_D_2: .long 0x00000103 -MMU_CONTROL_TI_D:.long 0x00000004 -RAMCR_D: .long 0x00000200 -MSTPCR0_D: .long 0x00000000 -MSTPCR1_D: .long 0x00000000 - -MMSELR_D: .long 0xa5a50000 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777670 -CS4BCR_D: .long 0x77777670 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777670 -CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x7777770F -CS6WCR_D: .long 0x7777770F -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 -ICR0_D: .long 0x00E00000 -MIM8_D: .long 0x00000000 -MIMC_D1: .long 0x01d10008 -MIMC_D2: .long 0x01d10009 -MIMC_D3: .long 0x01d10209 -SCR4_D1: .long 0x00000001 -SCR4_D2: .long 0x00000002 -SCR4_D3: .long 0x00000003 -SCR4_D4: .long 0x00000004 -STRC_D: .long 0x000f3980 -SDR4_D: .long 0x00000300 -SDMR00308_D: .long 0x00000000 -SDMR00B08_D: .long 0x00000000 -SDMR02000_D: .long 0x00000000 -PSEL0_D: .word 0x00000001 -PSEL1_D: .word 0x00000244 -SR_MASK_D: .long 0xEFFFFF0F -WDTST_D: .long 0x5A000FFF -WDTCSR_D: .long 0xA5000000 -WDTBST_D: .long 0x55000000 diff --git a/qemu/roms/u-boot/board/renesas/sh7763rdp/sh7763rdp.c b/qemu/roms/u-boot/board/renesas/sh7763rdp/sh7763rdp.c deleted file mode 100644 index 9658a5e44..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7763rdp/sh7763rdp.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/sh7763rdp.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CPU_CMDREG 0xB1000006 -#define PDCR 0xffef0006 -#define PECR 0xffef0008 -#define PFCR 0xffef000a -#define PGCR 0xffef000c -#define PHCR 0xffef000e -#define PJCR 0xffef0012 -#define PKCR 0xffef0014 -#define PLCR 0xffef0016 -#define PMCR 0xffef0018 -#define PSEL1 0xffef0072 -#define PSEL2 0xffef0074 -#define PSEL3 0xffef0076 - -int checkboard(void) -{ - puts("BOARD: Renesas SH7763 RDP\n"); - return 0; -} - -int board_init(void) -{ - vu_short dat; - - /* Enable mode */ - writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); - - /* GPIO Setting (eth1) */ - dat = inw(PSEL1); - writew(((dat & ~0xff00) | 0x2400), PSEL1); - writew(0, PFCR); - writew(0, PGCR); - writew(0, PHCR); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} diff --git a/qemu/roms/u-boot/board/renesas/sh7785lcr/Makefile b/qemu/roms/u-boot/board/renesas/sh7785lcr/Makefile deleted file mode 100644 index e8cfb053c..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7785lcr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/renesas/sh7785lcr/README.sh7785lcr b/qemu/roms/u-boot/board/renesas/sh7785lcr/README.sh7785lcr deleted file mode 100644 index 56455fc16..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7785lcr/README.sh7785lcr +++ /dev/null @@ -1,123 +0,0 @@ -======================================== -Renesas Technology R0P7785LC0011RL board -======================================== - -This board specification: -========================= - -The R0P7785LC0011RL(board config name:sh7785lcr) has the following device: - - - SH7785 (SH-4A) - - DDR2-SDRAM 512MB - - NOR Flash 64MB - - 2D Graphic controller - - SATA controller - - Ethernet controller - - USB host/peripheral controller - - SD controller - - I2C controller - - RTC - -This board has 2 physical memory maps. It can be changed with DIP switch(S2-5). - - phys address | S2-5 = OFF | S2-5 = ON - -------------------------------+---------------+--------------- - 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash - 0x04000000 - 0x05ffffff(CS1) | PLD | PLD - 0x06000000 - 0x07ffffff(CS1) | reserved | I2C - 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM - 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM - 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 - 0x14000000 - 0x17ffffff(CS5) | I2C | USB - 0x18000000 - 0x1bffffff(CS6) | reserved | SD - 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) - - -configuration for This board: -============================= - -You can choose configuration as follows: - - - make sh7785lcr_config - - make sh7785lcr_32bit_config - -When you use "make sh7785lcr_config", there is build U-Boot for 29-bit -address mode. This mode can use 128MB DDR-SDRAM. - -When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit -extended address mode. This mode can use 384MB DDR-SDRAM. And if you run -"pmb" command, this mode can use 512MB DDR-SDRAM. - - * 32-bit extended address mode PMB mapping * - a) on start-up - virt | phys | size | device - -------------+---------------+---------------+--------------- - 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable) - 0xa0000000 | 0x00000000 | 64MB | NOR Flash - 0xa4000000 | 0x04000000 | 16MB | PLD - 0xa6000000 | 0x08000000 | 16MB | USB - 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable) - - b) after "pmb" command - virt | phys | size | device - -------------+---------------+---------------+--------------- - 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable) - 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable) - - -This board specific command: -============================ - -This board has the following its specific command: - - - hwtest - - printmac - - setmac - - pmb (sh7785lcr_32bit_config only) - - -1. hwtest - -This is self-check command. This command has the following options: - - - all : test all hardware - - pld : output PLD version - - led : turn on LEDs - - dipsw : test DIP switch - - sm107 : output SM107 version - - net : check RTL8110 ID - - sata : check SiI3512 ID - - net : output PCI slot device ID - -i.e) -=> hwtest led -turn on LEDs 3, 5, 7, 9 -turn on LEDs 4, 6, 8, 10 - -=> hwtest net -Ethernet OK - - -2. printmac - -This command outputs MAC address of this board. - -i.e) -=> printmac -MAC = 00:00:87:**:**:** - - -3. setmac - -This command writes MAC address of this board. - -i.e) -=> setmac 00:00:87:**:**:** - - -4. pmb - -This command change PMB for DDR-SDRAM all mapping. However you cannot use -NOR Flash and USB Host on U-Boot when you run this command. -i.e) -=> pmb diff --git a/qemu/roms/u-boot/board/renesas/sh7785lcr/lowlevel_init.S b/qemu/roms/u-boot/board/renesas/sh7785lcr/lowlevel_init.S deleted file mode 100644 index 8b729ac39..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7785lcr/lowlevel_init.S +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <config.h> -#include <version.h> -#include <asm/processor.h> -#include <asm/macro.h> - -#include <asm/processor.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - wait_timer WAIT_200US - wait_timer WAIT_200US - - /*------- LBSC -------*/ - write32 MMSELR_A, MMSELR_D - - /*------- DBSC2 -------*/ - write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D - write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D - write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D - write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1 - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2 - wait_timer WAIT_200US - - write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H - wait_timer WAIT_200US - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1 - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2 - wait_timer WAIT_200US - - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - - write32 DBSC2_DBEN_A, DBSC2_DBEN_D - write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D - write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D - write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D - wait_timer WAIT_200US - - /*------- GPIO -------*/ - write16 PACR_A, PXCR_D - write16 PBCR_A, PXCR_D - write16 PCCR_A, PXCR_D - write16 PDCR_A, PXCR_D - write16 PECR_A, PXCR_D - write16 PFCR_A, PXCR_D - write16 PGCR_A, PXCR_D - write16 PHCR_A, PHCR_D - write16 PJCR_A, PJCR_D - write16 PKCR_A, PKCR_D - write16 PLCR_A, PXCR_D - write16 PMCR_A, PMCR_D - write16 PNCR_A, PNCR_D - write16 PPCR_A, PXCR_D - write16 PQCR_A, PXCR_D - write16 PRCR_A, PXCR_D - - write8 PEPUPR_A, PEPUPR_D - write8 PHPUPR_A, PHPUPR_D - write8 PJPUPR_A, PJPUPR_D - write8 PKPUPR_A, PKPUPR_D - write8 PLPUPR_A, PLPUPR_D - write8 PMPUPR_A, PMPUPR_D - write8 PNPUPR_A, PNPUPR_D - write16 PPUPR1_A, PPUPR1_D - write16 PPUPR2_A, PPUPR2_D - write16 P1MSELR_A, P1MSELR_D - write16 P2MSELR_A, P2MSELR_D - - /*------- LBSC -------*/ - write32 BCR_A, BCR_D - write32 CS0BCR_A, CS0BCR_D - write32 CS0WCR_A, CS0WCR_D - write32 CS1BCR_A, CS1BCR_D - write32 CS1WCR_A, CS1WCR_D - write32 CS4BCR_A, CS4BCR_D - write32 CS4WCR_A, CS4WCR_D - - mov.l PASCR_A, r0 - mov.l @r0, r2 - mov.l PASCR_32BIT_MODE, r1 - tst r1, r2 - bt lbsc_29bit - - write32 CS2BCR_A, CS_USB_BCR_D - write32 CS2WCR_A, CS_USB_WCR_D - write32 CS3BCR_A, CS_SD_BCR_D - write32 CS3WCR_A, CS_SD_WCR_D - write32 CS5BCR_A, CS_I2C_BCR_D - write32 CS5WCR_A, CS_I2C_WCR_D - write32 CS6BCR_A, CS0BCR_D - write32 CS6WCR_A, CS0WCR_D - bra lbsc_end - nop - -lbsc_29bit: - write32 CS5BCR_A, CS_USB_BCR_D - write32 CS5WCR_A, CS_USB_WCR_D - write32 CS6BCR_A, CS_SD_BCR_D - write32 CS6WCR_A, CS_SD_WCR_D - -lbsc_end: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 64M 0 0 - * 1 0xa4000000 0x04000000 1 16M 0 0 - * 2 0xa6000000 0x08000000 1 16M 0 0 - * 9 0x88000000 0x48000000 1 128M 1 1 - * 10 0x90000000 0x50000000 1 128M 1 1 - * 11 0x98000000 0x58000000 1 128M 1 1 - * 13 0xa8000000 0x48000000 1 128M 0 0 - * 14 0xb0000000 0x50000000 1 128M 0 0 - * 15 0xb8000000 0x58000000 1 128M 0 0 - */ - write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D - write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D - write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D - write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D - write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D - write32 PMB_DATA_USB_A, PMB_DATA_USB_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D - write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D - write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D - write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D - write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D - write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D - write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif - - write32 CCR_A, CCR_D - - rts - nop - - .align 4 - -/*------- GPIO -------*/ -/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ -PXCR_D: .word 0x0000 - -PHCR_D: .word 0x00c0 -PJCR_D: .word 0xc3fc -PKCR_D: .word 0x03ff -PMCR_D: .word 0xffff -PNCR_D: .word 0xf0c3 - -PEPUPR_D: .long 0xff -PHPUPR_D: .long 0x00 -PJPUPR_D: .long 0x00 -PKPUPR_D: .long 0x00 -PLPUPR_D: .long 0x00 -PMPUPR_D: .long 0xfc -PNPUPR_D: .long 0x00 -PPUPR1_D: .word 0xffbf -PPUPR2_D: .word 0xff00 -P1MSELR_D: .word 0x3780 -P2MSELR_D: .word 0x0000 - -#define GPIO_BASE 0xffe70000 -PACR_A: .long GPIO_BASE + 0x00 -PBCR_A: .long GPIO_BASE + 0x02 -PCCR_A: .long GPIO_BASE + 0x04 -PDCR_A: .long GPIO_BASE + 0x06 -PECR_A: .long GPIO_BASE + 0x08 -PFCR_A: .long GPIO_BASE + 0x0a -PGCR_A: .long GPIO_BASE + 0x0c -PHCR_A: .long GPIO_BASE + 0x0e -PJCR_A: .long GPIO_BASE + 0x10 -PKCR_A: .long GPIO_BASE + 0x12 -PLCR_A: .long GPIO_BASE + 0x14 -PMCR_A: .long GPIO_BASE + 0x16 -PNCR_A: .long GPIO_BASE + 0x18 -PPCR_A: .long GPIO_BASE + 0x1a -PQCR_A: .long GPIO_BASE + 0x1c -PRCR_A: .long GPIO_BASE + 0x1e -PEPUPR_A: .long GPIO_BASE + 0x48 -PHPUPR_A: .long GPIO_BASE + 0x4e -PJPUPR_A: .long GPIO_BASE + 0x50 -PKPUPR_A: .long GPIO_BASE + 0x52 -PLPUPR_A: .long GPIO_BASE + 0x54 -PMPUPR_A: .long GPIO_BASE + 0x56 -PNPUPR_A: .long GPIO_BASE + 0x58 -PPUPR1_A: .long GPIO_BASE + 0x60 -PPUPR2_A: .long GPIO_BASE + 0x62 -P1MSELR_A: .long GPIO_BASE + 0x80 -P2MSELR_A: .long GPIO_BASE + 0x82 - -MMSELR_A: .long 0xfc400020 -#if defined(CONFIG_SH_32BIT) -MMSELR_D: .long 0xa5a50005 -#else -MMSELR_D: .long 0xa5a50002 -#endif - -/*------- DBSC2 -------*/ -#define DBSC2_BASE 0xfe800000 -DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c -DBSC2_DBEN_A: .long DBSC2_BASE + 0x10 -DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14 -DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20 -DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30 -DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34 -DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38 -DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40 -DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 -DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 -DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c -DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 -DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54 -DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 -DDR_DUMMY_ACCESS_A: .long 0x40000000 - -DBSC2_DBCONF_D: .long 0x00630002 -DBSC2_DBTR0_D: .long 0x050b1f04 -DBSC2_DBTR1_D: .long 0x00040204 -DBSC2_DBTR2_D: .long 0x02100308 -DBSC2_DBFREQ_D1: .long 0x00000000 -DBSC2_DBFREQ_D2: .long 0x00000100 -DBSC2_DBDICODTOCD_D:.long 0x000f0907 - -DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 -DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 -DBSC2_DBCMDCNT_D_REF: .long 0x00000004 - -DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000 -DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000 -DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006 -DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386 -DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952 -DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852 - -DBSC2_DBEN_D: .long 0x00000001 - -DBSC2_DBPDCNT0_D3: .long 0x00000080 -DBSC2_DBRFCNT1_D: .long 0x00000926 -DBSC2_DBRFCNT2_D: .long 0x00fe00fe -DBSC2_DBRFCNT0_D: .long 0x00010000 - -WAIT_200US: .long 33333 - -/*------- LBSC -------*/ -PASCR_A: .long 0xff000070 -PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */ - -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS0WCR_A: .long CS0WCR -CS1BCR_A: .long CS1BCR -CS1WCR_A: .long CS1WCR -CS2BCR_A: .long CS2BCR -CS2WCR_A: .long CS2WCR -CS3BCR_A: .long CS3BCR -CS3WCR_A: .long CS3WCR -CS4BCR_A: .long CS4BCR -CS4WCR_A: .long CS4WCR -CS5BCR_A: .long CS5BCR -CS5WCR_A: .long CS5WCR -CS6BCR_A: .long CS6BCR -CS6WCR_A: .long CS6WCR - -BCR_D: .long 0x80000003 -CS0BCR_D: .long 0x22222340 -CS0WCR_D: .long 0x00111118 -CS1BCR_D: .long 0x11111100 -CS1WCR_D: .long 0x33333303 -CS4BCR_D: .long 0x11111300 -CS4WCR_D: .long 0x00101012 - -/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */ -CS_USB_BCR_D: .long 0x11111200 -CS_USB_WCR_D: .long 0x00020005 - -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ -CS_SD_BCR_D: .long 0x00000300 -CS_SD_WCR_D: .long 0x00030108 - -/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */ -CS_I2C_BCR_D: .long 0x11111100 -CS_I2C_WCR_D: .long 0x00000003 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9) -PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10) -PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13) -PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14) -PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15) - -PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4) -PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90) -PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0) -PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8) - -PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0) -PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1) -PMB_DATA_USB_A: .long PMB_DATA_BASE(2) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9) -PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10) -PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13) -PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14) -PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1) -PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1) -PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) -PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1) -PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1) - -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 /* check booting mode */ -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090b diff --git a/qemu/roms/u-boot/board/renesas/sh7785lcr/rtl8169.h b/qemu/roms/u-boot/board/renesas/sh7785lcr/rtl8169.h deleted file mode 100644 index 888de4846..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7785lcr/rtl8169.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr)) -#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr)) -#define PCI_PAR PCIREG_32(0xfe0401c0) -#define PCI_PDR PCIREG_32(0xfe040220) -#define PCI_CR PCIREG_32(0xfe040100) -#define PCI_CONF1 PCIREG_32(0xfe040004) - -#define HIGH 1 -#define LOW 0 - -#define PCI_PROG 0x80 -#define PCI_EEP_ADDRESS (unsigned short)0x0007 -#define PCI_MAC_ADDRESS_SIZE 3 - -#define TIME1 100 -#define TIME2 20000 - -#define BIT_DUMMY 0 -#define MAC_EEP_READ 1 -#define MAC_EEP_WRITE 2 -#define MAC_EEP_ERACE 3 -#define MAC_EEP_EWEN 4 -#define MAC_EEP_EWDS 5 - -/* RTL8169 */ -const unsigned short EEPROM_W_Data_8169_A[] = { - 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b, - 0x4020, 0xa101 -}; -const unsigned short EEPROM_W_Data_8169_B[] = { - 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 -}; diff --git a/qemu/roms/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c b/qemu/roms/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c deleted file mode 100644 index c91ebdc54..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include "rtl8169.h" - -static unsigned char *PCI_MEMR; - -static void mac_delay(unsigned int cnt) -{ - udelay(cnt); -} - -static void mac_pci_setup(void) -{ - unsigned long pci_data; - - PCI_PAR = 0x00000010; - PCI_PDR = 0x00001000; - PCI_PAR = 0x00000004; - pci_data = PCI_PDR; - PCI_PDR = pci_data | 0x00000007; - PCI_PAR = 0x00000010; - - PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0); -} - -static void EECS(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x08; - else - *PCI_MEMR = data & 0xf7; -} - -static void EECLK(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x04; - else - *PCI_MEMR = data & 0xfb; -} - -static void EEDI(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x02; - else - *PCI_MEMR = data & 0xfd; -} - -static inline void sh7785lcr_bitset(unsigned short bit) -{ - if (bit) - EEDI(HIGH); - else - EEDI(LOW); - - EECLK(LOW); - mac_delay(TIME1); - EECLK(HIGH); - mac_delay(TIME1); - EEDI(LOW); -} - -static inline unsigned char sh7785lcr_bitget(void) -{ - unsigned char bit; - - EECLK(LOW); - mac_delay(TIME1); - bit = *PCI_MEMR & 0x01; - EECLK(HIGH); - mac_delay(TIME1); - - return bit; -} - -static inline void sh7785lcr_setcmd(unsigned char command) -{ - sh7785lcr_bitset(BIT_DUMMY); - switch (command) { - case MAC_EEP_READ: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - break; - case MAC_EEP_WRITE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(1); - break; - case MAC_EEP_ERACE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - break; - case MAC_EEP_EWEN: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - case MAC_EEP_EWDS: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - default: - break; - } -} - -static inline unsigned short sh7785lcr_getdt(void) -{ - unsigned short data = 0; - int i; - - sh7785lcr_bitget(); /* DUMMY */ - for (i = 0 ; i < 16 ; i++) { - data <<= 1; - data |= sh7785lcr_bitget(); - } - return data; -} - -static inline void sh7785lcr_setadd(unsigned short address) -{ - sh7785lcr_bitset(address & 0x0020); /* A5 */ - sh7785lcr_bitset(address & 0x0010); /* A4 */ - sh7785lcr_bitset(address & 0x0008); /* A3 */ - sh7785lcr_bitset(address & 0x0004); /* A2 */ - sh7785lcr_bitset(address & 0x0002); /* A1 */ - sh7785lcr_bitset(address & 0x0001); /* A0 */ -} - -static inline void sh7785lcr_setdata(unsigned short data) -{ - sh7785lcr_bitset(data & 0x8000); - sh7785lcr_bitset(data & 0x4000); - sh7785lcr_bitset(data & 0x2000); - sh7785lcr_bitset(data & 0x1000); - sh7785lcr_bitset(data & 0x0800); - sh7785lcr_bitset(data & 0x0400); - sh7785lcr_bitset(data & 0x0200); - sh7785lcr_bitset(data & 0x0100); - sh7785lcr_bitset(data & 0x0080); - sh7785lcr_bitset(data & 0x0040); - sh7785lcr_bitset(data & 0x0020); - sh7785lcr_bitset(data & 0x0010); - sh7785lcr_bitset(data & 0x0008); - sh7785lcr_bitset(data & 0x0004); - sh7785lcr_bitset(data & 0x0002); - sh7785lcr_bitset(data & 0x0001); -} - -static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address, - unsigned int count) -{ - unsigned int i; - - for (i = 0; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_WRITE); - sh7785lcr_setadd(address++); - sh7785lcr_setdata(*(data + i)); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME2); - } -} - -static void sh7785lcr_macerase(void) -{ - unsigned int i; - unsigned short pci_address = 7; - - for (i = 0; i < 3; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_ERACE); - sh7785lcr_setadd(pci_address++); - mac_delay(TIME1); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } - - mac_delay(TIME2); - - printf("\n\nErace End\n"); - for (i = 0; i < 10; i++) - mac_delay(TIME2); -} - -static void sh7785lcr_macwrite(unsigned short *data) -{ - sh7785lcr_macerase(); - - sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7); - sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); - sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54); -} - -void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count) -{ - unsigned int i; - unsigned short wk; - - for (i = 0 ; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_READ); - sh7785lcr_setadd(address++); - wk = sh7785lcr_getdt(); - - *buf++ = (unsigned char)(wk & 0xff); - *buf++ = (unsigned char)((wk >> 8) & 0xff); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } -} - -static void sh7785lcr_macadrd(unsigned char *buf) -{ - *PCI_MEMR = PCI_PROG; - - sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); -} - -static void sh7785lcr_eepewen(void) -{ - *PCI_MEMR = PCI_PROG; - mac_delay(TIME1); - EECS(LOW); - EECLK(LOW); - EEDI(LOW); - EECS(HIGH); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_EWEN); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME1); -} - -void mac_write(unsigned short *data) -{ - mac_pci_setup(); - sh7785lcr_eepewen(); - sh7785lcr_macwrite(data); -} - -void mac_read(void) -{ - unsigned char data[6]; - - mac_pci_setup(); - sh7785lcr_macadrd(data); - printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n", - data[0], data[1], data[2], data[3], data[4], data[5]); -} - -int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - unsigned char mac[6]; - char *s, *e; - - if (argc != 2) - return cmd_usage(cmdtp); - - s = argv[1]; - - for (i = 0; i < 6; i++) { - mac[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - mac_write((unsigned short *)mac); - - return 0; -} - -U_BOOT_CMD( - setmac, 2, 1, do_set_mac, - "write MAC address for RTL8110SCL", - "\n" - "setmac <mac address> - write MAC address for RTL8110SCL" -); - -int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 1) - return cmd_usage(cmdtp); - - mac_read(); - - return 0; -} - -U_BOOT_CMD( - printmac, 1, 1, do_print_mac, - "print MAC address for RTL8110", - "\n" - " - print MAC address for RTL8110" -); diff --git a/qemu/roms/u-boot/board/renesas/sh7785lcr/selfcheck.c b/qemu/roms/u-boot/board/renesas/sh7785lcr/selfcheck.c deleted file mode 100644 index d52075070..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7785lcr/selfcheck.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/pci.h> - -#if defined(CONFIG_CPU_32BIT) -#define NOCACHE_OFFSET 0x00000000 -#else -#define NOCACHE_OFFSET 0xa0000000 -#endif -#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET) -#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET) -#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET) - -#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) - -static void test_pld(void) -{ - printf("PLD version = %04x\n", readb(PLD_VERSR)); -} - -static void test_sm107(void) -{ - printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID)); -} - -static void test_led(void) -{ - printf("turn on LEDs 3, 5, 7, 9\n"); - writeb(0x55, PLD_LEDCR); - mdelay(2000); - printf("turn on LEDs 4, 6, 8, 10\n"); - writeb(0xaa, PLD_LEDCR); - mdelay(2000); - writeb(0x00, PLD_LEDCR); -} - -static void test_dipsw(void) -{ - printf("Please DIPSW set = B'0101\n"); - while (readb(PLD_SWSR) != 0x05) { - if (ctrlc()) - return; - } - printf("Please DIPSW set = B'1010\n"); - while (readb(PLD_SWSR) != 0x0A) { - if (ctrlc()) - return; - } - printf("DIPSW OK\n"); -} - -static void test_net(void) -{ - unsigned long data; - - writel(0x80000000, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x816910ec) - printf("Ethernet OK\n"); - else - printf("Ethernet NG, data = %08x\n", (unsigned int)data); -} - -static void test_sata(void) -{ - unsigned long data; - - writel(0x80000800, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x35121095) - printf("SATA OK\n"); - else - printf("SATA NG, data = %08x\n", (unsigned int)data); -} - -static void test_pci(void) -{ - writel(0x80001800, 0xfe0401c0); - printf("PCI CN1 ID = %08x\n", readl(0xfe040220)); - - writel(0x80001000, 0xfe0401c0); - printf("PCI CN2 ID = %08x\n", readl(0xfe040220)); -} - -int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *cmd; - - if (argc != 2) - return cmd_usage(cmdtp); - - cmd = argv[1]; - switch (cmd[0]) { - case 'a': /* all */ - test_pld(); - test_led(); - test_dipsw(); - test_sm107(); - test_net(); - test_sata(); - test_pci(); - break; - case 'p': /* pld or pci */ - if (cmd[1] == 'l') - test_pld(); - else - test_pci(); - break; - case 'l': /* led */ - test_led(); - break; - case 'd': /* dipsw */ - test_dipsw(); - break; - case 's': /* sm107 or sata */ - if (cmd[1] == 'm') - test_sm107(); - else - test_sata(); - break; - case 'n': /* net */ - test_net(); - break; - default: - return cmd_usage(cmdtp); - } - - return 0; -} - -U_BOOT_CMD( - hwtest, 2, 1, do_hw_test, - "hardware test for R0P7785LC0011RL board", - "\n" - "hwtest all - test all hardware\n" - "hwtest pld - output PLD version\n" - "hwtest led - turn on LEDs\n" - "hwtest dipsw - test DIP switch\n" - "hwtest sm107 - output SM107 version\n" - "hwtest net - check RTL8110 ID\n" - "hwtest sata - check SiI3512 ID\n" - "hwtest pci - output PCI slot device ID" -); diff --git a/qemu/roms/u-boot/board/renesas/sh7785lcr/sh7785lcr.c b/qemu/roms/u-boot/board/renesas/sh7785lcr/sh7785lcr.c deleted file mode 100644 index 622e60261..000000000 --- a/qemu/roms/u-boot/board/renesas/sh7785lcr/sh7785lcr.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/pci.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -#if defined(CONFIG_SH_32BIT) -int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - /* clear ITLB */ - writel(0x00000004, 0xff000010); - - /* delete PMB for peripheral */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - writel(0, PMB_ADDR_BASE(1)); - writel(0, PMB_DATA_BASE(1)); - writel(0, PMB_ADDR_BASE(2)); - writel(0, PMB_DATA_BASE(2)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8)); - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12)); - - return 0; -} - -U_BOOT_CMD( - pmb, 1, 1, do_pmb, - "pmb - PMB setting\n", - "\n" - " - PMB setting for all SDRAM mapping" -); -#endif |