diff options
Diffstat (limited to 'qemu/roms/u-boot/board/matrix_vision/mvblm7')
9 files changed, 577 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/.gitignore b/qemu/roms/u-boot/board/matrix_vision/mvblm7/.gitignore new file mode 100644 index 000000000..469f1bc4c --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/.gitignore @@ -0,0 +1 @@ +bootscript.img diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/Makefile b/qemu/roms/u-boot/board/matrix_vision/mvblm7/Makefile new file mode 100644 index 000000000..9ed2837a7 --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/Makefile @@ -0,0 +1,18 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mvblm7.o pci.o fpga.o + +extra-y := bootscript.img + +quiet_cmd_mkimage = MKIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script + +$(obj)/bootscript.img: $(src)/bootscript + $(call cmd,mkimage) diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/README.mvblm7 b/qemu/roms/u-boot/board/matrix_vision/mvblm7/README.mvblm7 new file mode 100644 index 000000000..a0686f7fa --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/README.mvblm7 @@ -0,0 +1,84 @@ +Matrix Vision mvBlueLYNX-M7 (mvBL-M7) +------------------------------------- + +1. Board Description + + The mvBL-M7 is a 120x120mm single board computing platform + with strong focus on stereo image processing applications. + + Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) + on any port (requires add-on board). + +2 System Components + +2.1 CPU + Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. + 512MByte DDR-II memory @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 SD-Card slot connected to SPI. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2 PCI + A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. + +2.3 FPGA + Altera Cyclone-II EP2C20/35 with PCI DMA engines. + Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. + Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. + +2.3.1 I/O @ FPGA + 2x8 Outputs : Infineon High-Side Switches to Main Supply. + 2x8 Inputs : Programmable input threshold + trigger capabilities + 2 dedicated flash interfaces for illuminator boards. + Cross trigger for chaining several boards. + +2.4 I2C + Bus1: + MAX5381 DAC @ 0x60 for 1st digital input threshold. + LM75 @ 0x90 for temperature monitoring. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + 1st image sensor interface (slave addresses depend on sensor) + Bus2: + MAX5381 DAC @ 0x60 for 2nd digital input threshold. + 2nd image sensor interface (slave addresses depend on sensor) + +3 Flash layout. + + reset vector is 0xFFF00100, i.e. "HIGHBOOT". + + FF800000 environment + FF802000 redundant environment + FF804000 u-boot script image + FF806000 redundant u-boot script image + FF808000 device tree blob + FF80A000 redundant device tree blob + FF80C000 tbd. + FF80E000 tbd. + FF810000 kernel + FFC00000 root FS + FFF00000 u-boot + FFF80000 FPGA raw bit file + + mtd partitions are propagated to linux kernel via device tree blob. + +4 Booting + + On startup the bootscript @ FF804000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + 3. device tree blob - name is stored in "dtb_name" + Fallback files are the flash versions. diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/bootscript b/qemu/roms/u-boot/board/matrix_vision/mvblm7/bootscript new file mode 100644 index 000000000..dc385fde7 --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/bootscript @@ -0,0 +1,43 @@ +echo +echo "==== running autoscript ====" +echo +setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} +setenv ramkernel setenv kernel_boot \${loadaddr} +setenv flashkernel setenv kernel_boot \${mv_kernel_addr} +setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} +setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb +setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} +setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 +setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup +setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel +if test ${console} = yes; +then +setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 +else +setenv addcons setenv bootargs \${bootargs} console=tty0 +fi +setenv set_static_ip setenv ipaddr \${static_ipaddr} +setenv set_static_nm setenv netmask \${static_netmask} +setenv set_static_gw setenv gatewayip \${static_gateway} +setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} +setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs +if test ${autoscript_boot} != no; +then + if test ${netboot} = yes; + then + bootp + if test $? = 0; + then + echo "=== bootp succeeded -> netboot ===" + run set_ip + run getdtb rundtb bootfromnet ramparam addcons bootdtb + else + echo "=== netboot failed ===" + fi + fi + run set_static_ip set_static_nm set_static_gw set_ip + echo "=== bootfromflash ===" + run cpdtb rundtb bootfromflash +else + echo "=== boot stopped with autoscript_boot no ===" +fi diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.c b/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.c new file mode 100644 index 000000000..c0c5bedb2 --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.c @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ACEX1K.h> +#include <command.h> +#include "fpga.h" +#include "mvblm7.h" + +#ifdef FPGA_DEBUG +#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) +#else +#define fpga_debug(fmt, args...) +#endif + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + passive_serial, + Altera_EP2C20_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mvblm7_init_fpga(void) +{ + fpga_debug("Initialize FPGA interface\n"); + fpga_init(); + fpga_add(fpga_altera, &cyclone2); + fpga_config_fn(0, 1, 0); + udelay(60); + + return 1; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("SET config : %s\n", assert ? "low" : "high"); + if (assert) + dvo |= FPGA_CONFIG; + else + dvo &= ~FPGA_CONFIG; + + if (flush) + gpio->dat = dvo; + + return assert; +} + +int fpga_done_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + udelay(10); + fpga_debug("CONF_DONE check ... "); + if (gpio->dat & FPGA_CONF_DONE) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_status_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + fpga_debug("STATUS check ... "); + if (gpio->dat & FPGA_STATUS) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); + if (assert_clk) + dvo |= FPGA_CCLK; + else + dvo &= ~FPGA_CCLK; + + if (flush) + gpio->dat = dvo; + + return assert_clk; +} + +static inline int _write_fpga(u8 val, int dump) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int i; + u32 dvo = gpio->dat; + + if (dump) + fpga_debug(" %02x -> ", val); + for (i = 0; i < 8; i++) { + dvo &= ~FPGA_CCLK; + gpio->dat = dvo; + dvo &= ~FPGA_DIN; + if (dump) + fpga_debug("%d ", val&1); + if (val & 1) + dvo |= FPGA_DIN; + gpio->dat = dvo; + dvo |= FPGA_CCLK; + gpio->dat = dvo; + val >>= 1; + } + if (dump) + fpga_debug("\n"); + + return 0; +} + +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i], 0); + fpga_debug("\n"); + + return FPGA_SUCCESS; +} diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.h b/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.h new file mode 100644 index 000000000..b480c09b2 --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +extern int mvblm7_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.c b/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.c new file mode 100644 index 000000000..f3c16a3e9 --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ioports.h> +#include <mpc83xx.h> +#include <asm/mpc8349_pci.h> +#include <pci.h> +#include <spi.h> +#include <asm/mmu.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + +#include "../common/mv_common.h" +#include "mvblm7.h" + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + char *s = getenv("ddr_size"); + + msize = CONFIG_SYS_DDR_SIZE; + if (s) { + u32 env_ddr_size = simple_strtoul(s, NULL, 10); + if (env_ddr_size == 512) + msize = 512; + } + + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & + LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + + asm("sync;isync"); + udelay(600); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + asm("sync;isync"); + udelay(500); + + return msize; +} + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram(); + + /* return total bus RAM size(bytes) */ + return msize * 1024 * 1024; +} + +int misc_init_r(void) +{ + char *s = getenv("reset_env"); + + if (s) { + mv_reset_environment(); + } + + return 0; +} + +int checkboard(void) +{ + puts("Board: Matrix Vision mvBlueLYNX-M7\n"); + + return 0; +} + +#ifdef CONFIG_HARD_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + + iopd->dat &= ~MVBLM7_MMC_CS; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + + iopd->dat |= ~MVBLM7_MMC_CS; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} + +#endif diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.h b/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.h new file mode 100644 index 000000000..de9fec7fb --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.h @@ -0,0 +1,20 @@ +#ifndef __MVBC_H__ +#define __MVBC_H__ + +#define MV_GPIO + +#define FPGA_CONFIG 0x80000000 +#define FPGA_CCLK 0x40000000 +#define FPGA_DIN 0x20000000 +#define FPGA_STATUS 0x10000000 +#define FPGA_CONF_DONE 0x08000000 + +#define WD_WDI 0x00400000 +#define WD_TS 0x00200000 +#define MAN_RST 0x00100000 + +#define MV_GPIO_DAT (WD_TS) +#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) +#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) + +#endif diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/pci.c b/qemu/roms/u-boot/board/matrix_vision/mvblm7/pci.c new file mode 100644 index 000000000..f14837ad4 --- /dev/null +++ b/qemu/roms/u-boot/board/matrix_vision/mvblm7/pci.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#include <pci.h> +#include <mpc83xx.h> +#include <fpga.h> +#include "mvblm7.h" +#include "fpga.h" +#include "../common/mv_common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct pci_region pci_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + int i; + volatile immap_t *immr; + volatile pcictrl83xx_t *pci_ctrl; + volatile gpio83xx_t *gpio; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + struct pci_region *reg[] = { pci_regions }; + + immr = (immap_t *) CONFIG_SYS_IMMR; + clk = (clk83xx_t *) &immr->clk; + pci_ctrl = immr->pci_ctrl; + pci_law = immr->sysconf.pcilaw; + gpio = (volatile gpio83xx_t *)&immr->gpio[0]; + + gpio->dat = MV_GPIO_DAT; + gpio->odr = MV_GPIO_ODE; + gpio->dir = MV_GPIO_OUT; + + printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, + immr->sysconf.sicrl); + + mvblm7_init_fpga(); + mv_load_fpga(); + + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + + /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ + clk->occr = 0xc0000000; + + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + + for (i = 0; i < 1000; ++i) + udelay(1000); + + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + mpc83xx_pci_init(1, reg); +} |