3 files changed, 0 insertions, 80 deletions
diff --git a/qemu/roms/u-boot/board/avnet/fx12mm/Makefile b/qemu/roms/u-boot/board/avnet/fx12mm/Makefile
deleted file mode 100644
index 618b42f89..000000000
--- a/qemu/roms/u-boot/board/avnet/fx12mm/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2008
-# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
-# This work has been supported by: Qtechnology http://qtec.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= fx12mm.o
-
-include $(srctree)/board/xilinx/ppc405-generic/Makefile
diff --git a/qemu/roms/u-boot/board/avnet/fx12mm/fx12mm.c b/qemu/roms/u-boot/board/avnet/fx12mm/fx12mm.c
deleted file mode 100644
index 92e1cfb75..000000000
--- a/qemu/roms/u-boot/board/avnet/fx12mm/fx12mm.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2008
- *
- * Author: Xilinx Inc.
- *
- * Modified by:
- *  Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
-	char buf[64];
-	int i;
-	int l = getenv_f("serial#", buf, sizeof(buf));
-
-	if (l < 0) {
-		printf("Avnet Virtex4 FX12 with no serial #");
-	} else {
-		printf("Avnet Virtex4 FX12 Minimodul # ");
-		for (i = 0; i < l; ++i) {
-			if (buf[i] == ' ')
-				break;
-			putc(buf[i]);
-		}
-	}
-	putc('\n');
-	return 0;
-}
diff --git a/qemu/roms/u-boot/board/avnet/fx12mm/xparameters.h b/qemu/roms/u-boot/board/avnet/fx12mm/xparameters.h
deleted file mode 100644
index 94f682f8e..000000000
--- a/qemu/roms/u-boot/board/avnet/fx12mm/xparameters.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2008
- *
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * CAUTION: This file is based on the xparameters.h automatically
- * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
- */
-
-#ifndef __XPARAMETER_H__
-#define __XPARAMETER_H__
-
-/* RS232 */
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
-#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
-
-
-/* INT_C */
-#define XPAR_XPS_INTC_0_DEVICE_ID 0
-#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
-
-/* CPU core clock */
-#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
-#define XPAR_PLB_CLOCK_FREQ_HZ  100000000
-
-/* RAM */
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
-
-/* FLASH */
-#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
-
-#endif