1 files changed, 0 insertions, 117 deletions
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/slcr.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/slcr.c
deleted file mode 100644
index d7c188233..000000000
--- a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/slcr.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2013 Xilinx Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-
-#define SLCR_LOCK_MAGIC		0x767B
-#define SLCR_UNLOCK_MAGIC	0xDF0D
-
-#define SLCR_IDCODE_MASK	0x1F000
-#define SLCR_IDCODE_SHIFT	12
-
-static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
-
-void zynq_slcr_lock(void)
-{
-	if (!slcr_lock)
-		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
-}
-
-void zynq_slcr_unlock(void)
-{
-	if (slcr_lock)
-		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
-}
-
-/* Reset the entire system */
-void zynq_slcr_cpu_reset(void)
-{
-	/*
-	 * Unlock the SLCR then reset the system.
-	 * Note that this seems to require raw i/o
-	 * functions or there's a lockup?
-	 */
-	zynq_slcr_unlock();
-
-	/*
-	 * Clear 0x0F000000 bits of reboot status register to workaround
-	 * the FSBL not loading the bitstream after soft-reboot
-	 * This is a temporary solution until we know more.
-	 */
-	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
-
-	writel(1, &slcr_base->pss_rst_ctrl);
-}
-
-/* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
-{
-	int ret;
-
-	zynq_slcr_unlock();
-
-	if (gem_id > 1) {
-		printf("Non existing GEM id %d\n", gem_id);
-		goto out;
-	}
-
-	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
-	if (ret)
-		goto out;
-
-	if (gem_id) {
-		/* Configure GEM_RCLK_CTRL */
-		writel(1, &slcr_base->gem1_rclk_ctrl);
-	} else {
-		/* Configure GEM_RCLK_CTRL */
-		writel(1, &slcr_base->gem0_rclk_ctrl);
-	}
-	udelay(100000);
-out:
-	zynq_slcr_lock();
-}
-
-void zynq_slcr_devcfg_disable(void)
-{
-	zynq_slcr_unlock();
-
-	/* Disable AXI interface */
-	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
-
-	/* Set Level Shifters DT618760 */
-	writel(0xA, &slcr_base->lvl_shftr_en);
-
-	zynq_slcr_lock();
-}
-
-void zynq_slcr_devcfg_enable(void)
-{
-	zynq_slcr_unlock();
-
-	/* Set Level Shifters DT618760 */
-	writel(0xF, &slcr_base->lvl_shftr_en);
-
-	/* Disable AXI interface */
-	writel(0x0, &slcr_base->fpga_rst_ctrl);
-
-	zynq_slcr_lock();
-}
-
-u32 zynq_slcr_get_boot_mode(void)
-{
-	/* Get the bootmode register value */
-	return readl(&slcr_base->boot_mode);
-}
-
-u32 zynq_slcr_get_idcode(void)
-{
-	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
-							SLCR_IDCODE_SHIFT;
-}