diff options
Diffstat (limited to 'qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga')
11 files changed, 0 insertions, 956 deletions
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/Makefile deleted file mode 100644 index cbe1d406d..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2012 Altera Corporation <www.altera.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := lowlevel_init.o -obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/clock_manager.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/clock_manager.c deleted file mode 100644 index 23d697dee..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock_manager.h> - -static const struct socfpga_clock_manager *clock_manager_base = - (void *)SOCFPGA_CLKMGR_ADDRESS; - -#define CLKMGR_BYPASS_ENABLE 1 -#define CLKMGR_BYPASS_DISABLE 0 -#define CLKMGR_STAT_IDLE 0 -#define CLKMGR_STAT_BUSY 1 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1 - -#define CLEAR_BGP_EN_PWRDN \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) - -#define VCO_EN_BASE \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) - -static inline void cm_wait_for_lock(uint32_t mask) -{ - register uint32_t inter_val; - do { - inter_val = readl(&clock_manager_base->inter) & mask; - } while (inter_val != mask); -} - -/* function to poll in the fsm busy bit */ -static inline void cm_wait_for_fsm(void) -{ - while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) - ; -} - -/* - * function to write the bypass register which requires a poll of the - * busy bit - */ -static inline void cm_write_bypass(uint32_t val) -{ - writel(val, &clock_manager_base->bypass); - cm_wait_for_fsm(); -} - -/* function to write the ctrl register which requires a poll of the busy bit */ -static inline void cm_write_ctrl(uint32_t val) -{ - writel(val, &clock_manager_base->ctrl); - cm_wait_for_fsm(); -} - -/* function to write a clock register that has phase information */ -static inline void cm_write_with_phase(uint32_t value, - uint32_t reg_address, uint32_t mask) -{ - /* poll until phase is zero */ - while (readl(reg_address) & mask) - ; - - writel(value, reg_address); - - while (readl(reg_address) & mask) - ; -} - -/* - * Setup clocks while making no assumptions about previous state of the clocks. - * - * Start by being paranoid and gate all sw managed clocks - * Put all plls in bypass - * Put all plls VCO registers back to reset value (bandgap power down). - * Put peripheral and main pll src to reset value to avoid glitch. - * Delay 5 us. - * Deassert bandgap power down and set numerator and denominator - * Start 7 us timer. - * set internal dividers - * Wait for 7 us timer. - * Enable plls - * Set external dividers while plls are locking - * Wait for pll lock - * Assert/deassert outreset all. - * Take all pll's out of bypass - * Clear safe mode - * set source main and peripheral clocks - * Ungate clocks - */ - -void cm_basic_init(const cm_config_t *cfg) -{ - uint32_t start, timeout; - - /* Start by being paranoid and gate all sw managed clocks */ - - /* - * We need to disable nandclk - * and then do another apb access before disabling - * gatting off the rest of the periperal clocks. - */ - writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & - readl(&clock_manager_base->per_pll_en), - &clock_manager_base->per_pll_en); - - /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ - writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | - CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | - CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, - &clock_manager_base->main_pll_en); - - writel(0, &clock_manager_base->sdr_pll_en); - - /* now we can gate off the rest of the peripheral clocks */ - writel(0, &clock_manager_base->per_pll_en); - - /* Put all plls in bypass */ - cm_write_bypass( - CLKMGR_BYPASS_PERPLLSRC_SET( - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_SDRPLLSRC_SET( - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) | - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) | - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE)); - - /* - * Put all plls VCO registers back to reset value. - * Some code might have messed with them. - */ - writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE, - &clock_manager_base->main_pll_vco); - writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE, - &clock_manager_base->per_pll_vco); - writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE, - &clock_manager_base->sdr_pll_vco); - - /* - * The clocks to the flash devices and the L4_MAIN clocks can - * glitch when coming out of safe mode if their source values - * are different from their reset value. So the trick it to - * put them back to their reset state, and change input - * after exiting safe mode but before ungating the clocks. - */ - writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, - &clock_manager_base->per_pll_src); - writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, - &clock_manager_base->main_pll_l4src); - - /* read back for the required 5 us delay. */ - readl(&clock_manager_base->main_pll_vco); - readl(&clock_manager_base->per_pll_vco); - readl(&clock_manager_base->sdr_pll_vco); - - - /* - * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN - * with numerator and denominator. - */ - writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll_vco); - - writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll_vco); - - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll_vco); - - /* - * Time starts here - * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) - */ - reset_timer(); - start = get_timer(0); - /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ - timeout = 7; - - /* main mpu */ - writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk); - - /* main main clock */ - writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk); - - /* main for dbg */ - writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk); - - /* main for cfgs2fuser0clk */ - writel(cfg->cfg2fuser0clk, - &clock_manager_base->main_pll_cfgs2fuser0clk); - - /* Peri emac0 50 MHz default to RMII */ - writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk); - - /* Peri emac1 50 MHz default to RMII */ - writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk); - - /* Peri QSPI */ - writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk); - - writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk); - - /* Peri pernandsdmmcclk */ - writel(cfg->pernandsdmmcclk, - &clock_manager_base->per_pll_pernandsdmmcclk); - - /* Peri perbaseclk */ - writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk); - - /* Peri s2fuser1clk */ - writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk); - - /* 7 us must have elapsed before we can enable the VCO */ - while (get_timer(start) < timeout) - ; - - /* Enable vco */ - /* main pll vco */ - writel(cfg->main_vco_base | VCO_EN_BASE, - &clock_manager_base->main_pll_vco); - - /* periferal pll */ - writel(cfg->peri_vco_base | VCO_EN_BASE, - &clock_manager_base->per_pll_vco); - - /* sdram pll vco */ - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | VCO_EN_BASE, - &clock_manager_base->sdr_pll_vco); - - /* L3 MP and L3 SP */ - writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv); - - writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv); - - writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv); - - /* L4 MP, L4 SP, can0, and can1 */ - writel(cfg->perdiv, &clock_manager_base->per_pll_div); - - writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv); - -#define LOCKED_MASK \ - (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ - CLKMGR_INTER_PERPLLLOCKED_MASK | \ - CLKMGR_INTER_MAINPLLLOCKED_MASK) - - cm_wait_for_lock(LOCKED_MASK); - - /* write the sdram clock counters before toggling outreset all */ - writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll_ddrdqsclk); - - writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll_ddr2xdqsclk); - - writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, - &clock_manager_base->sdr_pll_ddrdqclk); - - writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, - &clock_manager_base->sdr_pll_s2fuser2clk); - - /* - * after locking, but before taking out of bypass - * assert/deassert outresetall - */ - uint32_t mainvco = readl(&clock_manager_base->main_pll_vco); - - /* assert main outresetall */ - writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll_vco); - - uint32_t periphvco = readl(&clock_manager_base->per_pll_vco); - - /* assert pheriph outresetall */ - writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll_vco); - - /* assert sdram outresetall */ - writel(cfg->sdram_vco_base | VCO_EN_BASE| - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1), - &clock_manager_base->sdr_pll_vco); - - /* deassert main outresetall */ - writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll_vco); - - /* deassert pheriph outresetall */ - writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll_vco); - - /* deassert sdram outresetall */ - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | VCO_EN_BASE, - &clock_manager_base->sdr_pll_vco); - - /* - * now that we've toggled outreset all, all the clocks - * are aligned nicely; so we can change any phase. - */ - cm_write_with_phase(cfg->ddrdqsclk, - (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk, - CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); - - /* SDRAM DDR2XDQSCLK */ - cm_write_with_phase(cfg->ddr2xdqsclk, - (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk, - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); - - cm_write_with_phase(cfg->ddrdqclk, - (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk, - CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); - - cm_write_with_phase(cfg->s2fuser2clk, - (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk, - CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); - - /* Take all three PLLs out of bypass when safe mode is cleared. */ - cm_write_bypass( - CLKMGR_BYPASS_PERPLLSRC_SET( - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_SDRPLLSRC_SET( - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) | - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) | - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE)); - - /* clear safe mode */ - cm_write_ctrl(readl(&clock_manager_base->ctrl) | - CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK)); - - /* - * now that safe mode is clear with clocks gated - * it safe to change the source mux for the flashes the the L4_MAIN - */ - writel(cfg->persrc, &clock_manager_base->per_pll_src); - writel(cfg->l4src, &clock_manager_base->main_pll_l4src); - - /* Now ungate non-hw-managed clocks */ - writel(~0, &clock_manager_base->main_pll_en); - writel(~0, &clock_manager_base->per_pll_en); - writel(~0, &clock_manager_base->sdr_pll_en); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/config.mk deleted file mode 100644 index 3d1849157..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# -ifndef CONFIG_SPL_BUILD -ALL-y += u-boot.img -endif diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c deleted file mode 100644 index b8c9bce1e..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/freeze_controller.h> -#include <asm/arch/timer.h> -#include <asm/errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const struct socfpga_freeze_controller *freeze_controller_base = - (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); - -/* - * Default state from cold reset is FREEZE_ALL; the global - * flag is set to TRUE to indicate the IO banks are frozen - */ -static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM] - = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN, - FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN}; - -/* Freeze HPS IOs */ -void sys_mgr_frzctrl_freeze_req(void) -{ - u32 ioctrl_reg_offset; - u32 reg_value; - u32 reg_cfg_mask; - u32 channel_id; - - /* select software FSM */ - writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); - - /* Freeze channel 0 to 2 */ - for (channel_id = 0; channel_id <= 2; channel_id++) { - ioctrl_reg_offset = (u32)( - &freeze_controller_base->vioctrl + - (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); - - /* - * Assert active low enrnsl, plniotri - * and niotri signals - */ - reg_cfg_mask = - SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK - | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK - | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; - clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); - - /* - * Note: Delay for 20ns at min - * Assert active low bhniotri signal and de-assert - * active high csrdone - */ - reg_cfg_mask - = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK - | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; - clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); - - /* Set global flag to indicate channel is frozen */ - frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; - } - - /* Freeze channel 3 */ - /* - * Assert active low enrnsl, plniotri and - * niotri signals - */ - reg_cfg_mask - = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK - | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK - | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; - clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); - - /* - * assert active low bhniotri & nfrzdrv signals, - * de-assert active high csrdone and assert - * active high frzreg and nfrzdrv signals - */ - reg_value = readl(&freeze_controller_base->hioctrl); - reg_cfg_mask - = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK - | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK; - reg_value - = (reg_value & ~reg_cfg_mask) - | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK - | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; - writel(reg_value, &freeze_controller_base->hioctrl); - - /* - * assert active high reinit signal and de-assert - * active high pllbiasen signals - */ - reg_value = readl(&freeze_controller_base->hioctrl); - reg_value - = (reg_value & - ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK) - | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK; - writel(reg_value, &freeze_controller_base->hioctrl); - - /* Set global flag to indicate channel is frozen */ - frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; -} - -/* Unfreeze/Thaw HPS IOs */ -void sys_mgr_frzctrl_thaw_req(void) -{ - u32 ioctrl_reg_offset; - u32 reg_cfg_mask; - u32 reg_value; - u32 channel_id; - - /* select software FSM */ - writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); - - /* Thaw channel 0 to 2 */ - for (channel_id = 0; channel_id <= 2; channel_id++) { - ioctrl_reg_offset - = (u32)(&freeze_controller_base->vioctrl - + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); - - /* - * Assert active low bhniotri signal and - * de-assert active high csrdone - */ - reg_cfg_mask - = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK - | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; - setbits_le32(ioctrl_reg_offset, reg_cfg_mask); - - /* - * Note: Delay for 20ns at min - * de-assert active low plniotri and niotri signals - */ - reg_cfg_mask - = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK - | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; - setbits_le32(ioctrl_reg_offset, reg_cfg_mask); - - /* - * Note: Delay for 20ns at min - * de-assert active low enrnsl signal - */ - setbits_le32(ioctrl_reg_offset, - SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK); - - /* Set global flag to indicate channel is thawed */ - frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; - } - - /* Thaw channel 3 */ - /* de-assert active high reinit signal */ - clrbits_le32(&freeze_controller_base->hioctrl, - SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); - - /* - * Note: Delay for 40ns at min - * assert active high pllbiasen signals - */ - setbits_le32(&freeze_controller_base->hioctrl, - SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); - - /* - * Delay 1000 intosc. intosc is based on eosc1 - * Use worst case which is fatest eosc1=50MHz, delay required - * is 1/50MHz * 1000 = 20us - */ - udelay(20); - - /* - * de-assert active low bhniotri signals, - * assert active high csrdone and nfrzdrv signal - */ - reg_value = readl(&freeze_controller_base->hioctrl); - reg_value = (reg_value - | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK - | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK) - & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; - writel(reg_value, &freeze_controller_base->hioctrl); - - /* - * Delay 33 intosc - * Use worst case which is fatest eosc1=50MHz, delay required - * is 1/50MHz * 33 = 660ns ~= 1us - */ - udelay(1); - - /* de-assert active low plniotri and niotri signals */ - reg_cfg_mask - = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK - | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; - - setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); - - /* - * Note: Delay for 40ns at min - * de-assert active high frzreg signal - */ - clrbits_le32(&freeze_controller_base->hioctrl, - SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK); - - /* - * Note: Delay for 40ns at min - * de-assert active low enrnsl signal - */ - setbits_le32(&freeze_controller_base->hioctrl, - SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK); - - /* Set global flag to indicate channel is thawed */ - frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/lowlevel_init.S deleted file mode 100644 index 1caaa2759..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> - -/* Save the parameter pass in by previous boot loader */ -.global save_boot_params -save_boot_params: - /* save the parameter here */ - - /* - * Setup stack for exception, which is located - * at the end of on-chip RAM. We don't expect exception prior to - * relocation and if that happens, we won't worry -- it will overide - * global data region as the code will goto reset. After relocation, - * this region won't be used by other part of program. - * Hence it is safe. - */ - ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) - ldr r1, =IRQ_STACK_START_IN - str r0, [r1] - - bx lr - - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: - - /* Remap */ -#ifdef CONFIG_SPL_BUILD - /* - * SPL : configure the remap (L3 NIC-301 GPV) - * so the on-chip RAM at lower memory instead ROM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x19 - str r1, [r0] -#else - /* - * U-Boot : configure the remap (L3 NIC-301 GPV) - * so the SDRAM at lower memory instead on-chip RAM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x2 - str r1, [r0] - - /* Private components security */ - - /* - * U-Boot : configure private timer, global timer and cpu - * component access as non secure for kernel stage (as required - * by kernel) - */ - mrc p15,4,r0,c15,c0,0 - add r1, r0, #0x54 - ldr r2, [r1] - orr r2, r2, #0xff - orr r2, r2, #0xf00 - str r2, [r1] -#endif /* #ifdef CONFIG_SPL_BUILD */ - mov pc, lr diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/misc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/misc.c deleted file mode 100644 index 2f1c7160f..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/misc.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - return 0; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c deleted file mode 100644 index e320c011a..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/reset_manager.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ - writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), - &reset_manager_base->ctrl); - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} - -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/spl.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/spl.c deleted file mode 100644 index 2ae88bbd0..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/spl.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/u-boot.h> -#include <asm/utils.h> -#include <version.h> -#include <image.h> -#include <asm/arch/reset_manager.h> -#include <spl.h> -#include <asm/arch/system_manager.h> -#include <asm/arch/freeze_controller.h> - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_RAM; -} - -/* - * Board initialization after bss clearance - */ -void spl_board_init(void) -{ -#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET - cm_config_t cm_default_cfg = { - /* main group */ - MAIN_VCO_BASE, - CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT), - CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT), - CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT), - CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT), - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT), - CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT), - CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK), - CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET( - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) | - CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET( - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK), - CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET( - CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK), - CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET( - CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) | - CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET( - CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP), - - /* peripheral group */ - PERI_VCO_BASE, - CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT), - CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT), - CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT), - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT), - CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT), - CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT), - CLKMGR_PERPLLGRP_DIV_USBCLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_USBCLK) | - CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) | - CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) | - CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK), - CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET( - CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK), - CLKMGR_PERPLLGRP_SRC_QSPI_SET( - CONFIG_HPS_PERPLLGRP_SRC_QSPI) | - CLKMGR_PERPLLGRP_SRC_NAND_SET( - CONFIG_HPS_PERPLLGRP_SRC_NAND) | - CLKMGR_PERPLLGRP_SRC_SDMMC_SET( - CONFIG_HPS_PERPLLGRP_SRC_SDMMC), - - /* sdram pll group */ - SDR_VCO_BASE, - CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT), - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT), - CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT), - CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) | - CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT), - }; - - debug("Freezing all I/O banks\n"); - /* freeze all IO banks */ - sys_mgr_frzctrl_freeze_req(); - - debug("Reconfigure Clock Manager\n"); - /* reconfigure the PLLs */ - cm_basic_init(&cm_default_cfg); - - /* configure the pin muxing through system manager */ - sysmgr_pinmux_init(); -#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ - - /* de-assert reset for peripherals and bridges based on handoff */ - reset_deassert_peripherals_handoff(); - - debug("Unfreezing/Thaw all I/O banks\n"); - /* unfreeze / thaw all IO banks */ - sys_mgr_frzctrl_thaw_req(); - - /* enable console uart printing */ - preloader_console_init(); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/system_manager.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/system_manager.c deleted file mode 100644 index d96521ba0..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/system_manager.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/system_manager.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Configure all the pin muxes - */ -void sysmgr_pinmux_init(void) -{ - unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET; - - const unsigned long *pval = sys_mgr_init_table; - unsigned long i; - - for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); - i++, offset += sizeof(unsigned long)) { - writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset)); - } -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/timer.c deleted file mode 100644 index 58fc789e6..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/timer.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/timer.h> - -static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; - -/* - * Timer initialization - */ -int timer_init(void) -{ - writel(TIMER_LOAD_VAL, &timer_base->load_val); - writel(TIMER_LOAD_VAL, &timer_base->curr_val); - writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); - return 0; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds deleted file mode 100644 index 4282beb39..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - } >.sdram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } - - .bss : { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram - - . = ALIGN(8); - __malloc_start = .; - . = . + CONFIG_SPL_MALLOC_SIZE; - __malloc_end = .; - - . = . + CONFIG_SPL_STACK_SIZE; - . = ALIGN(8); - __stack_start = .; -} |