diff options
Diffstat (limited to 'qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear')
13 files changed, 0 insertions, 1559 deletions
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/Makefile deleted file mode 100644 index 3f190bc0c..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cpu.o \ - reset.o \ - timer.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o spl_boot.o -obj-$(CONFIG_SPEAR600) += spear600.o -obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o -obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o -obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o -obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o -endif - -extra-$(CONFIG_SPL_BUILD) := start.o diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/cpu.c deleted file mode 100644 index 3757ffb2c..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/cpu.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_misc.h> - -int arch_cpu_init(void) -{ - struct misc_regs *const misc_p = - (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - u32 periph1_clken, periph_clk_cfg; - - periph1_clken = readl(&misc_p->periph1_clken); - -#if defined(CONFIG_SPEAR3XX) - periph1_clken |= MISC_GPT2ENB; -#elif defined(CONFIG_SPEAR600) - periph1_clken |= MISC_GPT3ENB; -#endif - -#if defined(CONFIG_PL011_SERIAL) - periph1_clken |= MISC_UART0ENB; - - periph_clk_cfg = readl(&misc_p->periph_clk_cfg); - periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK; - periph_clk_cfg |= CONFIG_SPEAR_UART48M; - writel(periph_clk_cfg, &misc_p->periph_clk_cfg); -#endif -#if defined(CONFIG_DESIGNWARE_ETH) - periph1_clken |= MISC_ETHENB; -#endif -#if defined(CONFIG_DW_UDC) - periph1_clken |= MISC_USBDENB; -#endif -#if defined(CONFIG_DW_I2C) - periph1_clken |= MISC_I2CENB; -#endif -#if defined(CONFIG_ST_SMI) - periph1_clken |= MISC_SMIENB; -#endif -#if defined(CONFIG_NAND_FSMC) - periph1_clken |= MISC_FSMCENB; -#endif - - writel(periph1_clken, &misc_p->periph1_clken); - return 0; -} - -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) -{ -#ifdef CONFIG_SPEAR300 - printf("CPU: SPEAr300\n"); -#elif defined(CONFIG_SPEAR310) - printf("CPU: SPEAr310\n"); -#elif defined(CONFIG_SPEAR320) - printf("CPU: SPEAr320\n"); -#elif defined(CONFIG_SPEAR600) - printf("CPU: SPEAr600\n"); -#else -#error CPU not supported in spear platform -#endif - return 0; -} -#endif diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/reset.c deleted file mode 100644 index 9546e80bc..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/reset.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_syscntl.h> - -void reset_cpu(ulong ignored) -{ - struct syscntl_regs *syscntl_regs_p = - (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; - - printf("System is going to reboot ...\n"); - - /* - * This 1 second delay will allow the above message - * to be printed before reset - */ - udelay((1000 * 1000)); - - /* Going into slow mode before resetting SOC */ - writel(0x02, &syscntl_regs_p->scctrl); - - /* - * Writing any value to the system status register will - * reset the SoC - */ - writel(0x00, &syscntl_regs_p->scsysstat); - - /* system will restart */ - while (1) - ; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spear600.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spear600.c deleted file mode 100644 index 6474e9d55..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spear600.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/hardware.h> -#include <asm/io.h> -#include <asm/arch/spr_misc.h> -#include <asm/arch/spr_defs.h> - -static void sel_1v8(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - u32 ddr1v8, ddr2v5; - - ddr2v5 = readl(&misc_p->ddr_2v5_compensation); - ddr2v5 &= 0x8080ffc0; - ddr2v5 |= 0x78000003; - writel(ddr2v5, &misc_p->ddr_2v5_compensation); - - ddr1v8 = readl(&misc_p->ddr_1v8_compensation); - ddr1v8 &= 0x8080ffc0; - ddr1v8 |= 0x78000010; - writel(ddr1v8, &misc_p->ddr_1v8_compensation); - - while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) - ; -} - -static void sel_2v5(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - u32 ddr1v8, ddr2v5; - - ddr1v8 = readl(&misc_p->ddr_1v8_compensation); - ddr1v8 &= 0x8080ffc0; - ddr1v8 |= 0x78000003; - writel(ddr1v8, &misc_p->ddr_1v8_compensation); - - ddr2v5 = readl(&misc_p->ddr_2v5_compensation); - ddr2v5 &= 0x8080ffc0; - ddr2v5 |= 0x78000010; - writel(ddr2v5, &misc_p->ddr_2v5_compensation); - - while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) - ; -} - -/* - * plat_ddr_init: - */ -void plat_ddr_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - u32 ddrpad; - u32 core3v3, ddr1v8, ddr2v5; - - /* DDR pad register configurations */ - ddrpad = readl(&misc_p->ddr_pad); - ddrpad &= ~DDR_PAD_CNF_MSK; - -#if (CONFIG_DDR_HCLK) - ddrpad |= 0xEAAB; -#elif (CONFIG_DDR_2HCLK) - ddrpad |= 0xEAAD; -#elif (CONFIG_DDR_PLL2) - ddrpad |= 0xEAAD; -#endif - writel(ddrpad, &misc_p->ddr_pad); - - /* Compensation register configurations */ - core3v3 = readl(&misc_p->core_3v3_compensation); - core3v3 &= 0x8080ffe0; - core3v3 |= 0x78000002; - writel(core3v3, &misc_p->core_3v3_compensation); - - ddr1v8 = readl(&misc_p->ddr_1v8_compensation); - ddr1v8 &= 0x8080ffc0; - ddr1v8 |= 0x78000004; - writel(ddr1v8, &misc_p->ddr_1v8_compensation); - - ddr2v5 = readl(&misc_p->ddr_2v5_compensation); - ddr2v5 &= 0x8080ffc0; - ddr2v5 |= 0x78000004; - writel(ddr2v5, &misc_p->ddr_2v5_compensation); - - if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) { - /* Software memory configuration */ - if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL) - sel_1v8(); - else - sel_2v5(); - } else { - /* Hardware memory configuration */ - if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE) - sel_1v8(); - else - sel_2v5(); - } -} - -/* - * soc_init: - */ -void soc_init(void) -{ - /* Nothing to be done for SPEAr600 */ -} - -/* - * xxx_boot_selected: - * - * return true if the particular booting option is selected - * return false otherwise - */ -static u32 read_bootstrap(void) -{ - return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT) - & CONFIG_SPEAR_BOOTSTRAPMASK; -} - -int snor_boot_selected(void) -{ - u32 bootstrap = read_bootstrap(); - - if (SNOR_BOOT_SUPPORTED) { - /* Check whether SNOR boot is selected */ - if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) == - CONFIG_SPEAR_ONLYSNORBOOT) - return true; - - if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == - CONFIG_SPEAR_NORNAND8BOOT) - return true; - - if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == - CONFIG_SPEAR_NORNAND16BOOT) - return true; - } - - return false; -} - -int nand_boot_selected(void) -{ - u32 bootstrap = read_bootstrap(); - - if (NAND_BOOT_SUPPORTED) { - /* Check whether NAND boot is selected */ - if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == - CONFIG_SPEAR_NORNAND8BOOT) - return true; - - if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == - CONFIG_SPEAR_NORNAND16BOOT) - return true; - } - - return false; -} - -int pnor_boot_selected(void) -{ - /* Parallel NOR boot is not selected in any SPEAr600 revision */ - return false; -} - -int usb_boot_selected(void) -{ - u32 bootstrap = read_bootstrap(); - - if (USB_BOOT_SUPPORTED) { - /* Check whether USB boot is selected */ - if (!(bootstrap & CONFIG_SPEAR_USBBOOT)) - return true; - } - - return false; -} - -int tftp_boot_selected(void) -{ - /* TFTP boot is not selected in any SPEAr600 revision */ - return false; -} - -int uart_boot_selected(void) -{ - /* UART boot is not selected in any SPEAr600 revision */ - return false; -} - -int spi_boot_selected(void) -{ - /* SPI boot is not selected in any SPEAr600 revision */ - return false; -} - -int i2c_boot_selected(void) -{ - /* I2C boot is not selected in any SPEAr600 revision */ - return false; -} - -int mmc_boot_selected(void) -{ - return false; -} - -void plat_late_init(void) -{ - spear_late_init(); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl.c deleted file mode 100644 index b55040435..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Copyright (C) 2012 Stefan Roese <sr@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <version.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_defs.h> -#include <asm/arch/spr_misc.h> -#include <asm/arch/spr_syscntl.h> - -static void ddr_clock_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - u32 clkenb, ddrpll; - - clkenb = readl(&misc_p->periph1_clken); - clkenb &= ~PERIPH_MPMCMSK; - clkenb |= PERIPH_MPMC_WE; - - /* Intentionally done twice */ - writel(clkenb, &misc_p->periph1_clken); - writel(clkenb, &misc_p->periph1_clken); - - ddrpll = readl(&misc_p->pll_ctr_reg); - ddrpll &= ~MEM_CLK_SEL_MSK; -#if (CONFIG_DDR_HCLK) - ddrpll |= MEM_CLK_HCLK; -#elif (CONFIG_DDR_2HCLK) - ddrpll |= MEM_CLK_2HCLK; -#elif (CONFIG_DDR_PLL2) - ddrpll |= MEM_CLK_PLL2; -#else -#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)" -#endif - writel(ddrpll, &misc_p->pll_ctr_reg); - - writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN, - &misc_p->periph1_clken); -} - -static void mpmc_init_values(void) -{ - u32 i; - u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; - u32 *mpmc_val_p = &mpmc_conf_vals[0]; - - for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++) - writel(*mpmc_val_p, mpmc_reg_p); - - mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; - - /* - * MPMC controller start - * MPMC waiting for DLLLOCKREG high - */ - writel(0x01000100, &mpmc_reg_p[7]); - - while (!(readl(&mpmc_reg_p[3]) & 0x10000)) - ; -} - -static void mpmc_init(void) -{ - /* Clock related settings for DDR */ - ddr_clock_init(); - - /* - * DDR pad register bits are different for different SoCs - * Compensation values are also handled separately - */ - plat_ddr_init(); - - /* Initialize mpmc register values */ - mpmc_init_values(); -} - -static void pll_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - - /* Initialize PLLs */ - writel(FREQ_332, &misc_p->pll1_frq); - writel(0x1C0A, &misc_p->pll1_cntl); - writel(0x1C0E, &misc_p->pll1_cntl); - writel(0x1C06, &misc_p->pll1_cntl); - writel(0x1C0E, &misc_p->pll1_cntl); - - writel(FREQ_332, &misc_p->pll2_frq); - writel(0x1C0A, &misc_p->pll2_cntl); - writel(0x1C0E, &misc_p->pll2_cntl); - writel(0x1C06, &misc_p->pll2_cntl); - writel(0x1C0E, &misc_p->pll2_cntl); - - /* wait for pll locks */ - while (!(readl(&misc_p->pll1_cntl) & 0x1)) - ; - while (!(readl(&misc_p->pll2_cntl) & 0x1)) - ; -} - -static void mac_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - - writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC), - &misc_p->periph1_clken); - - writel(SYNTH23, &misc_p->gmac_synth_clk); - - switch (get_socrev()) { - case SOC_SPEAR600_AA: - case SOC_SPEAR600_AB: - case SOC_SPEAR600_BA: - case SOC_SPEAR600_BB: - case SOC_SPEAR600_BC: - case SOC_SPEAR600_BD: - writel(0x0, &misc_p->gmac_ctr_reg); - break; - - case SOC_SPEAR300: - case SOC_SPEAR310: - case SOC_SPEAR320: - writel(0x4, &misc_p->gmac_ctr_reg); - break; - } - - writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC, - &misc_p->periph1_clken); - - writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC, - &misc_p->periph1_rst); - writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC), - &misc_p->periph1_rst); -} - -static void sys_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - struct syscntl_regs *syscntl_p = - (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; - - /* Set system state to SLOW */ - writel(SLOW, &syscntl_p->scctrl); - writel(PLL_TIM << 3, &syscntl_p->scpllctrl); - - /* Initialize PLLs */ - pll_init(); - - /* - * Ethernet configuration - * To be done only if the tftp boot is not selected already - * Boot code ensures the correct configuration in tftp booting - */ - if (!tftp_boot_selected()) - mac_init(); - - writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg); - writel(0x555, &misc_p->amba_clk_cfg); - - writel(NORMAL, &syscntl_p->scctrl); - - /* Wait for system to switch to normal mode */ - while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK) - != NORMAL) - ; -} - -/* - * get_socrev - * - * Get SoC Revision. - * @return SOC_SPEARXXX - */ -int get_socrev(void) -{ -#if defined(CONFIG_SPEAR600) - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - u32 soc_id = readl(&misc_p->soc_core_id); - u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF; - u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF; - - if ((pri_socid == 'B') && (sec_socid == 'B')) - return SOC_SPEAR600_BB; - else if ((pri_socid == 'B') && (sec_socid == 'C')) - return SOC_SPEAR600_BC; - else if ((pri_socid == 'B') && (sec_socid == 'D')) - return SOC_SPEAR600_BD; - else if (soc_id == 0) - return SOC_SPEAR600_BA; - else - return SOC_SPEAR_NA; -#elif defined(CONFIG_SPEAR300) - return SOC_SPEAR300; -#elif defined(CONFIG_SPEAR310) - return SOC_SPEAR310; -#elif defined(CONFIG_SPEAR320) - return SOC_SPEAR320; -#endif -} - -void lowlevel_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - const char *u_boot_rev = U_BOOT_VERSION; - - /* Initialize PLLs */ - sys_init(); - - /* Initialize UART */ - serial_init(); - - /* Print U-Boot SPL version string */ - serial_puts("\nU-Boot SPL "); - /* Avoid a second "U-Boot" coming from this string */ - u_boot_rev = &u_boot_rev[7]; - serial_puts(u_boot_rev); - serial_puts(" ("); - serial_puts(U_BOOT_DATE); - serial_puts(" - "); - serial_puts(U_BOOT_TIME); - serial_puts(")\n"); - -#if defined(CONFIG_OS_BOOT) - writel(readl(&misc_p->periph1_clken) | PERIPH_UART1, - &misc_p->periph1_clken); -#endif - - /* Enable IPs (release reset) */ - writel(PERIPH_RST_ALL, &misc_p->periph1_rst); - - /* Initialize MPMC */ - serial_puts("Configure DDR\n"); - mpmc_init(); - - /* SoC specific initialization */ - soc_init(); -} - -void spear_late_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - - writel(0x80000007, &misc_p->arb_icm_ml1); - writel(0x80000007, &misc_p->arb_icm_ml2); - writel(0x80000007, &misc_p->arb_icm_ml3); - writel(0x80000007, &misc_p->arb_icm_ml4); - writel(0x80000007, &misc_p->arb_icm_ml5); - writel(0x80000007, &misc_p->arb_icm_ml6); - writel(0x80000007, &misc_p->arb_icm_ml7); - writel(0x80000007, &misc_p->arb_icm_ml8); - writel(0x80000007, &misc_p->arb_icm_ml9); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl_boot.c deleted file mode 100644 index c846d758c..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl_boot.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com - * - * Copyright (C) 2012 Stefan Roese <sr@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <image.h> -#include <linux/compiler.h> -#include <asm/io.h> -#include <asm/arch/spr_defs.h> -#include <linux/mtd/st_smi.h> - -static const char kernel_name[] = "Linux"; -static const char loader_name[] = "U-Boot"; - -int image_check_header(image_header_t *hdr, const char *name) -{ - if (image_check_magic(hdr) && - (!strncmp(image_get_name(hdr), name, strlen(name))) && - image_check_hcrc(hdr)) { - return 1; - } - return 0; -} - -int image_check_data(image_header_t *hdr) -{ - if (image_check_dcrc(hdr)) - return 1; - - return 0; -} - -/* - * SNOR (Serial NOR flash) related functions - */ -void snor_init(void) -{ - struct smi_regs *const smicntl = - (struct smi_regs * const)CONFIG_SYS_SMI_BASE; - - /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ - writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, - &smicntl->smi_cr1); -} - -static int snor_image_load(u8 *load_addr, void (**image_p)(void), - const char *image_name) -{ - image_header_t *header; - - /* - * Since calculating the crc in the SNOR flash does not - * work, we copy the image to the destination address - * minus the header size. And point the header to this - * new destination. This will not work for address 0 - * of course. - */ - header = (image_header_t *)load_addr; - memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)), - (const ulong *)load_addr, - image_get_data_size(header) + sizeof(image_header_t)); - header = (image_header_t *)(image_get_load(header) - - sizeof(image_header_t)); - - if (image_check_header(header, image_name)) { - if (image_check_data(header)) { - /* Jump to boot image */ - *image_p = (void *)image_get_load(header); - return 1; - } - } - - return 0; -} - -static void boot_image(void (*image)(void)) -{ - void (*funcp)(void) __noreturn = (void *)image; - - (*funcp)(); -} - -/* - * spl_boot: - * - * All supported booting types of all supported SoCs are listed here. - * Generic readback APIs are provided for each supported booting type - * eg. nand_read_skip_bad - */ -u32 spl_boot(void) -{ - void (*image)(void); - -#ifdef CONFIG_SPEAR_USBTTY - plat_late_init(); - return 1; -#endif - - /* - * All the supported booting devices are listed here. Each of - * the booting type supported by the platform would define the - * macro xxx_BOOT_SUPPORTED to true. - */ - - if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) { - /* SNOR-SMI initialization */ - snor_init(); - - serial_puts("Booting via SNOR\n"); - /* Serial NOR booting */ - if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE, - &image, loader_name)) { - /* Platform related late initialasations */ - plat_late_init(); - - /* Jump to boot image */ - serial_puts("Jumping to U-Boot\n"); - boot_image(image); - return 1; - } - } - - if (NAND_BOOT_SUPPORTED && nand_boot_selected()) { - /* NAND booting */ - /* Not ported from XLoader to SPL yet */ - return 0; - } - - if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) { - /* PNOR booting */ - /* Not ported from XLoader to SPL yet */ - return 0; - } - - if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) { - /* MMC booting */ - /* Not ported from XLoader to SPL yet */ - return 0; - } - - if (SPI_BOOT_SUPPORTED && spi_boot_selected()) { - /* SPI booting */ - /* Not supported for any platform as of now */ - return 0; - } - - if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) { - /* I2C booting */ - /* Not supported for any platform as of now */ - return 0; - } - - /* - * All booting types without memory are listed as below - * Control has to be returned to BootROM in case of all - * the following booting scenarios - */ - - if (USB_BOOT_SUPPORTED && usb_boot_selected()) { - plat_late_init(); - return 1; - } - - if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) { - plat_late_init(); - return 1; - } - - if (UART_BOOT_SUPPORTED && uart_boot_selected()) { - plat_late_init(); - return 1; - } - - /* Ideally, the control should not reach here. */ - hang(); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c deleted file mode 100644 index 3d6ad04ab..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if (CONFIG_DDR_PLL2) - -const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { - 0x00000001, - 0x00000000, - 0x01000000, - 0x00000101, - 0x00000001, - 0x01000000, - 0x00010001, - 0x00000100, - 0x00010001, - 0x00000003, - 0x01000201, - 0x06000202, - 0x06060106, - 0x03050502, - 0x03040404, - 0x02020503, - 0x02010106, - 0x03000404, - 0x02030202, - 0x03000204, - 0x0707073f, - 0x07070707, - 0x06060607, - 0x06060606, - 0x05050506, - 0x05050505, - 0x04040405, - 0x04040404, - 0x03030304, - 0x03030303, - 0x02020203, - 0x02020202, - 0x01010102, - 0x01010101, - 0x08080a01, - 0x0000023f, - 0x00040800, - 0x00000000, - 0x00000f02, - 0x00001b1b, - 0x7f000000, - 0x005f0000, - 0x1c040b6a, - 0x00640064, - 0x00640064, - 0x00640064, - 0x00000064, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x000007ff, - 0x00000000, - 0x47ec00c8, - 0x00c8001f, - 0x00000000, - 0x0000cd98, - 0x00000000, - 0x03030100, - 0x03030303, - 0x03030303, - 0x03030303, - 0x00270000, - 0x00250027, - 0x00300000, - 0x008900b7, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000 -}; -#endif diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c deleted file mode 100644 index 105b3058f..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) - -const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { -#if (CONFIG_DDR_PLL2) - 0x00000001, - 0x00000000, -#elif (CONFIG_DDR_2HCLK) - 0x02020201, - 0x02020202, -#endif - 0x01000000, - 0x00000101, - 0x00000101, - 0x01000000, - 0x00010001, - 0x00000100, - 0x01010001, - 0x00000201, - 0x01000101, - 0x06000002, - 0x06060106, - 0x03050502, - 0x03040404, - 0x02020503, - 0x02010106, - 0x03000405, - 0x03040202, - 0x04000305, - 0x0707073f, - 0x07070707, - 0x06060607, - 0x06060606, - 0x05050506, - 0x05050505, - 0x04040405, - 0x04040404, - 0x03030304, - 0x03030303, - 0x02020203, - 0x02020202, - 0x01010102, - 0x01010101, - 0x0a0a0a01, - 0x0000023f, - 0x00050a00, - 0x11000000, - 0x00001302, - 0x00000A0A, - 0x72000000, - 0x00550000, - 0x2b050e86, - 0x00640064, - 0x00640064, - 0x00640064, - 0x00000064, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00000a24, - 0x43C20000, - 0x5b1c00c8, - 0x00c8002e, - 0x00000000, - 0x0001046b, - 0x00000000, - 0x03030100, - 0x03030303, - 0x03030303, - 0x03030303, - 0x00210000, - 0x00010021, - 0x00200000, - 0x006c0090, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000 -}; -#endif diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c deleted file mode 100644 index 00b6b2927..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if (CONFIG_DDR_HCLK) - -const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { - 0x03030301, - 0x03030303, - 0x01000000, - 0x00000101, - 0x00000001, - 0x01000000, - 0x00010001, - 0x00000100, - 0x00010001, - 0x00000003, - 0x01000201, - 0x06000202, - 0x06060106, - 0x03050502, - 0x03040404, - 0x02020503, - 0x02010106, - 0x03000404, - 0x02020202, - 0x03000203, - 0x0707073f, - 0x07070707, - 0x06060607, - 0x06060606, - 0x05050506, - 0x05050505, - 0x04040405, - 0x04040404, - 0x03030304, - 0x03030303, - 0x02020203, - 0x02020202, - 0x01010102, - 0x01010101, - 0x08080a01, - 0x0000023f, - 0x00030600, - 0x00000000, - 0x00000a02, - 0x00001c1c, - 0x7f000000, - 0x005f0000, - 0x12030743, - 0x00640064, - 0x00640064, - 0x00640064, - 0x00000064, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x0000050e, - 0x00000000, - 0x2d8900c8, - 0x00c80014, - 0x00000000, - 0x00008236, - 0x00000000, - 0x03030100, - 0x03030303, - 0x03030303, - 0x03030303, - 0x00400000, - 0x003a0040, - 0x00680000, - 0x00d80120, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000 -}; -#endif diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c deleted file mode 100644 index a406c3e8c..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) - -const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { -#if (CONFIG_DDR_PLL2) - 0x00000001, - 0x00000000, -#elif (CONFIG_DDR_2HCLK) - 0x02020201, - 0x02020202, -#endif - 0x01000000, - 0x00000101, - 0x00000101, - 0x01000000, - 0x00010001, - 0x00000100, - 0x01010001, - 0x00000201, - 0x01000101, - 0x06000002, - 0x06060106, - 0x03050502, - 0x03040404, - 0x02020503, -#ifdef CONFIG_X600 - 0x02030206, -#else - 0x02010106, -#endif - 0x03000405, - 0x03040202, - 0x04000305, - 0x0707073f, - 0x07070707, - 0x06060607, - 0x06060606, - 0x05050506, - 0x05050505, - 0x04040405, - 0x04040404, - 0x03030304, - 0x03030303, - 0x02020203, - 0x02020202, - 0x01010102, - 0x01010101, - 0x0a0a0a01, - 0x0000023f, - 0x00050a00, - 0x11000000, - 0x00001302, - 0x00000A0A, -#ifdef CONFIG_X600 - 0x7f000000, - 0x005c0000, -#else - 0x72000000, - 0x00550000, -#endif - 0x2b050e86, - 0x00640064, - 0x00640064, - 0x00640064, - 0x00000064, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00200020, - 0x00000a24, - 0x43C20000, - 0x5b1c00c8, - 0x00c8002e, - 0x00000000, - 0x0001046b, - 0x00000000, - 0x03030100, - 0x03030303, - 0x03030303, - 0x03030303, - 0x00210000, - 0x00010021, - 0x00200000, - 0x006c0090, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x003fffff, - 0x003fffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000 -}; -#endif diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/start.S deleted file mode 100644 index 7dbd5dbf9..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/start.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (c) 2003 Kshitij <kshitij@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <config.h> - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: -_software_interrupt: -_prefetch_abort: -_data_abort: -_not_used: -_irq: -_fiq: - .word infinite_loop - -infinite_loop: - b infinite_loop - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * Below are the critical initializations already taken place in BootROM. - * So, these are not taken care in Xloader - * 1. Relocation to RAM - * 2. Initializing stacks - * - ************************************************************************* - */ - -/* - * the actual reset code - */ - -reset: -/* - * Xloader has to return back to BootROM in a few cases. - * eg. Ethernet boot, UART boot, USB boot - * Saving registers for returning back - */ - stmdb sp!, {r0-r12,r14} - bl cpu_init_crit -/* - * Clearing bss area is not done in Xloader. - * BSS area lies in the DDR location which is not yet initialized - * bss is assumed to be uninitialized. - */ - bl spl_boot - ldmia sp!, {r0-r12,pc} - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * enable instruction cache - */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ - mcr p15, 0, r0, c1, c0, 0 - - /* - * Go setup Memory and board specific bits prior to relocation. - */ - stmdb sp!, {lr} - bl lowlevel_init /* go setup pll,mux,memory */ - ldmia sp!, {pc} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/timer.c deleted file mode 100644 index c88e962a3..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/timer.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_gpt.h> -#include <asm/arch/spr_misc.h> - -#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ) -#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING) - -static struct gpt_regs *const gpt_regs_p = - (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE; - -static struct misc_regs *const misc_regs_p = - (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -int timer_init(void) -{ - u32 synth; - - /* Prescaler setting */ -#if defined(CONFIG_SPEAR3XX) - writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg); - synth = MISC_GPT4SYNTH; -#elif defined(CONFIG_SPEAR600) - writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg); - synth = MISC_GPT3SYNTH; -#else -# error Incorrect config. Can only be spear{600|300|310|320} -#endif - - writel(readl(&misc_regs_p->periph_clk_cfg) | synth, - &misc_regs_p->periph_clk_cfg); - - /* disable timers */ - writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control); - - /* load value for free running */ - writel(GPT_FREE_RUNNING, &gpt_regs_p->compare); - - /* auto reload, start timer */ - writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); - - /* Reset the timer */ - lastdec = READ_TIMER(); - timestamp = 0; - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer(ulong base) -{ - return (get_timer_masked() / GPT_RESOLUTION) - base; -} - -void __udelay(unsigned long usec) -{ - ulong tmo; - ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100); - ulong rndoff; - - rndoff = (usec % 10) ? 1 : 0; - - /* tenudelcnt timer tick gives 10 microsecconds delay */ - tmo = ((usec / 10) + rndoff) * tenudelcnt; - - while ((ulong) (get_timer_masked() - start) < tmo) - ; -} - -ulong get_timer_masked(void) -{ - ulong now = READ_TIMER(); - - if (now >= lastdec) { - /* normal mode */ - timestamp += now - lastdec; - } else { - /* we have an overflow ... */ - timestamp += now + GPT_FREE_RUNNING - lastdec; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked(unsigned long usec) -{ - return udelay(usec); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SPEAR_HZ; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds deleted file mode 100644 index b6d0f65b6..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm926ejs/spear/start.o (.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .bss : { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} |