diff options
Diffstat (limited to 'qemu/roms/ipxe/src/drivers/bitbash')
| -rw-r--r-- | qemu/roms/ipxe/src/drivers/bitbash/bitbash.c | 58 | ||||
| -rw-r--r-- | qemu/roms/ipxe/src/drivers/bitbash/i2c_bit.c | 403 | ||||
| -rw-r--r-- | qemu/roms/ipxe/src/drivers/bitbash/spi_bit.c | 235 |
3 files changed, 696 insertions, 0 deletions
diff --git a/qemu/roms/ipxe/src/drivers/bitbash/bitbash.c b/qemu/roms/ipxe/src/drivers/bitbash/bitbash.c new file mode 100644 index 000000000..23ca30356 --- /dev/null +++ b/qemu/roms/ipxe/src/drivers/bitbash/bitbash.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <ipxe/bitbash.h> + +/** @file + * + * Bit-bashing interfaces + * + */ + +/** + * Set/clear output bit + * + * @v basher Bit-bashing interface + * @v bit_id Bit number + * @v data Value to write + * + * If @c data is 0, a logic 0 will be written. If @c data is + * non-zero, a logic 1 will be written. + */ +void write_bit ( struct bit_basher *basher, unsigned int bit_id, + unsigned long data ) { + basher->op->write ( basher, bit_id, ( data ? -1UL : 0 ) ); +} + +/** + * Read input bit + * + * @v basher Bit-bashing interface + * @v bit_id Bit number + * @ret data Value read + * + * @c data will always be either 0 or -1UL. The idea is that the + * caller can simply binary-AND the returned value with whatever mask + * it needs to apply. + */ +int read_bit ( struct bit_basher *basher, unsigned int bit_id ) { + return ( basher->op->read ( basher, bit_id ) ? -1UL : 0 ); +} diff --git a/qemu/roms/ipxe/src/drivers/bitbash/i2c_bit.c b/qemu/roms/ipxe/src/drivers/bitbash/i2c_bit.c new file mode 100644 index 000000000..decc8d80e --- /dev/null +++ b/qemu/roms/ipxe/src/drivers/bitbash/i2c_bit.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stddef.h> +#include <stdint.h> +#include <errno.h> +#include <string.h> +#include <assert.h> +#include <unistd.h> +#include <ipxe/bitbash.h> +#include <ipxe/i2c.h> + +/** @file + * + * I2C bit-bashing interface + * + * This implements a simple I2C master via a bit-bashing interface + * that provides two lines: SCL (clock) and SDA (data). + */ + +/** + * Delay between output state changes + * + * Max rated i2c speed (for the basic i2c protocol) is 100kbps, + * i.e. 200k clock transitions per second. + */ +static void i2c_delay ( void ) { + udelay ( I2C_UDELAY ); +} + +/** + * Set state of I2C SCL line + * + * @v basher Bit-bashing interface + * @v state New state of SCL + */ +static void setscl ( struct bit_basher *basher, int state ) { + DBG2 ( "%c", ( state ? '/' : '\\' ) ); + write_bit ( basher, I2C_BIT_SCL, state ); + i2c_delay(); +} + +/** + * Set state of I2C SDA line + * + * @v basher Bit-bashing interface + * @v state New state of SDA + */ +static void setsda ( struct bit_basher *basher, int state ) { + DBG2 ( "%c", ( state ? '1' : '0' ) ); + write_bit ( basher, I2C_BIT_SDA, state ); + i2c_delay(); +} + +/** + * Get state of I2C SDA line + * + * @v basher Bit-bashing interface + * @ret state State of SDA + */ +static int getsda ( struct bit_basher *basher ) { + int state; + state = read_bit ( basher, I2C_BIT_SDA ); + DBG2 ( "%c", ( state ? '+' : '-' ) ); + return state; +} + +/** + * Send an I2C start condition + * + * @v basher Bit-bashing interface + */ +static void i2c_start ( struct bit_basher *basher ) { + setscl ( basher, 1 ); + setsda ( basher, 0 ); + setscl ( basher, 0 ); + setsda ( basher, 1 ); +} + +/** + * Send an I2C data bit + * + * @v basher Bit-bashing interface + * @v bit Bit to send + */ +static void i2c_send_bit ( struct bit_basher *basher, int bit ) { + setsda ( basher, bit ); + setscl ( basher, 1 ); + setscl ( basher, 0 ); + setsda ( basher, 1 ); +} + +/** + * Receive an I2C data bit + * + * @v basher Bit-bashing interface + * @ret bit Received bit + */ +static int i2c_recv_bit ( struct bit_basher *basher ) { + int bit; + + setscl ( basher, 1 ); + bit = getsda ( basher ); + setscl ( basher, 0 ); + return bit; +} + +/** + * Send an I2C stop condition + * + * @v basher Bit-bashing interface + */ +static void i2c_stop ( struct bit_basher *basher ) { + setsda ( basher, 0 ); + setscl ( basher, 1 ); + setsda ( basher, 1 ); +} + +/** + * Send byte via I2C bus and check for acknowledgement + * + * @v basher Bit-bashing interface + * @v byte Byte to send + * @ret rc Return status code + * + * Sends a byte via the I2C bus and checks for an acknowledgement from + * the slave device. + */ +static int i2c_send_byte ( struct bit_basher *basher, uint8_t byte ) { + int i; + int ack; + + /* Send byte */ + DBG2 ( "[send %02x]", byte ); + for ( i = 8 ; i ; i-- ) { + i2c_send_bit ( basher, byte & 0x80 ); + byte <<= 1; + } + + /* Check for acknowledgement from slave */ + ack = ( i2c_recv_bit ( basher ) == 0 ); + DBG2 ( "%s", ( ack ? "[acked]" : "[not acked]" ) ); + + return ( ack ? 0 : -EIO ); +} + +/** + * Receive byte via I2C bus + * + * @v basher Bit-bashing interface + * @ret byte Received byte + * + * Receives a byte via the I2C bus and sends NACK to the slave device. + */ +static uint8_t i2c_recv_byte ( struct bit_basher *basher ) { + uint8_t byte = 0; + int i; + + /* Receive byte */ + for ( i = 8 ; i ; i-- ) { + byte <<= 1; + byte |= ( i2c_recv_bit ( basher ) & 0x1 ); + } + + /* Send NACK */ + i2c_send_bit ( basher, 1 ); + + DBG2 ( "[rcvd %02x]", byte ); + return byte; +} + +/** + * Select I2C device for reading or writing + * + * @v basher Bit-bashing interface + * @v i2cdev I2C device + * @v offset Starting offset within the device + * @v direction I2C_READ or I2C_WRITE + * @ret rc Return status code + */ +static int i2c_select ( struct bit_basher *basher, struct i2c_device *i2cdev, + unsigned int offset, unsigned int direction ) { + unsigned int address; + int shift; + unsigned int byte; + int rc; + + i2c_start ( basher ); + + /* Calculate address to appear on bus */ + address = ( ( ( i2cdev->dev_addr | + ( offset >> ( 8 * i2cdev->word_addr_len ) ) ) << 1 ) + | direction ); + + /* Send address a byte at a time */ + for ( shift = ( 8 * ( i2cdev->dev_addr_len - 1 ) ) ; + shift >= 0 ; shift -= 8 ) { + byte = ( ( address >> shift ) & 0xff ); + if ( ( rc = i2c_send_byte ( basher, byte ) ) != 0 ) + return rc; + } + + return 0; +} + +/** + * Reset I2C bus + * + * @v basher Bit-bashing interface + * @ret rc Return status code + * + * i2c devices often don't have a reset line, so even a reboot or + * system power cycle is sometimes not enough to bring them back to a + * known state. + */ +static int i2c_reset ( struct bit_basher *basher ) { + unsigned int i; + int sda; + + /* Clock through several cycles, waiting for an opportunity to + * pull SDA low while SCL is high (which creates a start + * condition). + */ + open_bit ( basher ); + setscl ( basher, 0 ); + setsda ( basher, 1 ); + for ( i = 0 ; i < I2C_RESET_MAX_CYCLES ; i++ ) { + setscl ( basher, 1 ); + sda = getsda ( basher ); + if ( sda ) { + /* Now that the device will see a start, issue it */ + i2c_start ( basher ); + /* Stop the bus to leave it in a known good state */ + i2c_stop ( basher ); + DBGC ( basher, "I2CBIT %p reset after %d attempts\n", + basher, ( i + 1 ) ); + close_bit ( basher ); + return 0; + } + setscl ( basher, 0 ); + } + + DBGC ( basher, "I2CBIT %p could not reset after %d attempts\n", + basher, i ); + close_bit ( basher ); + return -ETIMEDOUT; +} + +/** + * Read data from I2C device via bit-bashing interface + * + * @v i2c I2C interface + * @v i2cdev I2C device + * @v offset Starting offset within the device + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + * + * Note that attempting to read zero bytes of data is a valid way to + * check for I2C device presence. + */ +static int i2c_bit_read ( struct i2c_interface *i2c, + struct i2c_device *i2cdev, unsigned int offset, + uint8_t *data, unsigned int len ) { + struct i2c_bit_basher *i2cbit + = container_of ( i2c, struct i2c_bit_basher, i2c ); + struct bit_basher *basher = &i2cbit->basher; + int rc = 0; + + DBGC ( basher, "I2CBIT %p reading from device %x: ", + basher, i2cdev->dev_addr ); + + open_bit ( basher ); + + for ( ; ; data++, offset++ ) { + + /* Select device for writing */ + if ( ( rc = i2c_select ( basher, i2cdev, offset, + I2C_WRITE ) ) != 0 ) + break; + + /* Abort at end of data */ + if ( ! ( len-- ) ) + break; + + /* Select offset */ + if ( ( rc = i2c_send_byte ( basher, offset ) ) != 0 ) + break; + + /* Select device for reading */ + if ( ( rc = i2c_select ( basher, i2cdev, offset, + I2C_READ ) ) != 0 ) + break; + + /* Read byte */ + *data = i2c_recv_byte ( basher ); + DBGC ( basher, "%02x ", *data ); + } + + DBGC ( basher, "%s\n", ( rc ? "failed" : "" ) ); + i2c_stop ( basher ); + close_bit ( basher ); + return rc; +} + +/** + * Write data to I2C device via bit-bashing interface + * + * @v i2c I2C interface + * @v i2cdev I2C device + * @v offset Starting offset within the device + * @v data Data buffer + * @v len Length of data buffer + * @ret rc Return status code + * + * Note that attempting to write zero bytes of data is a valid way to + * check for I2C device presence. + */ +static int i2c_bit_write ( struct i2c_interface *i2c, + struct i2c_device *i2cdev, unsigned int offset, + const uint8_t *data, unsigned int len ) { + struct i2c_bit_basher *i2cbit + = container_of ( i2c, struct i2c_bit_basher, i2c ); + struct bit_basher *basher = &i2cbit->basher; + int rc = 0; + + DBGC ( basher, "I2CBIT %p writing to device %x: ", + basher, i2cdev->dev_addr ); + + open_bit ( basher ); + + for ( ; ; data++, offset++ ) { + + /* Select device for writing */ + if ( ( rc = i2c_select ( basher, i2cdev, offset, + I2C_WRITE ) ) != 0 ) + break; + + /* Abort at end of data */ + if ( ! ( len-- ) ) + break; + + /* Select offset */ + if ( ( rc = i2c_send_byte ( basher, offset ) ) != 0 ) + break; + + /* Write data to device */ + DBGC ( basher, "%02x ", *data ); + if ( ( rc = i2c_send_byte ( basher, *data ) ) != 0 ) + break; + } + + DBGC ( basher, "%s\n", ( rc ? "failed" : "" ) ); + i2c_stop ( basher ); + close_bit ( basher ); + return rc; +} + +/** + * Initialise I2C bit-bashing interface + * + * @v i2cbit I2C bit-bashing interface + * @v bash_op Bit-basher operations + */ +int init_i2c_bit_basher ( struct i2c_bit_basher *i2cbit, + struct bit_basher_operations *bash_op ) { + struct bit_basher *basher = &i2cbit->basher; + int rc; + + /* Initialise data structures */ + basher->op = bash_op; + assert ( basher->op->read != NULL ); + assert ( basher->op->write != NULL ); + i2cbit->i2c.read = i2c_bit_read; + i2cbit->i2c.write = i2c_bit_write; + + /* Reset I2C bus */ + if ( ( rc = i2c_reset ( basher ) ) != 0 ) { + DBGC ( basher, "I2CBIT %p could not reset I2C bus: %s\n", + basher, strerror ( rc ) ); + return rc; + } + + return 0; +} diff --git a/qemu/roms/ipxe/src/drivers/bitbash/spi_bit.c b/qemu/roms/ipxe/src/drivers/bitbash/spi_bit.c new file mode 100644 index 000000000..1b39d72fa --- /dev/null +++ b/qemu/roms/ipxe/src/drivers/bitbash/spi_bit.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +FILE_LICENCE ( GPL2_OR_LATER ); + +#include <stddef.h> +#include <stdint.h> +#include <string.h> +#include <byteswap.h> +#include <errno.h> +#include <assert.h> +#include <unistd.h> +#include <ipxe/bitbash.h> +#include <ipxe/spi_bit.h> + +/** @file + * + * SPI bit-bashing interface + * + */ + +/** Delay between SCLK changes and around SS changes */ +static void spi_bit_delay ( void ) { + udelay ( SPI_BIT_UDELAY ); +} + +/** Chip select line will be asserted */ +#define SELECT_SLAVE 0 + +/** Chip select line will be deasserted */ +#define DESELECT_SLAVE SPI_MODE_SSPOL + +/** + * Select/deselect slave + * + * @v spibit SPI bit-bashing interface + * @v slave Slave number + * @v state Slave select state + * + * @c state must be @c SELECT_SLAVE or @c DESELECT_SLAVE. + */ +static void spi_bit_set_slave_select ( struct spi_bit_basher *spibit, + unsigned int slave, + unsigned int state ) { + struct bit_basher *basher = &spibit->basher; + + state ^= ( spibit->bus.mode & SPI_MODE_SSPOL ); + DBGC2 ( spibit, "SPIBIT %p setting slave %d select %s\n", + spibit, slave, ( state ? "high" : "low" ) ); + + spi_bit_delay(); + write_bit ( basher, SPI_BIT_SS ( slave ), state ); + spi_bit_delay(); +} + +/** + * Transfer bits over SPI bit-bashing bus + * + * @v bus SPI bus + * @v data_out TX data buffer (or NULL) + * @v data_in RX data buffer (or NULL) + * @v len Length of transfer (in @b bits) + * @v endianness Endianness of this data transfer + * + * This issues @c len clock cycles on the SPI bus, shifting out data + * from the @c data_out buffer to the MOSI line and shifting in data + * from the MISO line to the @c data_in buffer. If @c data_out is + * NULL, then the data sent will be all zeroes. If @c data_in is + * NULL, then the incoming data will be discarded. + */ +static void spi_bit_transfer ( struct spi_bit_basher *spibit, + const void *data_out, void *data_in, + unsigned int len, int endianness ) { + struct spi_bus *bus = &spibit->bus; + struct bit_basher *basher = &spibit->basher; + unsigned int sclk = ( ( bus->mode & SPI_MODE_CPOL ) ? 1 : 0 ); + unsigned int cpha = ( ( bus->mode & SPI_MODE_CPHA ) ? 1 : 0 ); + unsigned int bit_offset; + unsigned int byte_offset; + unsigned int byte_mask; + unsigned int bit; + unsigned int step; + + DBGC2 ( spibit, "SPIBIT %p transferring %d bits in mode %#x\n", + spibit, len, bus->mode ); + + for ( step = 0 ; step < ( len * 2 ) ; step++ ) { + /* Calculate byte offset and byte mask */ + bit_offset = ( ( endianness == SPI_BIT_BIG_ENDIAN ) ? + ( len - ( step / 2 ) - 1 ) : ( step / 2 ) ); + byte_offset = ( bit_offset / 8 ); + byte_mask = ( 1 << ( bit_offset % 8 ) ); + + /* Shift data in or out */ + if ( sclk == cpha ) { + const uint8_t *byte; + + /* Shift data out */ + if ( data_out ) { + byte = ( data_out + byte_offset ); + bit = ( *byte & byte_mask ); + DBGCP ( spibit, "SPIBIT %p wrote bit %d\n", + spibit, ( bit ? 1 : 0 ) ); + } else { + bit = 0; + } + write_bit ( basher, SPI_BIT_MOSI, bit ); + } else { + uint8_t *byte; + + /* Shift data in */ + bit = read_bit ( basher, SPI_BIT_MISO ); + if ( data_in ) { + DBGCP ( spibit, "SPIBIT %p read bit %d\n", + spibit, ( bit ? 1 : 0 ) ); + byte = ( data_in + byte_offset ); + *byte &= ~byte_mask; + *byte |= ( bit & byte_mask ); + } + } + + /* Toggle clock line */ + spi_bit_delay(); + sclk ^= 1; + write_bit ( basher, SPI_BIT_SCLK, sclk ); + } +} + +/** + * Read/write data via SPI bit-bashing bus + * + * @v bus SPI bus + * @v device SPI device + * @v command Command + * @v address Address to read/write (<0 for no address) + * @v data_out TX data buffer (or NULL) + * @v data_in RX data buffer (or NULL) + * @v len Length of transfer + * @ret rc Return status code + */ +static int spi_bit_rw ( struct spi_bus *bus, struct spi_device *device, + unsigned int command, int address, + const void *data_out, void *data_in, size_t len ) { + struct spi_bit_basher *spibit + = container_of ( bus, struct spi_bit_basher, bus ); + uint32_t tmp_command; + uint32_t tmp_address; + uint32_t tmp_address_detect; + + /* Open bit-bashing interface */ + open_bit ( &spibit->basher ); + + /* Deassert chip select to reset specified slave */ + spi_bit_set_slave_select ( spibit, device->slave, DESELECT_SLAVE ); + + /* Set clock line to idle state */ + write_bit ( &spibit->basher, SPI_BIT_SCLK, + ( bus->mode & SPI_MODE_CPOL ) ); + + /* Assert chip select on specified slave */ + spi_bit_set_slave_select ( spibit, device->slave, SELECT_SLAVE ); + + /* Transmit command */ + assert ( device->command_len <= ( 8 * sizeof ( tmp_command ) ) ); + tmp_command = cpu_to_le32 ( command ); + spi_bit_transfer ( spibit, &tmp_command, NULL, device->command_len, + SPI_BIT_BIG_ENDIAN ); + + /* Transmit address, if present */ + if ( address >= 0 ) { + assert ( device->address_len <= ( 8 * sizeof ( tmp_address ))); + tmp_address = cpu_to_le32 ( address ); + if ( device->address_len == SPI_AUTODETECT_ADDRESS_LEN ) { + /* Autodetect address length. This relies on + * the device responding with a dummy zero + * data bit before the first real data bit. + */ + DBGC ( spibit, "SPIBIT %p autodetecting device " + "address length\n", spibit ); + assert ( address == 0 ); + device->address_len = 0; + do { + spi_bit_transfer ( spibit, &tmp_address, + &tmp_address_detect, 1, + SPI_BIT_BIG_ENDIAN ); + device->address_len++; + } while ( le32_to_cpu ( tmp_address_detect ) & 1 ); + DBGC ( spibit, "SPIBIT %p autodetected device address " + "length %d\n", spibit, device->address_len ); + } else { + spi_bit_transfer ( spibit, &tmp_address, NULL, + device->address_len, + SPI_BIT_BIG_ENDIAN ); + } + } + + /* Transmit/receive data */ + spi_bit_transfer ( spibit, data_out, data_in, ( len * 8 ), + spibit->endianness ); + + /* Deassert chip select on specified slave */ + spi_bit_set_slave_select ( spibit, device->slave, DESELECT_SLAVE ); + + /* Close bit-bashing interface */ + close_bit ( &spibit->basher ); + + return 0; +} + +/** + * Initialise SPI bit-bashing interface + * + * @v spibit SPI bit-bashing interface + */ +void init_spi_bit_basher ( struct spi_bit_basher *spibit ) { + assert ( &spibit->basher.op->read != NULL ); + assert ( &spibit->basher.op->write != NULL ); + spibit->bus.rw = spi_bit_rw; +} |