diff options
Diffstat (limited to 'kernel/Documentation/devicetree/bindings/timer')
9 files changed, 186 insertions, 1 deletions
diff --git a/kernel/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/kernel/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt index 993695c65..eeee6cd51 100644 --- a/kernel/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt +++ b/kernel/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt @@ -6,6 +6,9 @@ Required properties: - interrupts : A list of 3 interrupts; one per timer channel. - clocks: phandle to the source clock +Optional properties: +- timer-width: Bit width of the timer, necessary if not 16. + Example: ttc0: ttc0@f8001000 { @@ -14,4 +17,5 @@ ttc0: ttc0@f8001000 { compatible = "cdns,ttc"; reg = <0xF8001000 0x1000>; clocks = <&cpu_clk 3>; + timer-width = <32>; }; diff --git a/kernel/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt b/kernel/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt new file mode 100644 index 000000000..7afce80bf --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt @@ -0,0 +1,28 @@ +* Pistachio general-purpose timer based clocksource + +Required properties: + - compatible: "img,pistachio-gptimer". + - reg: Address range of the timer registers. + - interrupts: An interrupt for each of the four timers + - clocks: Should contain a clock specifier for each entry in clock-names + - clock-names: Should contain the following entries: + "sys", interface clock + "slow", slow counter clock + "fast", fast counter clock + - img,cr-periph: Must contain a phandle to the peripheral control + syscon node. + +Example: + timer: timer@18102000 { + compatible = "img,pistachio-gptimer"; + reg = <0x18102000 0x100>; + interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, + <&clk_periph PERIPH_CLK_COUNTER_SLOW>, + <&cr_periph SYS_CLK_TIMER>; + clock-names = "fast", "slow", "sys"; + img,cr-periph = <&cr_periph>; + }; diff --git a/kernel/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/kernel/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 7c4408ff4..64083bc56 100644 --- a/kernel/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/kernel/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -2,7 +2,13 @@ Mediatek MT6577, MT6572 and MT6589 Timers --------------------------------------- Required properties: -- compatible: Should be "mediatek,mt6577-timer" +- compatible should contain: + * "mediatek,mt6580-timer" for MT6580 compatible timers + * "mediatek,mt6589-timer" for MT6589 compatible timers + * "mediatek,mt8127-timer" for MT8127 compatible timers + * "mediatek,mt8135-timer" for MT8135 compatible timers + * "mediatek,mt8173-timer" for MT8173 compatible timers + * "mediatek,mt6577-timer" for MT6577 and all above compatible timers - reg: Should contain location and length for timers register. - clocks: Clocks driving the timer hardware. This list should include two clocks. The order is system clock and as second clock the RTC clock. diff --git a/kernel/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt b/kernel/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt new file mode 100644 index 000000000..51b05a0e7 --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt @@ -0,0 +1,26 @@ +* NXP LPC3220 timer + +The NXP LPC3220 timer is used on a wide range of NXP SoCs. This +includes LPC32xx, LPC178x, LPC18xx and LPC43xx parts. + +Required properties: +- compatible: + Should be "nxp,lpc3220-timer". +- reg: + Address and length of the register set. +- interrupts: + Reference to the timer interrupt +- clocks: + Should contain a reference to timer clock. +- clock-names: + Should contain "timerclk". + +Example: + +timer1: timer@40085000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40085000 0x1000>; + interrupts = <13>; + clocks = <&ccu1 CLK_CPU_TIMER1>; + clock-names = "timerclk"; +}; diff --git a/kernel/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt b/kernel/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt new file mode 100644 index 000000000..e8792447a --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt @@ -0,0 +1,25 @@ +* Renesas H8/300 16bit timer + +The 16bit timer is a 16bit timer/counter with configurable clock inputs and +programmable compare match. + +Required Properties: + + - compatible: must contain "renesas,16bit-timer" + - reg: base address and length of the registers block for the timer module. + - interrupts: interrupt-specifier for the timer, IMIA + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "peripheral_clk" for the functional clock. + - renesas,channel: timer channel number. + +Example: + + timer16: timer@ffff68 { + compatible = "reneas,16bit-timer"; + reg = <0xffff68 8>, <0xffff60 8>; + interrupts = <24>; + renesas,channel = <0>; + clocks = <&pclk>; + clock-names = "peripheral_clk"; + }; + diff --git a/kernel/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt b/kernel/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt new file mode 100644 index 000000000..9dca3759a --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt @@ -0,0 +1,25 @@ +* Renesas H8/300 8bit timer + +The 8bit timer is a 8bit timer/counter with configurable clock inputs and +programmable compare match. + +This implement only supported cascade mode. + +Required Properties: + + - compatible: must contain "renesas,8bit-timer" + - reg: base address and length of the registers block for the timer module. + - interrupts: interrupt-specifier for the timer, CMIA and TOVI + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "fck" for the functional clock. + +Example: + + timer8_0: timer@ffff80 { + compatible = "renesas,8bit-timer"; + reg = <0xffff80 10>; + interrupts = <36>; + clocks = <&fclk>; + clock-names = "fck"; + }; + diff --git a/kernel/Documentation/devicetree/bindings/timer/renesas,tpu.txt b/kernel/Documentation/devicetree/bindings/timer/renesas,tpu.txt new file mode 100644 index 000000000..f8b25897f --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/timer/renesas,tpu.txt @@ -0,0 +1,21 @@ +* Renesas H8/300 Timer Pluse Unit + +The TPU is a 16bit timer/counter with configurable clock inputs and +programmable compare match. +This implementation support only cascade mode. + +Required Properties: + + - compatible: must contain "renesas,tpu" + - reg: base address and length of the registers block in 2 channel. + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "peripheral_clk" for the functional clock. + + +Example: + tpu: tpu@ffffe0 { + compatible = "renesas,tpu"; + reg = <0xffffe0 16>, <0xfffff0 12>; + clocks = <&pclk>; + clock-names = "peripheral_clk"; + }; diff --git a/kernel/Documentation/devicetree/bindings/timer/st,stih407-lpc b/kernel/Documentation/devicetree/bindings/timer/st,stih407-lpc new file mode 100644 index 000000000..72acb487b --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/timer/st,stih407-lpc @@ -0,0 +1,28 @@ +STMicroelectronics Low Power Controller (LPC) - Clocksource +=========================================================== + +LPC currently supports Watchdog OR Real Time Clock OR Clocksource +functionality. + +[See: ../watchdog/st_lpc_wdt.txt for Watchdog options] +[See: ../rtc/rtc-st-lpc.txt for RTC options] + +Required properties + +- compatible : Must be: "st,stih407-lpc" +- reg : LPC registers base address + size +- interrupts : LPC interrupt line number and associated flags +- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) +- st,lpc-mode : The LPC can run either one of three modes: + ST_LPC_MODE_RTC [0] + ST_LPC_MODE_WDT [1] + ST_LPC_MODE_CLKSRC [2] + One (and only one) mode must be selected. + +Example: + lpc@fde05000 { + compatible = "st,stih407-lpc"; + reg = <0xfde05000 0x1000>; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + st,lpc-mode = <ST_LPC_MODE_CLKSRC>; + }; diff --git a/kernel/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/kernel/Documentation/devicetree/bindings/timer/st,stm32-timer.txt new file mode 100644 index 000000000..8ef28e70d --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/timer/st,stm32-timer.txt @@ -0,0 +1,22 @@ +. STMicroelectronics STM32 timer + +The STM32 MCUs family has several general-purpose 16 and 32 bits timers. + +Required properties: +- compatible : Should be "st,stm32-timer" +- reg : Address and length of the register set +- clocks : Reference on the timer input clock +- interrupts : Reference to the timer interrupt + +Optional properties: +- resets: Reference to a reset controller asserting the timer + +Example: + +timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&rrc 259>; + clocks = <&clk_pmtr1>; +}; |