summaryrefslogtreecommitdiffstats
path: root/qemu/tests/tcg/mips/mips64-dspr2/shrav_ob.c
diff options
context:
space:
mode:
authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/mips/mips64-dspr2/shrav_ob.c
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/mips/mips64-dspr2/shrav_ob.c')
-rw-r--r--qemu/tests/tcg/mips/mips64-dspr2/shrav_ob.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/qemu/tests/tcg/mips/mips64-dspr2/shrav_ob.c b/qemu/tests/tcg/mips/mips64-dspr2/shrav_ob.c
new file mode 100644
index 000000000..fbdfbab35
--- /dev/null
+++ b/qemu/tests/tcg/mips/mips64-dspr2/shrav_ob.c
@@ -0,0 +1,22 @@
+#include "io.h"
+
+int main(void)
+{
+ long long rd, rt, rs;
+ long long res;
+
+ rt = 0x1234567887654321;
+ rs = 0x4;
+ res = 0xf1f3f5f7f8060402;
+
+ asm ("shrav.ob %0, %1, %2"
+ : "=r"(rd)
+ : "r"(rt), "r"(rs)
+ );
+
+ if (rd != res) {
+ printf("shra.ob error\n");
+ return -1;
+ }
+ return 0;
+}