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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c')
-rw-r--r--qemu/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c51
1 files changed, 51 insertions, 0 deletions
diff --git a/qemu/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c b/qemu/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c
new file mode 100644
index 000000000..7660f037d
--- /dev/null
+++ b/qemu/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c
@@ -0,0 +1,51 @@
+#include "io.h"
+
+int main(void)
+{
+ long long rs, rt;
+ long long ach = 5, acl = 5;
+ long long resulth, resultl;
+
+ rs = 0xBC0123AD;
+ rt = 0x01643721;
+ resulth = 0x04;
+ resultl = 0xFFFFFFFFEE9794A3;
+ __asm
+ ("mthi %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
+ "dpsq_s.w.ph $ac1, %2, %3\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ : "+r"(ach), "+r"(acl)
+ : "r"(rs), "r"(rt)
+ );
+ if ((ach != resulth) || (acl != resultl)) {
+ printf("1 dpsq_s.w.ph wrong\n");
+
+ return -1;
+ }
+
+ ach = 0x1424Ef1f;
+ acl = 0x1035219A;
+ rs = 0x800083AD;
+ rt = 0x80003721;
+ resulth = 0x1424ef1e;
+ resultl = 0x577ed901;
+
+ __asm
+ ("mthi %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
+ "dpsq_s.w.ph $ac1, %2, %3\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ : "+r"(ach), "+r"(acl)
+ : "r"(rs), "r"(rt)
+ );
+ if ((ach != resulth) || (acl != resultl)) {
+ printf("2 dpsq_s.w.ph wrong\n");
+
+ return -1;
+ }
+
+ return 0;
+}