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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c')
-rw-r--r--qemu/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c55
1 files changed, 55 insertions, 0 deletions
diff --git a/qemu/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c b/qemu/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c
new file mode 100644
index 000000000..d83dce6f3
--- /dev/null
+++ b/qemu/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c
@@ -0,0 +1,55 @@
+#include<stdio.h>
+#include<assert.h>
+
+int main()
+{
+ int rt, rs;
+ int achi, acli;
+ int dsp;
+ int acho, aclo;
+ int resulth, resultl;
+ int resdsp;
+
+ achi = 0x00000000;
+ acli = 0x0000B4CB;
+ rs = 0xFF060000;
+ rt = 0xCB000000;
+ resulth = 0x00000000;
+ resultl = 0x006838CB;
+
+ __asm
+ ("mthi %2, $ac1\n\t"
+ "mtlo %3, $ac1\n\t"
+ "maq_sa.w.phl $ac1, %4, %5\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ : "=r"(acho), "=r"(aclo)
+ : "r"(achi), "r"(acli), "r"(rs), "r"(rt)
+ );
+ assert(resulth == acho);
+ assert(resultl == aclo);
+
+ achi = 0x00000000;
+ acli = 0x0000B4CB;
+ rs = 0x80000000;
+ rt = 0x80000000;
+ resulth = 0x00;
+ resultl = 0x7fffffff;
+ resdsp = 0x01;
+
+ __asm
+ ("mthi %3, $ac1\n\t"
+ "mtlo %4, $ac1\n\t"
+ "maq_sa.w.phl $ac1, %5, %6\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ "rddsp %2\n\t"
+ : "=r"(acho), "=r"(aclo), "=r"(dsp)
+ : "r"(achi), "r"(acli), "r"(rs), "r"(rt)
+ );
+ assert(resulth == acho);
+ assert(resultl == aclo);
+ assert(((dsp >> 17) & 0x01) == 0x01);
+
+ return 0;
+}