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| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/lm32/test_sw.S | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/lm32/test_sw.S')
| -rw-r--r-- | qemu/tests/tcg/lm32/test_sw.S | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/qemu/tests/tcg/lm32/test_sw.S b/qemu/tests/tcg/lm32/test_sw.S new file mode 100644 index 000000000..2b1c017e7 --- /dev/null +++ b/qemu/tests/tcg/lm32/test_sw.S @@ -0,0 +1,38 @@ +.include "macros.inc" + +start + +test_name SW_1 +load r1 data +load r2 0xaabbccdd +sw (r1+0), r2 +check_mem data 0xaabbccdd + +test_name SW_2 +load r1 data +load r2 0x00112233 +sw (r1+4), r2 +check_mem data1 0x00112233 + +test_name SW_3 +load r1 data +load r2 0x44556677 +sw (r1+-4), r2 +check_mem data0 0x44556677 + +test_name SW_4 +load r1 data +sw (r1+0), r1 +lw r3, (r1+0) +check_r3 data + +end + +.data + .align 4 +data0: + .byte 0, 0, 0, 0 +data: + .byte 0, 0, 0, 0 +data1: + .byte 0, 0, 0, 0 |