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| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/cris/check_scc.s | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/cris/check_scc.s')
| -rw-r--r-- | qemu/tests/tcg/cris/check_scc.s | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/qemu/tests/tcg/cris/check_scc.s b/qemu/tests/tcg/cris/check_scc.s new file mode 100644 index 000000000..4a8674cc1 --- /dev/null +++ b/qemu/tests/tcg/cris/check_scc.s @@ -0,0 +1,95 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n + + .include "testutils.inc" + + .macro lcheckr3 v + move $ccs, $r9 + checkr3 \v + move $r9, $ccs + .endm + + start + clearf nzvc + scc r3 + lcheckr3 1 + scs r3 + lcheckr3 0 + sne r3 + lcheckr3 1 + seq r3 + lcheckr3 0 + svc r3 + lcheckr3 1 + svs r3 + lcheckr3 0 + spl r3 + lcheckr3 1 + smi r3 + lcheckr3 0 + sls r3 + lcheckr3 0 + shi r3 + lcheckr3 1 + sge r3 + lcheckr3 1 + slt r3 + lcheckr3 0 + sgt r3 + lcheckr3 1 + sle r3 + lcheckr3 0 + sa r3 + lcheckr3 1 + setf nzvc + scc r3 + lcheckr3 0 + scs r3 + lcheckr3 1 + sne r3 + lcheckr3 0 + svc r3 + lcheckr3 0 + svs r3 + lcheckr3 1 + spl r3 + lcheckr3 0 + smi r3 + lcheckr3 1 + sls r3 + lcheckr3 1 + shi r3 + lcheckr3 0 + sge r3 + lcheckr3 1 + slt r3 + lcheckr3 0 + sgt r3 + lcheckr3 0 + sle r3 + lcheckr3 1 + sa r3 + lcheckr3 1 + clearf n + sge r3 + lcheckr3 0 + slt r3 + lcheckr3 1 + + .if 1 ;..asm.arch.cris.v32 + setf p + ssb r3 + .else + moveq 1,r3 + .endif + lcheckr3 1 + + .if 1 ;..asm.arch.cris.v32 + clearf p + ssb r3 + .else + moveq 0,r3 + .endif + lcheckr3 0 + + quit |