Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

1 files changed, 0 insertions, 55 deletions

diff --git a/qemu/target-s390x/insn-format.def b/qemu/target-s390x/insn-format.def
deleted file mode 100644
index 0e898b90b..000000000
--- a/qemu/target-s390x/insn-format.def
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Description of s390 insn formats.  */
-/* NAME   F1,          F2... */
-F0(E)
-F1(I,     I(1, 8, 8))
-F2(RI_a,  R(1, 8),     I(2,16,16))
-F2(RI_b,  R(1, 8),     I(2,16,16))
-F2(RI_c,  M(1, 8),     I(2,16,16))
-F3(RIE_a, R(1, 8),     I(2,16,16),  M(3,32))
-F4(RIE_b, R(1, 8),     R(2,12),     M(3,32),   I(4,16,16))
-F4(RIE_c, R(1, 8),     I(2,32, 8),  M(3,12),   I(4,16,16))
-F3(RIE_d, R(1, 8),     I(2,16,16),  R(3,12))
-F3(RIE_e, R(1, 8),     I(2,16,16),  R(3,12))
-F5(RIE_f, R(1, 8),     R(2,12),     I(3,16,8), I(4,24,8),  I(5,32,8))
-F2(RIL_a, R(1, 8),     I(2,16,32))
-F2(RIL_b, R(1, 8),     I(2,16,32))
-F2(RIL_c, M(1, 8),     I(2,16,32))
-F4(RIS,   R(1, 8),     I(2,32, 8),  M(3,12),   BD(4,16,20))
-/* ??? The PoO does not call out subtypes _a and _b for RR, as it does
-   for e.g. RX.  Our checking requires this for e.g. BCR.  */
-F2(RR_a,  R(1, 8),     R(2,12))
-F2(RR_b,  M(1, 8),     R(2,12))
-F2(RRE,   R(1,24),     R(2,28))
-F3(RRD,   R(1,16),     R(2,28),     R(3,24))
-F4(RRF_a, R(1,24),     R(2,28),     R(3,16),   M(4,20))
-F4(RRF_b, R(1,24),     R(2,28),     R(3,16),   M(4,20))
-F4(RRF_c, R(1,24),     R(2,28),     M(3,16),   M(4,20))
-F4(RRF_d, R(1,24),     R(2,28),     M(3,16),   M(4,20))
-F4(RRF_e, R(1,24),     R(2,28),     M(3,16),   M(4,20))
-F4(RRS,   R(1, 8),     R(2,12),     M(3,32),   BD(4,16,20))
-F3(RS_a,  R(1, 8),     BD(2,16,20), R(3,12))
-F3(RS_b,  R(1, 8),     BD(2,16,20), M(3,12))
-F3(RSI,   R(1, 8),     I(2,16,16),  R(3,12))
-F2(RSL,   L(1, 8, 4),  BD(1,16,20))
-F3(RSY_a, R(1, 8),     BDL(2),      R(3,12))
-F3(RSY_b, R(1, 8),     BDL(2),      M(3,12))
-F2(RX_a,  R(1, 8),     BXD(2))
-F2(RX_b,  M(1, 8),     BXD(2))
-F2(RXE,   R(1, 8),     BXD(2))
-F3(RXF,   R(1,32),     BXD(2),      R(3, 8))
-F2(RXY_a, R(1, 8),     BXDL(2))
-F2(RXY_b, M(1, 8),     BXDL(2))
-F1(S,     BD(2,16,20))
-F2(SI,    BD(1,16,20), I(2,8,8))
-F2(SIL,   BD(1,16,20), I(2,32,16))
-F2(SIY,   BDL(1),      I(2, 8, 8))
-F3(SS_a,  L(1, 8, 8),  BD(1,16,20), BD(2,32,36))
-F4(SS_b,  L(1, 8, 4),  BD(1,16,20), L(2,12,4),   BD(2,32,36))
-F4(SS_c,  L(1, 8, 4),  BD(1,16,20), BD(2,32,36), I(3,12, 4))
-/* ??? Odd man out.  The L1 field here is really a register, but the
-   easy way to compress the fields has R1 and B1 overlap.  */
-F4(SS_d,  L(1, 8, 4),  BD(1,16,20), BD(2,32,36), R(3,12))
-F4(SS_e,  R(1, 8),     BD(2,16,20), R(3,12),     BD(4,32,36))
-F3(SS_f,  BD(1,16,20), L(2,8,8),    BD(2,32,36))
-F2(SSE,   BD(1,16,20), BD(2,32,36))
-F3(SSF,   BD(1,16,20), BD(2,32,36), R(3,8))