Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

1 files changed, 375 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/include/configs/v37.h b/qemu/roms/u-boot/include/configs/v37.h
new file mode 100644
index 000000000..0d01fe207
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/v37.h
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_V37		1	/* ...on a Marel V37 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_LCD
+#define CONFIG_MPC8XX_LCD
+#define CONFIG_SHARP_LQ084V1DG21
+#undef CONFIG_LCD_LOGO
+
+/*-----------------------------------------------------------------------------
+ * I2C Configuration
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_I2C              1
+#define CONFIG_SYS_I2C_SLAVE           0x2
+
+#define	CONFIG_8xx_CONS_SMC1	1
+#undef	CONFIG_8xx_CONS_SMC2		/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; "								\
+	"setenv bootargs console=tty0 "                                   \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "			\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_CAN_DRIVER	1	/* CAN Driver support enabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DATE
+
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor1=v37-1"
+#define MTDPARTS_DEFAULT	"mtdparts=v37-1:-(jffs2)"
+*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE0		0x40000000
+#define CONFIG_SYS_FLASH_BASE1		0x60000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH_BASE1
+
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE0
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_NVRAM	1
+#define	CONFIG_ENV_ADDR		0x80000000/* Address of Environment */
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+#define CONFIG_ENV_OFFSET		0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	0xFFFFFF88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
+/*
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
+*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_PLPRCR	( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+#define CONFIG_SYS_OR_TIMING_FLASH	0xF56
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+#define CONFIG_SYS_OR5_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR5_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
+
+/*
+ * BR1 and OR1 (Battery backed SRAM)
+ */
+#define	CONFIG_SYS_BR1_PRELIM	0x80000401
+#define CONFIG_SYS_OR1_PRELIM	0xFFC00736
+
+/*
+ * BR2 and OR2 (SDRAM)
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB */
+
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* Marel V37 mem setting */
+
+#define	CONFIG_SYS_BR3_CAN	0xC0000401
+#define CONFIG_SYS_OR3_CAN	0xFFFF0724
+
+/*
+#define	CONFIG_SYS_BR3_PRELIM	0xFA400001
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
+#define	CONFIG_SYS_BR4_PRELIM	0xFA000401
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
+*/
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV16
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 10 column SDRAM */
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
+			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
+
+#endif	/* __CONFIG_H */