diff options
author | 2015-08-28 09:58:54 +0800 | |
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committer | 2015-09-01 12:44:00 +0800 | |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/drivers/watchdog/xilinx_tb_wdt.c | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/drivers/watchdog/xilinx_tb_wdt.c')
-rw-r--r-- | qemu/roms/u-boot/drivers/watchdog/xilinx_tb_wdt.c | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/drivers/watchdog/xilinx_tb_wdt.c b/qemu/roms/u-boot/drivers/watchdog/xilinx_tb_wdt.c new file mode 100644 index 000000000..6336c9488 --- /dev/null +++ b/qemu/roms/u-boot/drivers/watchdog/xilinx_tb_wdt.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2011-2013 Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/microblaze_intc.h> +#include <asm/processor.h> +#include <watchdog.h> + +#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */ +#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */ +#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/ +#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */ + +struct watchdog_regs { + u32 twcsr0; /* 0x0 */ + u32 twcsr1; /* 0x4 */ + u32 tbr; /* 0x8 */ +}; + +static struct watchdog_regs *watchdog_base = + (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR; + +void hw_watchdog_reset(void) +{ + u32 reg; + + /* Read the current contents of TCSR0 */ + reg = readl(&watchdog_base->twcsr0); + + /* Clear the watchdog WDS bit */ + if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK)) + writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0); +} + +void hw_watchdog_disable(void) +{ + u32 reg; + + /* Read the current contents of TCSR0 */ + reg = readl(&watchdog_base->twcsr0); + + writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0); + writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); + + puts("Watchdog disabled!\n"); +} + +static void hw_watchdog_isr(void *arg) +{ + hw_watchdog_reset(); +} + +void hw_watchdog_init(void) +{ + int ret; + + writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK), + &watchdog_base->twcsr0); + writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); + + ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ, + hw_watchdog_isr, NULL); + if (ret) + puts("Watchdog IRQ registration failed."); +} |