diff options
author | Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
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committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/common/cmd_mp.c | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/common/cmd_mp.c')
-rw-r--r-- | qemu/roms/u-boot/common/cmd_mp.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/common/cmd_mp.c b/qemu/roms/u-boot/common/cmd_mp.c new file mode 100644 index 000000000..328b33806 --- /dev/null +++ b/qemu/roms/u-boot/common/cmd_mp.c @@ -0,0 +1,73 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> + +static int +cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned long cpuid; + + if (argc < 3) + return CMD_RET_USAGE; + + cpuid = simple_strtoul(argv[1], NULL, 10); + if (!is_core_valid(cpuid)) { + printf ("Core num: %lu is not valid\n", cpuid); + return 1; + } + + + if (argc == 3) { + if (strncmp(argv[2], "reset", 5) == 0) + cpu_reset(cpuid); + else if (strncmp(argv[2], "status", 6) == 0) + cpu_status(cpuid); + else if (strncmp(argv[2], "disable", 7) == 0) + return cpu_disable(cpuid); + else + return CMD_RET_USAGE; + + return 0; + } + + /* 4 or greater, make sure its release */ + if (strncmp(argv[2], "release", 7) != 0) + return CMD_RET_USAGE; + + if (cpu_release(cpuid, argc - 3, argv + 3)) + return CMD_RET_USAGE; + + return 0; +} + +#ifdef CONFIG_SYS_LONGHELP +static char cpu_help_text[] = + "<num> reset - Reset cpu <num>\n" + "cpu <num> status - Status of cpu <num>\n" + "cpu <num> disable - Disable cpu <num>\n" + "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]" +#ifdef CONFIG_PPC + "\n" + " [args] : <pir> <r3> <r6>\n" \ + " pir - processor id (if writeable)\n" \ + " r3 - value for gpr 3\n" \ + " r6 - value for gpr 6\n" \ + "\n" \ + " Use '-' for any arg if you want the default value.\n" \ + " Default for r3 is <num> and r6 is 0\n" \ + "\n" \ + " When cpu <num> is released r4 and r5 = 0.\n" \ + " r7 will contain the size of the initial mapped area" +#endif + ""; +#endif + +U_BOOT_CMD( + cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd, + "Multiprocessor CPU boot manipulation and release", cpu_help_text +); |