Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

5 files changed, 0 insertions, 336 deletions

diff --git a/qemu/roms/u-boot/board/xes/xpedite550x/Makefile b/qemu/roms/u-boot/board/xes/xpedite550x/Makefile
deleted file mode 100644
index 1a3fe7635..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite550x/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2007-2008 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= xpedite550x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/qemu/roms/u-boot/board/xes/xpedite550x/ddr.c b/qemu/roms/u-boot/board/xes/xpedite550x/ddr.c
deleted file mode 100644
index 0c0605e3a..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite550x/ddr.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		 sizeof(ddr3_spd_eeprom_t));
-}
-
-/*
- *     There are traditionally three board-specific SDRAM timing parameters
- *     which must be calculated based on the particular PCB artwork.  These are:
- *     1.) CPO (Read Capture Delay)
- *	       - TIMING_CFG_2 register
- *	       Source: Calculation based on board trace lengths and
- *		       chip-specific internal delays.
- *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *	       - DDR_SDRAM_CLK_CNTL register
- *	       Source: Signal Integrity Simulations
- *     3.) 2T Timing on Addr/Ctl
- *	       - TIMING_CFG_2 register
- *	       Source: Signal Integrity Simulations
- *	       Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     ====== XPedite550x DDR3-800 read delay calculations ======
- *
- *     The P2020 processor provides an autoleveling option. Setting CPO to
- *     0x1f enables this auto configuration.
- */
-
-typedef struct {
-	unsigned short datarate_mhz_low;
-	unsigned short datarate_mhz_high;
-	unsigned char clk_adjust;
-	unsigned char cpo;
-} board_specific_parameters_t;
-
-const board_specific_parameters_t board_specific_parameters[][20] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR3-600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo			= 31,
-		},
-		{
-			/* DDR3-800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo			= 31,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const board_specific_parameters_t *pbsp =
-				&(board_specific_parameters[ctrl_num][0]);
-	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
-				sizeof(board_specific_parameters[0][0]);
-	u32 i;
-	ulong ddr_freq;
-
-	/*
-	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
-	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
-	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
-	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
-	 */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i&1) {	/* odd CS */
-			popts->cs_local_opts[i].odt_rd_cfg = 0;
-			popts->cs_local_opts[i].odt_wr_cfg = 0;
-		} else {	/* even CS */
-			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-				popts->cs_local_opts[i].odt_rd_cfg = 0;
-				popts->cs_local_opts[i].odt_wr_cfg = 4;
-			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-				popts->cs_local_opts[i].odt_rd_cfg = 3;
-				popts->cs_local_opts[i].odt_wr_cfg = 3;
-			}
-		}
-	}
-
-	/*
-	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-
-	for (i = 0; i < num_params; i++) {
-		if (ddr_freq >= pbsp->datarate_mhz_low &&
-		    ddr_freq <= pbsp->datarate_mhz_high) {
-			popts->clk_adjust = pbsp->clk_adjust;
-			popts->cpo_override = pbsp->cpo;
-			popts->twot_en = 0;
-			break;
-		}
-		pbsp++;
-	}
-
-	if (i == num_params) {
-		printf("Warning: board specific timing not found "
-		"for data rate %lu MT/s!\n", ddr_freq);
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-
-	/*
-	 * Enable on-die termination.
-	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
-	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
-	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
-	 */
-	popts->rtt_override = 1;
-	popts->rtt_override_value = 3;
-}
diff --git a/qemu/roms/u-boot/board/xes/xpedite550x/law.c b/qemu/roms/u-boot/board/xes/xpedite550x/law.c
deleted file mode 100644
index 1a3e91b90..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite550x/law.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/qemu/roms/u-boot/board/xes/xpedite550x/tlb.c b/qemu/roms/u-boot/board/xes/xpedite550x/tlb.c
deleted file mode 100644
index 0bcb93069..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite550x/tlb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* W**G* - NOR flashes */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - NAND flash */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 2, BOOKE_PAGESZ_1M, 1),
-
-	/* **M** - Boot page for secondary processors */
-	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/qemu/roms/u-boot/board/xes/xpedite550x/xpedite550x.c b/qemu/roms/u-boot/board/xes/xpedite550x/xpedite550x.c
deleted file mode 100644
index e64d682af..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite550x/xpedite550x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void ft_board_pci_setup(void *blob, bd_t *bd);
-
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	/*
-	 * Remap NOR flash region to caching-inhibited
-	 * so that flash can be erased/programmed properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* Invalidate existing TLB entry for NOR flash */
-	disable_tlb(0);
-	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-}
-#endif