Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

6 files changed, 203 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/toradex/colibri_pxa270/Makefile b/qemu/roms/u-boot/board/toradex/colibri_pxa270/Makefile
new file mode 100644
index 000000000..57cfe9b78
--- /dev/null
+++ b/qemu/roms/u-boot/board/toradex/colibri_pxa270/Makefile
@@ -0,0 +1,9 @@
+#
+# Toradex Colibri PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= colibri_pxa270.o
diff --git a/qemu/roms/u-boot/board/toradex/colibri_pxa270/colibri_pxa270.c b/qemu/roms/u-boot/board/toradex/colibri_pxa270/colibri_pxa270.c
new file mode 100644
index 000000000..8d95e4d17
--- /dev/null
+++ b/qemu/roms/u-boot/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -0,0 +1,107 @@
+/*
+ * Toradex Colibri PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of vpac270 */
+	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	pxa2xx_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+#ifdef	CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (UHCHR & UHCHR_FSBIR)
+		;
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef	CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/board/toradex/colibri_t20-common/colibri_t20-common.c b/qemu/roms/u-boot/board/toradex/colibri_t20-common/colibri_t20-common.c
new file mode 100644
index 000000000..58a9916f0
--- /dev/null
+++ b/qemu/roms/u-boot/board/toradex/colibri_t20-common/colibri_t20-common.c
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+
+#include "colibri_t20-common.h"
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void colibri_t20_common_pin_mux_usb(void)
+{
+	/* module internal USB bus to connect ethernet chipset */
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+	/* ULPI reference clock output */
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+	/* PHY reset GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+	/* VBus GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_DTE);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+}
+#endif
diff --git a/qemu/roms/u-boot/board/toradex/colibri_t20-common/colibri_t20-common.h b/qemu/roms/u-boot/board/toradex/colibri_t20-common/colibri_t20-common.h
new file mode 100644
index 000000000..1fe53f607
--- /dev/null
+++ b/qemu/roms/u-boot/board/toradex/colibri_t20-common/colibri_t20-common.h
@@ -0,0 +1,7 @@
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void colibri_t20_common_pin_mux_usb(void);
diff --git a/qemu/roms/u-boot/board/toradex/colibri_t20_iris/Makefile b/qemu/roms/u-boot/board/toradex/colibri_t20_iris/Makefile
new file mode 100644
index 000000000..ebeac70ea
--- /dev/null
+++ b/qemu/roms/u-boot/board/toradex/colibri_t20_iris/Makefile
@@ -0,0 +1,9 @@
+#
+#  (C) Copyright 2012 Lucas Stach
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= ../../nvidia/common/board.o
+obj-y	+= ../colibri_t20-common/colibri_t20-common.o
+obj-y	+= colibri_t20_iris.o
diff --git a/qemu/roms/u-boot/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/qemu/roms/u-boot/board/toradex/colibri_t20_iris/colibri_t20_iris.c
new file mode 100644
index 000000000..49c74f34f
--- /dev/null
+++ b/qemu/roms/u-boot/board/toradex/colibri_t20_iris/colibri_t20_iris.c
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+
+#include "../colibri_t20-common/colibri_t20-common.h"
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+	colibri_t20_common_pin_mux_usb();
+
+	/* USB 1 aka Tegra USB port 3 VBus*/
+	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+	pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif