summaryrefslogtreecommitdiffstats
path: root/qemu/roms/u-boot/board/timll/devkit3250
diff options
context:
space:
mode:
authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/timll/devkit3250
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/timll/devkit3250')
-rw-r--r--qemu/roms/u-boot/board/timll/devkit3250/Makefile8
-rw-r--r--qemu/roms/u-boot/board/timll/devkit3250/devkit3250.c52
2 files changed, 60 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/timll/devkit3250/Makefile b/qemu/roms/u-boot/board/timll/devkit3250/Makefile
new file mode 100644
index 000000000..472298637
--- /dev/null
+++ b/qemu/roms/u-boot/board/timll/devkit3250/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := devkit3250.o
diff --git a/qemu/roms/u-boot/board/timll/devkit3250/devkit3250.c b/qemu/roms/u-boot/board/timll/devkit3250/devkit3250.c
new file mode 100644
index 000000000..6acc41689
--- /dev/null
+++ b/qemu/roms/u-boot/board/timll/devkit3250/devkit3250.c
@@ -0,0 +1,52 @@
+/*
+ * Embest/Timll DevKit3250 board support
+ *
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+
+int board_early_init_f(void)
+{
+ lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_SYS_FLASH_CFI
+ /* Use 16-bit memory interface for NOR Flash */
+ emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
+
+ /* Change the NOR timings to optimum value to get maximum bandwidth */
+ emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
+ emc->stat[0].waitoen = EMC_STAT_WAITOEN(1);
+ emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
+ emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
+ emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
+ emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}