Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

5 files changed, 0 insertions, 731 deletions

diff --git a/qemu/roms/u-boot/board/siemens/pxm2/Makefile b/qemu/roms/u-boot/board/siemens/pxm2/Makefile
deleted file mode 100644
index f15993216..000000000
--- a/qemu/roms/u-boot/board/siemens/pxm2/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Makefile
-#
-# (C) Copyright 2013 Siemens Schweiz AG
-# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# Based on:
-# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y	:= mux.o
-endif
-
-obj-y	+= board.o
-ifndef CONFIG_SPL_BUILD
-obj-y += ../common/factoryset.o
-endif
diff --git a/qemu/roms/u-boot/board/siemens/pxm2/board.c b/qemu/roms/u-boot/board/siemens/pxm2/board.c
deleted file mode 100644
index 98083d52c..000000000
--- a/qemu/roms/u-boot/board/siemens/pxm2/board.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * Board functions for TI AM335X based pxm2 board
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * u-boot:/board/ti/am335x/board.c
- *
- * Board functions for TI AM335X based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include "../../../drivers/video/da8xx-fb.h"
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <watchdog.h>
-#include "board.h"
-#include "../common/factoryset.h"
-#include "pmic.h"
-#include <nand.h>
-#include <bmp_layout.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-static void board_init_ddr(void)
-{
-struct emif_regs pxm2_ddr3_emif_reg_data = {
-	.sdram_config = 0x41805332,
-	.sdram_tim1 = 0x666b3c9,
-	.sdram_tim2 = 0x243631ca,
-	.sdram_tim3 = 0x33f,
-	.emif_ddr_phy_ctlr_1 = 0x100005,
-	.zq_config = 0,
-	.ref_ctrl = 0x81a,
-};
-
-struct ddr_data pxm2_ddr3_data = {
-	.datardsratio0 = 0x81204812,
-	.datawdsratio0 = 0,
-	.datafwsratio0 = 0x8020080,
-	.datawrsratio0 = 0x4010040,
-};
-
-struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
-	.cmd0csratio = 0x80,
-	.cmd0iclkout = 0,
-	.cmd1csratio = 0x80,
-	.cmd1iclkout = 0,
-	.cmd2csratio = 0x80,
-	.cmd2iclkout = 0,
-};
-
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= DXR2_IOCTRL_VAL,
-	.cm1ioctl		= DXR2_IOCTRL_VAL,
-	.cm2ioctl		= DXR2_IOCTRL_VAL,
-	.dt0ioctl		= DXR2_IOCTRL_VAL,
-	.dt1ioctl		= DXR2_IOCTRL_VAL,
-};
-
-	config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
-		   &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
-}
-
-/*
- * voltage switching for MPU frequency switching.
- * @module = mpu - 0, core - 1
- * @vddx_op_vol_sel = vdd voltage to set
- */
-
-#define MPU	0
-#define CORE	1
-
-int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
-{
-	uchar buf[4];
-	unsigned int reg_offset;
-
-	if (module == MPU)
-		reg_offset = PMIC_VDD1_OP_REG;
-	else
-		reg_offset = PMIC_VDD2_OP_REG;
-
-	/* Select VDDx OP   */
-	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
-		return 1;
-
-	buf[0] &= ~PMIC_OP_REG_CMD_MASK;
-
-	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
-		return 1;
-
-	/* Configure VDDx OP  Voltage */
-	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
-		return 1;
-
-	buf[0] &= ~PMIC_OP_REG_SEL_MASK;
-	buf[0] |= vddx_op_vol_sel;
-
-	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
-		return 1;
-
-	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
-		return 1;
-
-	if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
-		return 1;
-
-	return 0;
-}
-
-#define OSC     (V_OSCK/1000000)
-
-const struct dpll_params dpll_mpu_pxm2 = {
-		720, OSC-1, 1, -1, -1, -1, -1};
-
-void spl_siemens_board_init(void)
-{
-	uchar buf[4];
-	/*
-	 * pxm2 PMIC code.  All boards currently want an MPU voltage
-	 * of 1.2625V and CORE voltage of 1.1375V to operate at
-	 * 720MHz.
-	 */
-	if (i2c_probe(PMIC_CTRL_I2C_ADDR))
-		return;
-
-	/* VDD1/2 voltage selection register access by control i/f */
-	if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
-		return;
-
-	buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
-
-	if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
-		return;
-
-	/* Frequency switching for OPP 120 */
-	if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
-	    voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
-		printf("voltage update failed\n");
-	}
-}
-#endif /* if def CONFIG_SPL_BUILD */
-
-int read_eeprom(void)
-{
-	/* nothing ToDo here for this board */
-
-	return 0;
-}
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
-	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 0,
-		.phy_if		= PHY_INTERFACE_MODE_RMII,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_addr	= 1,
-		.phy_if		= PHY_INTERFACE_MODE_RMII,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 4,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
-
-#if defined(CONFIG_DRIVER_TI_CPSW) || \
-	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
-int board_eth_init(bd_t *bis)
-{
-	int n = 0;
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
-	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-#ifdef CONFIG_FACTORYSET
-	int rv;
-	if (!is_valid_ether_addr(factory_dat.mac))
-		printf("Error: no valid mac address\n");
-	else
-		eth_setenv_enetaddr("ethaddr", factory_dat.mac);
-#endif /* #ifdef CONFIG_FACTORYSET */
-
-	/* Set rgmii mode and enable rmii clock to be sourced from chip */
-	writel(RGMII_MODE_ENABLE , &cdev->miisel);
-
-	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
-		printf("Error %d registering CPSW switch\n", rv);
-	else
-		n += rv;
-#endif
-	return n;
-}
-#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
-
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-static struct da8xx_panel lcd_panels[] = {
-	/* AUO G156XW01 V1 */
-	[0] = {
-		.name = "AUO_G156XW01_V1",
-		.width = 1376,
-		.height = 768,
-		.hfp = 14,
-		.hbp = 64,
-		.hsw = 56,
-		.vfp = 1,
-		.vbp = 28,
-		.vsw = 3,
-		.pxl_clk = 60000000,
-		.invert_pxl_clk = 0,
-	},
-	/* AUO B101EVN06 V0 */
-	[1] = {
-		.name = "AUO_B101EVN06_V0",
-		.width = 1280,
-		.height = 800,
-		.hfp = 52,
-		.hbp = 84,
-		.hsw = 36,
-		.vfp = 3,
-		.vbp = 14,
-		.vsw = 6,
-		.pxl_clk = 60000000,
-		.invert_pxl_clk = 0,
-	},
-	/*
-	 * Settings from factoryset
-	 * stored in EEPROM
-	 */
-	[2] = {
-		.name = "factoryset",
-		.width = 0,
-		.height = 0,
-		.hfp = 0,
-		.hbp = 0,
-		.hsw = 0,
-		.vfp = 0,
-		.vbp = 0,
-		.vsw = 0,
-		.pxl_clk = 60000000,
-		.invert_pxl_clk = 0,
-	},
-};
-
-static const struct display_panel disp_panel = {
-	WVGA,
-	32,
-	16,
-	COLOR_ACTIVE,
-};
-
-static const struct lcd_ctrl_config lcd_cfg = {
-	&disp_panel,
-	.ac_bias		= 255,
-	.ac_bias_intrpt		= 0,
-	.dma_burst_sz		= 16,
-	.bpp			= 32,
-	.fdd			= 0x80,
-	.tft_alt_mode		= 0,
-	.stn_565_mode		= 0,
-	.mono_8bit_mode		= 0,
-	.invert_line_clock	= 1,
-	.invert_frm_clock	= 1,
-	.sync_edge		= 0,
-	.sync_ctrl		= 1,
-	.raster_order		= 0,
-};
-
-static int set_gpio(int gpio, int state)
-{
-	gpio_request(gpio, "temp");
-	gpio_direction_output(gpio, state);
-	gpio_set_value(gpio, state);
-	gpio_free(gpio);
-	return 0;
-}
-
-static int enable_backlight(void)
-{
-	set_gpio(BOARD_LCD_POWER, 1);
-	set_gpio(BOARD_BACK_LIGHT, 1);
-	set_gpio(BOARD_TOUCH_POWER, 1);
-	return 0;
-}
-
-static int enable_pwm(void)
-{
-	struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
-	struct pwmss_ecap_regs *ecap;
-	int ticks = PWM_TICKS;
-	int duty = PWM_DUTY;
-
-	ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
-	/* enable clock */
-	setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
-	/* TimeStam Counter register */
-	writel(0xdb9, &ecap->tsctr);
-	/* config period */
-	writel(ticks - 1, &ecap->cap3);
-	writel(ticks - 1, &ecap->cap1);
-	setbits_le16(&ecap->ecctl2,
-		     (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
-	/* config duty */
-	writel(duty, &ecap->cap2);
-	writel(duty, &ecap->cap4);
-	/* start */
-	setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
-	return 0;
-}
-
-static struct dpll_regs dpll_lcd_regs = {
-	.cm_clkmode_dpll = CM_WKUP + 0x98,
-	.cm_idlest_dpll = CM_WKUP + 0x48,
-	.cm_clksel_dpll = CM_WKUP + 0x54,
-};
-
-/* no console on this board */
-int board_cfb_skip(void)
-{
-	return 1;
-}
-
-#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
-#define PLL_GET_N(v) (v & 0x7f)
-
-static int get_clk(struct dpll_regs *dpll_regs)
-{
-	unsigned int val;
-	unsigned int m, n;
-	int f = 0;
-
-	val = readl(dpll_regs->cm_clksel_dpll);
-	m = PLL_GET_M(val);
-	n = PLL_GET_N(val);
-	f = (m * V_OSCK) / n;
-
-	return f;
-};
-
-int clk_get(int clk)
-{
-	return get_clk(&dpll_lcd_regs);
-};
-
-static int conf_disp_pll(int m, int n)
-{
-	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-	struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
-
-	u32 *const clk_domains[] = {
-		&cmper->lcdclkctrl,
-		0
-	};
-	u32 *const clk_modules_explicit_en[] = {
-		&cmper->lcdclkctrl,
-		&cmper->lcdcclkstctrl,
-		&cmper->epwmss0clkctrl,
-		0
-	};
-	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
-	writel(0x0, &cmdpll->clklcdcpixelclk);
-
-	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
-
-	return 0;
-}
-
-static int board_video_init(void)
-{
-	conf_disp_pll(24, 1);
-	if (factory_dat.pxm50)
-		da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
-	else
-		da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
-
-	enable_pwm();
-	enable_backlight();
-
-	return 0;
-}
-#endif
-#include "../common/board.c"
diff --git a/qemu/roms/u-boot/board/siemens/pxm2/board.h b/qemu/roms/u-boot/board/siemens/pxm2/board.h
deleted file mode 100644
index 03626129d..000000000
--- a/qemu/roms/u-boot/board/siemens/pxm2/board.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * board.h
- *
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * TI AM335x boards information header
- * u-boot:/board/ti/am335x/board.h
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(void);
-#endif
diff --git a/qemu/roms/u-boot/board/siemens/pxm2/mux.c b/qemu/roms/u-boot/board/siemens/pxm2/mux.c
deleted file mode 100644
index c64b0d23d..000000000
--- a/qemu/roms/u-boot/board/siemens/pxm2/mux.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * pinmux setup for siemens pxm2 board
- *
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * u-boot:/board/ti/am335x/mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
-	{OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_TXD */
-	{-1},
-};
-
-#ifdef CONFIG_NAND
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */
-	{OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN},	/* MCASP0_AHCLKX */
-	{-1},
-};
-#endif
-
-static struct module_pin_mux i2c0_pin_mux[] = {
-	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	{-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
-	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	{-1},
-};
-
-#ifndef CONFIG_NO_ETH
-static struct module_pin_mux rgmii1_pin_mux[] = {
-	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
-	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
-	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
-	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
-	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
-	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
-	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
-	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
-	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
-	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
-	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
-	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-static struct module_pin_mux rgmii2_pin_mux[] = {
-	{OFFSET(gpmc_a0), MODE(2)},			/* RGMII2_TCTL */
-	{OFFSET(gpmc_a1), MODE(2) | RXACTIVE},		/* RGMII2_RCTL */
-	{OFFSET(gpmc_a2), MODE(2)},			/* RGMII2_TD3 */
-	{OFFSET(gpmc_a3), MODE(2)},			/* RGMII2_TD2 */
-	{OFFSET(gpmc_a4), MODE(2)},			/* RGMII2_TD1 */
-	{OFFSET(gpmc_a5), MODE(2)},			/* RGMII2_TD0 */
-	{OFFSET(gpmc_a6), MODE(7)},			/* RGMII2_TCLK */
-	{OFFSET(gpmc_a7), MODE(2) | RXACTIVE},		/* RGMII2_RCLK */
-	{OFFSET(gpmc_a8), MODE(2) | RXACTIVE},		/* RGMII2_RD3 */
-	{OFFSET(gpmc_a9), MODE(7)},			/* RGMII2_RD2 */
-	{OFFSET(gpmc_a10), MODE(2) | RXACTIVE},		/* RGMII2_RD1 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-#endif
-
-#ifdef CONFIG_MMC
-static struct module_pin_mux mmc0_pin_mux[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
-	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)},	/* MMC0_CD */
-	{-1},
-};
-#endif
-
-static struct module_pin_mux lcdc_pin_mux[] = {
-	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD_DAT0 */
-	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD_DAT1 */
-	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD_DAT2 */
-	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD_DAT3 */
-	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD_DAT4 */
-	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD_DAT5 */
-	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD_DAT6 */
-	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD_DAT7 */
-	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD_DAT8 */
-	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD_DAT9 */
-	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD_DAT10 */
-	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD_DAT11 */
-	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD_DAT12 */
-	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD_DAT13 */
-	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD_DAT14 */
-	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD_DAT15 */
-	{OFFSET(gpmc_ad8), (MODE(1))},			/* LCD_DAT16 */
-	{OFFSET(gpmc_ad9), (MODE(1))},		/* LCD_DAT17 */
-	{OFFSET(gpmc_ad10), (MODE(1))},		/* LCD_DAT18 */
-	{OFFSET(gpmc_ad11), (MODE(1))},		/* LCD_DAT19 */
-	{OFFSET(gpmc_ad12), (MODE(1))},		/* LCD_DAT20 */
-	{OFFSET(gpmc_ad13), (MODE(1))},		/* LCD_DAT21 */
-	{OFFSET(gpmc_ad14), (MODE(1))},		/* LCD_DAT22 */
-	{OFFSET(gpmc_ad15), (MODE(1))},		/* LCD_DAT23 */
-	{OFFSET(lcd_vsync), (MODE(0))},		/* LCD_VSYNC */
-	{OFFSET(lcd_hsync), (MODE(0))},		/* LCD_HSYNC */
-	{OFFSET(lcd_pclk), (MODE(0))},		/* LCD_PCLK */
-	{OFFSET(lcd_ac_bias_en), (MODE(0))},	/* LCD_AC_BIAS_EN */
-	{-1},
-};
-
-static struct module_pin_mux ecap0_pin_mux[] = {
-	{OFFSET(ecap0_in_pwm0_out), (MODE(0))},
-	{-1},
-};
-
-static struct module_pin_mux gpio_pin_mux[] = {
-	{OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/
-	{OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */
-	{OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */
-	{-1},
-};
-void enable_i2c0_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_board_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-	configure_module_pin_mux(i2c1_pin_mux);
-#ifdef CONFIG_NAND
-	configure_module_pin_mux(nand_pin_mux);
-#endif
-#ifndef CONFIG_NO_ETH
-	configure_module_pin_mux(rgmii1_pin_mux);
-	configure_module_pin_mux(rgmii2_pin_mux);
-#endif
-#ifdef CONFIG_MMC
-	configure_module_pin_mux(mmc0_pin_mux);
-#endif
-	configure_module_pin_mux(lcdc_pin_mux);
-	configure_module_pin_mux(gpio_pin_mux);
-	configure_module_pin_mux(ecap0_pin_mux);
-}
diff --git a/qemu/roms/u-boot/board/siemens/pxm2/pmic.h b/qemu/roms/u-boot/board/siemens/pxm2/pmic.h
deleted file mode 100644
index c6347e512..000000000
--- a/qemu/roms/u-boot/board/siemens/pxm2/pmic.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef PMIC_H
-#define PMIC_H
-
-/*
- * The PMIC on this board is a TPS65910.
- */
-
-#define PMIC_SR_I2C_ADDR		0x12
-#define PMIC_CTRL_I2C_ADDR		0x2D
-/* PMIC Register offsets */
-#define PMIC_VDD1_REG			0x21
-#define PMIC_VDD1_OP_REG		0x22
-#define PMIC_VDD2_REG			0x24
-#define PMIC_VDD2_OP_REG		0x25
-#define PMIC_DEVCTRL_REG		0x3f
-
-/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
-#define PMIC_VGAIN_SEL_MASK		(0x3 << 6)
-#define PMIC_ILMAX_MASK			(0x1 << 5)
-#define PMIC_TSTEP_MASK			(0x7 << 2)
-#define PMIC_ST_MASK			(0x3)
-
-#define PMIC_REG_VGAIN_SEL_X1		(0x0 << 6)
-#define PMIC_REG_VGAIN_SEL_X1_0		(0x1 << 6)
-#define PMIC_REG_VGAIN_SEL_X3		(0x2 << 6)
-#define PMIC_REG_VGAIN_SEL_X4		(0x3 << 6)
-
-#define PMIC_REG_ILMAX_1_0_A		(0x0 << 5)
-#define PMIC_REG_ILMAX_1_5_A		(0x1 << 5)
-
-#define PMIC_REG_TSTEP_			(0x0 << 2)
-#define PMIC_REG_TSTEP_12_5		(0x1 << 2)
-#define PMIC_REG_TSTEP_9_4		(0x2 << 2)
-#define PMIC_REG_TSTEP_7_5		(0x3 << 2)
-#define PMIC_REG_TSTEP_6_25		(0x4 << 2)
-#define PMIC_REG_TSTEP_4_7		(0x5 << 2)
-#define PMIC_REG_TSTEP_3_12		(0x6 << 2)
-#define PMIC_REG_TSTEP_2_5		(0x7 << 2)
-
-#define PMIC_REG_ST_OFF			(0x0)
-#define PMIC_REG_ST_ON_HI_POW		(0x1)
-#define PMIC_REG_ST_OFF_1		(0x2)
-#define PMIC_REG_ST_ON_LOW_POW		(0x3)
-
-
-/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
-#define PMIC_OP_REG_SEL				(0x7F)
-
-#define PMIC_OP_REG_CMD_MASK			(0x1 << 7)
-#define PMIC_OP_REG_CMD_OP			(0x0 << 7)
-#define PMIC_OP_REG_CMD_SR			(0x1 << 7)
-
-#define PMIC_OP_REG_SEL_MASK			(0x7F)
-#define PMIC_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
-#define PMIC_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
-
-/* Device control register . (DEVCTRL_REG) */
-#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK	(0x1 << 4)
-#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
-#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
-
-#endif