diff options
| author |   RajithaY <rajithax.yerrumsetty@intel.com> | 2017-04-25 03:31:15 -0700 |
|---|---|---|
| committer | Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> | 2017-05-22 06:48:08 +0000 |
| commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
| tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/board/samsung | |
| parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) | |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/samsung')
43 files changed, 0 insertions, 5735 deletions
diff --git a/qemu/roms/u-boot/board/samsung/arndale/Makefile b/qemu/roms/u-boot/board/samsung/arndale/Makefile deleted file mode 100644 index be2b3662a..000000000 --- a/qemu/roms/u-boot/board/samsung/arndale/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (C) 2013 Samsung Electronics -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += arndale_spl.o - -ifndef CONFIG_SPL_BUILD -obj-y += arndale.o -endif diff --git a/qemu/roms/u-boot/board/samsung/arndale/arndale.c b/qemu/roms/u-boot/board/samsung/arndale/arndale.c deleted file mode 100644 index 9efc355da..000000000 --- a/qemu/roms/u-boot/board/samsung/arndale/arndale.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <usb.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/power.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_USB_EHCI_EXYNOS -int board_usb_init(int index, enum usb_init_type init) -{ - struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Configure gpios for usb 3503 hub: - * disconnect, toggle reset and connect - */ - s5p_gpio_direction_output(&gpio->d1, 7, 0); - s5p_gpio_direction_output(&gpio->x3, 5, 0); - - s5p_gpio_direction_output(&gpio->x3, 5, 1); - s5p_gpio_direction_output(&gpio->d1, 7, 1); - - return 0; -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - return 0; -} - -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - -int power_init_board(void) -{ - set_ps_hold_ctrl(); - return 0; -} - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int ret; - /* dwmmc initializattion for available channels */ - ret = exynos_dwmmc_init(gd->fdt_blob); - if (ret) - debug("dwmmc init failed\n"); - - return ret; -} -#endif - -static int board_uart_init(void) -{ - int err = 0, uart_id; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - return err; - } - } - return err; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } - return err; -} -#endif - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("\nBoard: Arndale\n"); - - return 0; -} -#endif diff --git a/qemu/roms/u-boot/board/samsung/arndale/arndale_spl.c b/qemu/roms/u-boot/board/samsung/arndale/arndale_spl.c deleted file mode 100644 index 2949c0828..000000000 --- a/qemu/roms/u-boot/board/samsung/arndale/arndale_spl.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/spl.h> - -#define SIGNATURE 0xdeadbeef - -/* Parameters of early board initialization in SPL */ -static struct spl_machine_param machine_param - __attribute__((section(".machine_param"))) = { - .signature = SIGNATURE, - .version = 1, - .params = "vmubfasirM", - .size = sizeof(machine_param), - - .mem_iv_size = 0x1f, - .mem_type = DDR_MODE_DDR3, - - /* - * Set uboot_size to 0x100000 bytes. - * - * This is an overly conservative value chosen to accommodate all - * possible U-Boot image. You are advised to set this value to a - * smaller realistic size via scripts that modifies the .machine_param - * section of output U-Boot image. - */ - .uboot_size = 0x100000, - - .boot_source = BOOT_MODE_OM, - .frequency_mhz = 800, - .arm_freq_mhz = 1000, - .serial_base = 0x12c30000, - .i2c_base = 0x12c60000, - .mem_manuf = MEM_MANUF_SAMSUNG, -}; - -struct spl_machine_param *spl_get_machine_params(void) -{ - if (machine_param.signature != SIGNATURE) { - /* Will hang if SIGNATURE dont match */ - while (1) - ; - } - - return &machine_param; -} diff --git a/qemu/roms/u-boot/board/samsung/common/Makefile b/qemu/roms/u-boot/board/samsung/common/Makefile deleted file mode 100644 index 7d2bb8c4a..000000000 --- a/qemu/roms/u-boot/board/samsung/common/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (C) 2012 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o -obj-$(CONFIG_THOR_FUNCTION) += thor.o -obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o -obj-$(CONFIG_MISC_COMMON) += misc.o - -ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_BOARD_COMMON) += board.o -endif diff --git a/qemu/roms/u-boot/board/samsung/common/board.c b/qemu/roms/u-boot/board/samsung/common/board.c deleted file mode 100644 index de154e0f6..000000000 --- a/qemu/roms/u-boot/board/samsung/common/board.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * (C) Copyright 2013 SAMSUNG Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <cros_ec.h> -#include <errno.h> -#include <fdtdec.h> -#include <spi.h> -#include <tmu.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/board.h> -#include <asm/arch/cpu.h> -#include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/power.h> -#include <power/pmic.h> -#include <asm/arch/sromc.h> -#include <lcd.h> -#include <samsung/misc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int __exynos_early_init_f(void) -{ - return 0; -} -int exynos_early_init_f(void) - __attribute__((weak, alias("__exynos_early_init_f"))); - -int __exynos_power_init(void) -{ - return 0; -} -int exynos_power_init(void) - __attribute__((weak, alias("__exynos_power_init"))); - -#if defined CONFIG_EXYNOS_TMU -/* Boot Time Thermal Analysis for SoC temperature threshold breach */ -static void boot_temp_check(void) -{ - int temp; - - switch (tmu_monitor(&temp)) { - case TMU_STATUS_NORMAL: - break; - case TMU_STATUS_TRIPPED: - /* - * Status TRIPPED ans WARNING means corresponding threshold - * breach - */ - puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); - set_ps_hold_ctrl(); - hang(); - break; - case TMU_STATUS_WARNING: - puts("EXYNOS_TMU: WARNING! Temperature very high\n"); - break; - case TMU_STATUS_INIT: - /* - * TMU_STATUS_INIT means something is wrong with temperature - * sensing and TMU status was changed back from NORMAL to INIT. - */ - puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); - break; - default: - debug("EXYNOS_TMU: Unknown TMU state\n"); - } -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); -#if defined CONFIG_EXYNOS_TMU - if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { - debug("%s: Failed to init TMU\n", __func__); - return -1; - } - boot_temp_check(); -#endif - -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif - return exynos_init(); -} - -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - -static int board_uart_init(void) -{ - int err, uart_id, ret = 0; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - ret |= err; - } - } - return ret; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } - -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(gd->fdt_blob); -#endif - - return exynos_early_init_f(); -} -#endif - -#if defined(CONFIG_POWER) -int power_init_board(void) -{ - set_ps_hold_ctrl(); - - return exynos_power_init(); -} -#endif - -#ifdef CONFIG_OF_CONTROL -#ifdef CONFIG_SMC911X -static int decode_sromc(const void *blob, struct fdt_sromc *config) -{ - int err; - int node; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); - if (node < 0) { - debug("Could not find SROMC node\n"); - return node; - } - - config->bank = fdtdec_get_int(blob, node, "bank", 0); - config->width = fdtdec_get_int(blob, node, "width", 2); - - err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, - FDT_SROM_TIMING_COUNT); - if (err < 0) { - debug("Could not decode SROMC configuration Error: %s\n", - fdt_strerror(err)); - return -FDT_ERR_NOTFOUND; - } - return 0; -} -#endif - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - int node; - - node = decode_sromc(gd->fdt_blob, &config); - if (node < 0) { - debug("%s: Could not find sromc configuration\n", __func__); - return 0; - } - node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); - if (node < 0) { - debug("%s: Could not find lan9215 configuration\n", __func__); - return 0; - } - - /* We now have a node, so any problems from now on are errors */ - base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) { - debug("%s: Could not find lan9215 address\n", __func__); - return -1; - } - - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int ret; - -#ifdef CONFIG_SDHCI - /* mmc initializattion for available channels */ - ret = exynos_mmc_init(gd->fdt_blob); - if (ret) - debug("mmc init failed\n"); -#endif -#ifdef CONFIG_DWMMC - /* dwmmc initializattion for available channels */ - ret = exynos_dwmmc_init(gd->fdt_blob); - if (ret) - debug("dwmmc init failed\n"); -#endif - - return ret; -} -#endif - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - printf("Board: %s\n", board_name ? board_name : "unknown"); - - return 0; -} -#endif -#endif /* CONFIG_OF_CONTROL */ - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - stdio_print_current_devices(); - - if (cros_ec_get_error()) { - /* Force console on */ - gd->flags &= ~GD_FLG_SILENT; - - printf("cros-ec communications failure %d\n", - cros_ec_get_error()); - puts("\nPlease reset with Power+Refresh\n\n"); - panic("Cannot init cros-ec device"); - return -1; - } - return 0; -} -#endif - -int arch_early_init_r(void) -{ -#ifdef CONFIG_CROS_EC - if (cros_ec_board_init()) { - printf("%s: Failed to init EC\n", __func__); - return 0; - } -#endif - - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif -#ifdef CONFIG_LCD_MENU - keys_init(); - check_boot_mode(); -#endif -#ifdef CONFIG_CMD_BMP - if (panel_info.logo_on) - draw_logo(); -#endif - return 0; -} -#endif diff --git a/qemu/roms/u-boot/board/samsung/common/dfu_sample_env.txt b/qemu/roms/u-boot/board/samsung/common/dfu_sample_env.txt deleted file mode 100644 index d6ee8a228..000000000 --- a/qemu/roms/u-boot/board/samsung/common/dfu_sample_env.txt +++ /dev/null @@ -1,9 +0,0 @@ -mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0 -rootfstype=ext4 -loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage -mmcdev=0 -mmcbootpart=2 -mmcrootpart=5 -console=console=ttySAC2,115200n8 -bootcmd=run mmcboot -dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2 diff --git a/qemu/roms/u-boot/board/samsung/common/exynos-uboot-spl.lds b/qemu/roms/u-boot/board/samsung/common/exynos-uboot-spl.lds deleted file mode 100644 index b22f9e07b..000000000 --- a/qemu/roms/u-boot/board/samsung/common/exynos-uboot-spl.lds +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * Copyright (C) 2012 Samsung Electronics - * - * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ - LENGTH = CONFIG_SPL_MAX_FOOTPRINT } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) - -SECTIONS -{ - .text : - { - __start = .; - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - } >.sram - . = ALIGN(4); - - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - . = ALIGN(4); - - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - . = ALIGN(4); - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } >.sram - . = ALIGN(4); - - /* Align .machine_param on 256 byte boundary for easier searching */ - .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram - . = ALIGN(4); - - __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sram -} diff --git a/qemu/roms/u-boot/board/samsung/common/misc.c b/qemu/roms/u-boot/board/samsung/common/misc.c deleted file mode 100644 index 3ff428978..000000000 --- a/qemu/roms/u-boot/board/samsung/common/misc.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * Przemyslaw Marczak <p.marczak@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <lcd.h> -#include <libtizen.h> -#include <samsung/misc.h> -#include <errno.h> -#include <version.h> -#include <linux/sizes.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/gpio.h> -#include <linux/input.h> -#include <power/pmic.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -void set_board_info(void) -{ - char info[64]; - - snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f, - (s5p_cpu_rev & 0xf0) >> 0x04); - setenv("soc_rev", info); - - snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id); - setenv("soc_id", info); - -#ifdef CONFIG_REVISION_TAG - snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev()); - setenv("board_rev", info); -#endif -#ifdef CONFIG_OF_LIBFDT - snprintf(info, ARRAY_SIZE(info), "%s%x-%s.dtb", - CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD); - setenv("fdtfile", info); -#endif -} -#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ - -#ifdef CONFIG_LCD_MENU -static int power_key_pressed(u32 reg) -{ - struct pmic *pmic; - u32 status; - u32 mask; - - pmic = pmic_get(KEY_PWR_PMIC_NAME); - if (!pmic) { - printf("%s: Not found\n", KEY_PWR_PMIC_NAME); - return 0; - } - - if (pmic_probe(pmic)) - return 0; - - if (reg == KEY_PWR_STATUS_REG) - mask = KEY_PWR_STATUS_MASK; - else - mask = KEY_PWR_INTERRUPT_MASK; - - if (pmic_reg_read(pmic, reg, &status)) - return 0; - - return !!(status & mask); -} - -static int key_pressed(int key) -{ - int value; - - switch (key) { - case KEY_POWER: - value = power_key_pressed(KEY_PWR_INTERRUPT_REG); - break; - case KEY_VOLUMEUP: - value = !gpio_get_value(KEY_VOL_UP_GPIO); - break; - case KEY_VOLUMEDOWN: - value = !gpio_get_value(KEY_VOL_DOWN_GPIO); - break; - default: - value = 0; - break; - } - - return value; -} - -static int check_keys(void) -{ - int keys = 0; - - if (key_pressed(KEY_POWER)) - keys += KEY_POWER; - if (key_pressed(KEY_VOLUMEUP)) - keys += KEY_VOLUMEUP; - if (key_pressed(KEY_VOLUMEDOWN)) - keys += KEY_VOLUMEDOWN; - - return keys; -} - -/* - * 0 BOOT_MODE_INFO - * 1 BOOT_MODE_THOR - * 2 BOOT_MODE_UMS - * 3 BOOT_MODE_DFU - * 4 BOOT_MODE_EXIT - */ -static char * -mode_name[BOOT_MODE_EXIT + 1] = { - "DEVICE", - "THOR", - "UMS", - "DFU", - "EXIT" -}; - -static char * -mode_info[BOOT_MODE_EXIT + 1] = { - "info", - "downloader", - "mass storage", - "firmware update", - "and run normal boot" -}; - -#define MODE_CMD_ARGC 4 - -static char * -mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = { - {"", "", "", ""}, - {"thor", "0", "mmc", "0"}, - {"ums", "0", "mmc", "0"}, - {"dfu", "0", "mmc", "0"}, - {"", "", "", ""}, -}; - -static void display_board_info(void) -{ -#ifdef CONFIG_GENERIC_MMC - struct mmc *mmc = find_mmc_device(0); -#endif - vidinfo_t *vid = &panel_info; - - lcd_position_cursor(4, 4); - - lcd_printf("%s\n\t", U_BOOT_VERSION); - lcd_puts("\n\t\tBoard Info:\n"); -#ifdef CONFIG_SYS_BOARD - lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD); -#endif -#ifdef CONFIG_REVISION_TAG - lcd_printf("\tBoard rev: %u\n", get_board_rev()); -#endif - lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS); - lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M); - -#ifdef CONFIG_GENERIC_MMC - if (mmc) { - if (!mmc->capacity) - mmc_init(mmc); - - lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M); - } -#endif - if (vid) - lcd_printf("\tDisplay resolution: %u x % u\n", - vid->vl_col, vid->vl_row); - - lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix); -} - -static int mode_leave_menu(int mode) -{ - char *exit_option; - char *exit_boot = "boot"; - char *exit_back = "back"; - cmd_tbl_t *cmd; - int cmd_result; - int cmd_repeatable; - int leave; - - lcd_clear(); - - switch (mode) { - case BOOT_MODE_EXIT: - return 1; - case BOOT_MODE_INFO: - display_board_info(); - exit_option = exit_back; - leave = 0; - break; - default: - cmd = find_cmd(mode_cmd[mode][0]); - if (cmd) { - printf("Enter: %s %s\n", mode_name[mode], - mode_info[mode]); - lcd_printf("\n\n\t%s %s\n", mode_name[mode], - mode_info[mode]); - lcd_puts("\n\tDo not turn off device before finish!\n"); - - cmd_result = cmd_process(0, MODE_CMD_ARGC, - *(mode_cmd + mode), - &cmd_repeatable, NULL); - - if (cmd_result == CMD_RET_SUCCESS) { - printf("Command finished\n"); - lcd_clear(); - lcd_printf("\n\n\t%s finished\n", - mode_name[mode]); - - exit_option = exit_boot; - leave = 1; - } else { - printf("Command error\n"); - lcd_clear(); - lcd_printf("\n\n\t%s command error\n", - mode_name[mode]); - - exit_option = exit_back; - leave = 0; - } - } else { - lcd_puts("\n\n\tThis mode is not supported.\n"); - exit_option = exit_back; - leave = 0; - } - } - - lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option); - - /* Clear PWR button Rising edge interrupt status flag */ - power_key_pressed(KEY_PWR_INTERRUPT_REG); - - /* Wait for PWR key */ - while (!key_pressed(KEY_POWER)) - mdelay(1); - - lcd_clear(); - return leave; -} - -static void display_download_menu(int mode) -{ - char *selection[BOOT_MODE_EXIT + 1]; - int i; - - for (i = 0; i <= BOOT_MODE_EXIT; i++) - selection[i] = "[ ]"; - - selection[mode] = "[=>]"; - - lcd_clear(); - lcd_printf("\n\t\tDownload Mode Menu\n"); - - for (i = 0; i <= BOOT_MODE_EXIT; i++) - lcd_printf("\t%s %s - %s\n\n", selection[i], - mode_name[i], - mode_info[i]); -} - -static void download_menu(void) -{ - int mode = 0; - int last_mode = 0; - int run; - int key; - - display_download_menu(mode); - - while (1) { - run = 0; - - if (mode != last_mode) - display_download_menu(mode); - - last_mode = mode; - mdelay(100); - - key = check_keys(); - switch (key) { - case KEY_POWER: - run = 1; - break; - case KEY_VOLUMEUP: - if (mode > 0) - mode--; - break; - case KEY_VOLUMEDOWN: - if (mode < BOOT_MODE_EXIT) - mode++; - break; - default: - break; - } - - if (run) { - if (mode_leave_menu(mode)) - break; - - display_download_menu(mode); - } - } - - lcd_clear(); -} - -static void display_mode_info(void) -{ - lcd_position_cursor(4, 4); - lcd_printf("%s\n", U_BOOT_VERSION); - lcd_puts("\nDownload Mode Menu\n"); -#ifdef CONFIG_SYS_BOARD - lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD); -#endif - lcd_printf("Press POWER KEY to display MENU options."); -} - -static int boot_menu(void) -{ - int key = 0; - int timeout = 10; - - display_mode_info(); - - while (timeout--) { - lcd_printf("\rNormal boot will start in: %d seconds.", timeout); - mdelay(1000); - - key = key_pressed(KEY_POWER); - if (key) - break; - } - - lcd_clear(); - - /* If PWR pressed - show download menu */ - if (key) { - printf("Power pressed - go to download menu\n"); - download_menu(); - printf("Download mode exit.\n"); - } - - return 0; -} - -void check_boot_mode(void) -{ - int pwr_key; - - pwr_key = power_key_pressed(KEY_PWR_STATUS_REG); - if (!pwr_key) - return; - - /* Clear PWR button Rising edge interrupt status flag */ - power_key_pressed(KEY_PWR_INTERRUPT_REG); - - if (key_pressed(KEY_VOLUMEUP)) - boot_menu(); - else if (key_pressed(KEY_VOLUMEDOWN)) - mode_leave_menu(BOOT_MODE_THOR); -} - -void keys_init(void) -{ - /* Set direction to input */ - gpio_direction_input(KEY_VOL_UP_GPIO); - gpio_direction_input(KEY_VOL_DOWN_GPIO); -} -#endif /* CONFIG_LCD_MENU */ - -#ifdef CONFIG_CMD_BMP -void draw_logo(void) -{ - int x, y; - ulong addr; - - addr = panel_info.logo_addr; - if (!addr) { - error("There is no logo data."); - return; - } - - if (panel_info.vl_width >= panel_info.logo_width) { - x = ((panel_info.vl_width - panel_info.logo_width) >> 1); - x += panel_info.logo_x_offset; /* For X center align */ - } else { - x = 0; - printf("Warning: image width is bigger than display width\n"); - } - - if (panel_info.vl_height >= panel_info.logo_height) { - y = ((panel_info.vl_height - panel_info.logo_height) >> 1); - y += panel_info.logo_y_offset; /* For Y center align */ - } else { - y = 0; - printf("Warning: image height is bigger than display height\n"); - } - - bmp_display(addr, x, y); -} -#endif /* CONFIG_CMD_BMP */ diff --git a/qemu/roms/u-boot/board/samsung/common/multi_i2c.c b/qemu/roms/u-boot/board/samsung/common/multi_i2c.c deleted file mode 100644 index 71c32c0b6..000000000 --- a/qemu/roms/u-boot/board/samsung/common/multi_i2c.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> - -#ifndef CONFIG_SOFT_I2C_I2C10_SCL -#define CONFIG_SOFT_I2C_I2C10_SCL 0 -#endif - -#ifndef CONFIG_SOFT_I2C_I2C10_SDA -#define CONFIG_SOFT_I2C_I2C10_SDA 0 -#endif - -/* Handle multiple I2C buses instances */ -int get_multi_scl_pin(void) -{ - unsigned int bus = i2c_get_bus_num(); - - switch (bus) { - case I2C_0: - return CONFIG_SOFT_I2C_I2C5_SCL; - case I2C_1: - return CONFIG_SOFT_I2C_I2C9_SCL; - case I2C_2: - return CONFIG_SOFT_I2C_I2C10_SCL; - default: - printf("I2C_%d not supported!\n", bus); - }; - - return 0; -} - -int get_multi_sda_pin(void) -{ - unsigned int bus = i2c_get_bus_num(); - - switch (bus) { - case I2C_0: - return CONFIG_SOFT_I2C_I2C5_SDA; - case I2C_1: - return CONFIG_SOFT_I2C_I2C9_SDA; - case I2C_2: - return CONFIG_SOFT_I2C_I2C10_SDA; - default: - printf("I2C_%d not supported!\n", bus); - }; - - return 0; -} - -int multi_i2c_init(void) -{ - return 0; -} diff --git a/qemu/roms/u-boot/board/samsung/common/thor.c b/qemu/roms/u-boot/board/samsung/common/thor.c deleted file mode 100644 index 1c7630df0..000000000 --- a/qemu/roms/u-boot/board/samsung/common/thor.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/usb/ch9.h> - -int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) -{ - if (!strcmp(name, "usb_dnl_thor")) { - put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor); - put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct); - } else { - put_unaligned(CONFIG_G_DNL_VENDOR_NUM, &dev->idVendor); - put_unaligned(CONFIG_G_DNL_PRODUCT_NUM, &dev->idProduct); - } - return 0; -} diff --git a/qemu/roms/u-boot/board/samsung/common/ums.c b/qemu/roms/u-boot/board/samsung/common/ums.c deleted file mode 100644 index cebabe920..000000000 --- a/qemu/roms/u-boot/board/samsung/common/ums.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <usb_mass_storage.h> -#include <part.h> - -static int ums_read_sector(struct ums *ums_dev, - ulong start, lbaint_t blkcnt, void *buf) -{ - block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev; - lbaint_t blkstart = start + ums_dev->start_sector; - int dev_num = block_dev->dev; - - return block_dev->block_read(dev_num, blkstart, blkcnt, buf); -} - -static int ums_write_sector(struct ums *ums_dev, - ulong start, lbaint_t blkcnt, const void *buf) -{ - block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev; - lbaint_t blkstart = start + ums_dev->start_sector; - int dev_num = block_dev->dev; - - return block_dev->block_write(dev_num, blkstart, blkcnt, buf); -} - -static struct ums ums_dev = { - .read_sector = ums_read_sector, - .write_sector = ums_write_sector, - .name = "UMS disk", -}; - -static struct ums *ums_disk_init(struct mmc *mmc) -{ - uint64_t mmc_end_sector = mmc->capacity / SECTOR_SIZE; - uint64_t ums_end_sector = UMS_NUM_SECTORS + UMS_START_SECTOR; - - if (!mmc_end_sector) { - error("MMC capacity is not valid"); - return NULL; - } - - ums_dev.mmc = mmc; - - if (ums_end_sector <= mmc_end_sector) { - ums_dev.start_sector = UMS_START_SECTOR; - if (UMS_NUM_SECTORS) - ums_dev.num_sectors = UMS_NUM_SECTORS; - else - ums_dev.num_sectors = mmc_end_sector - UMS_START_SECTOR; - } else { - ums_dev.num_sectors = mmc_end_sector; - puts("UMS: defined bad disk parameters. Using default.\n"); - } - - printf("UMS: disk start sector: %#x, count: %#x\n", - ums_dev.start_sector, ums_dev.num_sectors); - - return &ums_dev; -} - -struct ums *ums_init(unsigned int dev_num) -{ - struct mmc *mmc = find_mmc_device(dev_num); - - if (!mmc || mmc_init(mmc)) - return NULL; - return ums_disk_init(mmc); -} diff --git a/qemu/roms/u-boot/board/samsung/goni/Makefile b/qemu/roms/u-boot/board/samsung/goni/Makefile deleted file mode 100644 index 2cdc21d85..000000000 --- a/qemu/roms/u-boot/board/samsung/goni/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := goni.o onenand.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/samsung/goni/goni.c b/qemu/roms/u-boot/board/samsung/goni/goni.c deleted file mode 100644 index 61b9ece03..000000000 --- a/qemu/roms/u-boot/board/samsung/goni/goni.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (C) 2008-2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <power/pmic.h> -#include <usb/s3c_udc.h> -#include <asm/arch/cpu.h> -#include <power/max8998_pmic.h> -#include <samsung/misc.h> - -DECLARE_GLOBAL_DATA_PTR; - -static struct s5pc110_gpio *s5pc110_gpio; - -u32 get_board_rev(void) -{ - return 0; -} - -int board_init(void) -{ - /* Set Initial global variables */ - s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE; - - gd->bd->bi_arch_number = MACH_TYPE_GONI; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int power_init_board(void) -{ - int ret; - - /* - * For PMIC the I2C bus is named as I2C5, but it is connected - * to logical I2C adapter 0 - */ - ret = pmic_init(I2C_0); - if (ret) - return ret; - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + - PHYS_SDRAM_3_SIZE; - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tGoni\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int i, ret, ret_sd = 0; - - /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1); - - /* - * MMC0 GPIO - * GPG0[0] SD_0_CLK - * GPG0[1] SD_0_CMD - * GPG0[2] SD_0_CDn -> Not used - * GPG0[3:6] SD_0_DATA[0:3] - */ - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - /* GPG0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); - /* GPG0[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); - /* GPG0[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); - } - - ret = s5p_mmc_init(0, 4); - if (ret) - error("MMC: Failed to init MMC:0.\n"); - - /* - * SD card (T_FLASH) detect and init - * T_FLASH_DETECT: EINT28: GPH3[4] input mode - */ - s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT); - s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP); - - if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) { - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - - /* GPG2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2); - /* GPG2[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE); - /* GPG2[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X); - } - - ret_sd = s5p_mmc_init(2, 4); - if (ret_sd) - error("MMC: Failed to init SD card (MMC:2).\n"); - } - - return ret & ret_sd; -} -#endif - -#ifdef CONFIG_USB_GADGET -static int s5pc1xx_phy_control(int on) -{ - int ret; - static int status; - struct pmic *p = pmic_get("MAX8998_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (on && !status) { - ret = pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_ON); - ret = pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_ON); - if (ret) { - puts("MAX8998 LDO setting error!\n"); - return -1; - } - status = 1; - } else if (!on && status) { - ret = pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_OFF); - ret = pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_OFF); - if (ret) { - puts("MAX8998 LDO setting error!\n"); - return -1; - } - status = 0; - } - udelay(10000); - - return 0; -} - -struct s3c_plat_otg_data s5pc110_otg_data = { - .phy_control = s5pc1xx_phy_control, - .regs_phy = S5PC110_PHY_BASE, - .regs_otg = S5PC110_OTG_BASE, - .usb_phy_ctrl = S5PC110_USB_PHY_CONTROL, -}; -#endif - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif - return 0; -} -#endif diff --git a/qemu/roms/u-boot/board/samsung/goni/lowlevel_init.S b/qemu/roms/u-boot/board/samsung/goni/lowlevel_init.S deleted file mode 100644 index d52bc09f8..000000000 --- a/qemu/roms/u-boot/board/samsung/goni/lowlevel_init.S +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clock.h> -#include <asm/arch/power.h> - -/* - * Register usages: - * - * r5 has zero always - * r7 has S5PC100 GPIO base, 0xE0300000 - * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively - * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on - */ - - .globl lowlevel_init -lowlevel_init: - mov r11, lr - - /* r5 has always zero */ - mov r5, #0 - - ldr r7, =S5PC100_GPIO_BASE - ldr r8, =S5PC100_GPIO_BASE - /* Read CPU ID */ - ldr r2, =S5PC110_PRO_ID - ldr r0, [r2] - mov r1, #0x00010000 - and r0, r0, r1 - cmp r0, r5 - beq 100f - ldr r8, =S5PC110_GPIO_BASE -100: - /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */ - cmp r7, r8 - beq skip_check_didle @ Support C110 only - - ldr r0, =S5PC110_RST_STAT - ldr r1, [r0] - and r1, r1, #0x000D0000 - cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP - beq didle_wakeup - cmp r7, r8 - -skip_check_didle: - addeq r0, r8, #0x280 @ S5PC100_GPIO_J4 - addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4 - ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET - bic r1, r1, #(0xf << 4) @ 1 * 4-bit - orr r1, r1, #(0x1 << 4) - str r1, [r0, #0x0] @ GPIO_CON_OFFSET - - ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET - bic r1, r1, #(1 << 1) - str r1, [r0, #0x4] @ GPIO_DAT_OFFSET - - /* Don't setup at s5pc100 */ - beq 100f - - /* - * Initialize Async Register Setting for EVT1 - * Because we are setting EVT1 as the default value of EVT0, - * setting EVT0 as well does not make things worse. - * Thus, for the simplicity, we set for EVT0, too - * - * The "Async Registers" are: - * 0xE0F0_0000 - * 0xE1F0_0000 - * 0xF180_0000 - * 0xF190_0000 - * 0xF1A0_0000 - * 0xF1B0_0000 - * 0xF1C0_0000 - * 0xF1D0_0000 - * 0xF1E0_0000 - * 0xF1F0_0000 - * 0xFAF0_0000 - */ - ldr r0, =0xe0f00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xe1f00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1800000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1900000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1a00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1b00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1c00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1d00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1e00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xf1f00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - ldr r0, =0xfaf00000 - ldr r1, [r0] - bic r1, r1, #0x1 - str r1, [r0] - - /* - * Diable ABB block to reduce sleep current at low temperature - * Note that it's hidden register setup don't modify it - */ - ldr r0, =0xE010C300 - ldr r1, =0x00800000 - str r1, [r0] - -100: - /* IO retension release */ - ldreq r0, =S5PC100_OTHERS @ 0xE0108200 - ldrne r0, =S5PC110_OTHERS @ 0xE010E000 - ldr r1, [r0] - ldreq r2, =(1 << 31) @ IO_RET_REL - ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) - orr r1, r1, r2 - /* Do not release retention here for S5PC110 */ - streq r1, [r0] - - /* Disable Watchdog */ - ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000 - ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000 - str r5, [r0] - - /* setting SRAM */ - ldreq r0, =S5PC100_SROMC_BASE - ldrne r0, =S5PC110_SROMC_BASE - ldr r1, =0x9 - str r1, [r0] - - /* S5PC100 has 3 groups of interrupt sources */ - ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000 - ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000 - add r1, r0, #0x00100000 - add r2, r0, #0x00200000 - - /* Disable all interrupts (VIC0, VIC1 and VIC2) */ - mvn r3, #0x0 - str r3, [r0, #0x14] @ INTENCLEAR - str r3, [r1, #0x14] @ INTENCLEAR - str r3, [r2, #0x14] @ INTENCLEAR - - /* Set all interrupts as IRQ */ - str r5, [r0, #0xc] @ INTSELECT - str r5, [r1, #0xc] @ INTSELECT - str r5, [r2, #0xc] @ INTSELECT - - /* Pending Interrupt Clear */ - str r5, [r0, #0xf00] @ INTADDRESS - str r5, [r1, #0xf00] @ INTADDRESS - str r5, [r2, #0xf00] @ INTADDRESS - - /* for UART */ - bl uart_asm_init - - bl internal_ram_init - - cmp r7, r8 - /* Clear wakeup status register */ - ldreq r0, =S5PC100_WAKEUP_STAT - ldrne r0, =S5PC110_WAKEUP_STAT - ldr r1, [r0] - str r1, [r0] - - /* IO retension release */ - ldreq r0, =S5PC100_OTHERS @ 0xE0108200 - ldrne r0, =S5PC110_OTHERS @ 0xE010E000 - ldr r1, [r0] - ldreq r2, =(1 << 31) @ IO_RET_REL - ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) - orr r1, r1, r2 - str r1, [r0] - - b 1f - -didle_wakeup: - /* Wait when APLL is locked */ - ldr r0, =0xE0100100 @ S5PC110_APLL_CON -lockloop: - ldr r1, [r0] - and r1, r1, #(1 << 29) - cmp r1, #(1 << 29) - bne lockloop - - ldr r0, =S5PC110_INFORM0 - ldr r1, [r0] - mov pc, r1 - nop - nop - nop - nop - nop - -1: - mov lr, r11 - mov pc, lr - -/* - * system_clock_init: Initialize core clock and bus clock. - * void system_clock_init(void) - */ -system_clock_init: - ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 - - /* Check S5PC100 */ - cmp r7, r8 - bne 110f -100: - /* Set Lock Time */ - ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 - str r1, [r0, #0x000] @ S5PC100_APLL_LOCK - str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK - str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK - str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK - - /* S5P_APLL_CON */ - ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz) - str r1, [r0, #0x100] - /* S5P_MPLL_CON */ - ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) - str r1, [r0, #0x104] - /* S5P_EPLL_CON */ - ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) - str r1, [r0, #0x108] - /* S5P_HPLL_CON */ - ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96 - str r1, [r0, #0x10C] - - ldr r1, [r0, #0x300] - ldr r2, =0x00003fff - bic r1, r1, r2 - ldr r2, =0x00011301 - - orr r1, r1, r2 - str r1, [r0, #0x300] - ldr r1, [r0, #0x304] - ldr r2, =0x00011110 - orr r1, r1, r2 - str r1, [r0, #0x304] - ldr r1, =0x00000001 - str r1, [r0, #0x308] - - /* Set Source Clock */ - ldr r1, =0x00001111 @ A, M, E, HPLL Muxing - str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 - - b 200f -110: - ldr r0, =0xE010C000 @ S5PC110_PWR_CFG - - /* Set OSC_FREQ value */ - ldr r1, =0xf - str r1, [r0, #0x100] @ S5PC110_OSC_FREQ - - /* Set MTC_STABLE value */ - ldr r1, =0xffffffff - str r1, [r0, #0x110] @ S5PC110_MTC_STABLE - - /* Set CLAMP_STABLE value */ - ldr r1, =0x3ff03ff - str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE - - ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 - - /* Set Clock divider */ - ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 - str r1, [r0, #0x300] - ldr r1, =0x11110111 @ UART[3210]: MMC[3210] - str r1, [r0, #0x310] - - /* Set Lock Time */ - ldr r1, =0x2cf @ Locktime : 30us - str r1, [r0, #0x000] @ S5PC110_APLL_LOCK - ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 - str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK - str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK - str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK - - /* S5PC110_APLL_CON */ - ldr r1, =0x80C80601 @ 800MHz - str r1, [r0, #0x100] - /* S5PC110_MPLL_CON */ - ldr r1, =0x829B0C01 @ 667MHz - str r1, [r0, #0x108] - /* S5PC110_EPLL_CON */ - ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2 - str r1, [r0, #0x110] - /* S5PC110_VPLL_CON */ - ldr r1, =0x806C0603 @ 54MHz - str r1, [r0, #0x120] - - /* Set Source Clock */ - ldr r1, =0x10001111 @ A, M, E, VPLL Muxing - str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 - - /* OneDRAM(DMC0) clock setting */ - ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL - str r1, [r0, #0x218] @ S5PC110_CLK_SRC6 - ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1 - str r1, [r0, #0x318] @ S5PC110_CLK_DIV6 - - /* XCLKOUT = XUSBXTI 24MHz */ - add r2, r0, #0xE000 @ S5PC110_OTHERS - ldr r1, [r2] - orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI - str r1, [r2] - - /* CLK_IP0 */ - ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5] - str r1, [r0, #0x460] @ S5PC110_CLK_IP0 - - /* CLK_IP1 */ - ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16] - @ NANDXL[24] - str r1, [r0, #0x464] @ S5PC110_CLK_IP1 - - /* CLK_IP2 */ - ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9] - @ HOSTIF[10] HSMMC0[16] - @ HSMMC2[18] VIC[27:24] - str r1, [r0, #0x468] @ S5PC110_CLK_IP2 - - /* CLK_IP3 */ - ldr r1, =0x8eff038c @ I2C[8:6] - @ SYSTIMER[16] UART0[17] - @ UART1[18] UART2[19] - @ UART3[20] WDT[22] - @ PWM[23] GPIO[26] SYSCON[27] - str r1, [r0, #0x46c] @ S5PC110_CLK_IP3 - - /* CLK_IP4 */ - ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5] - str r1, [r0, #0x470] @ S5PC110_CLK_IP3 - -200: - /* wait at least 200us to stablize all clock */ - mov r2, #0x10000 -1: subs r2, r2, #1 - bne 1b - - mov pc, lr - -internal_ram_init: - ldreq r0, =0xE3800000 - ldrne r0, =0xF1500000 - ldr r1, =0x0 - str r1, [r0] - - mov pc, lr - -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - /* set GPIO to enable UART0-UART4 */ - mov r0, r8 - ldr r1, =0x22222222 - str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET - ldr r1, =0x00002222 - str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET - - /* Check S5PC100 */ - cmp r7, r8 - bne 110f - - /* UART_SEL GPK0[5] at S5PC100 */ - add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET - ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET - bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit - orr r1, r1, #(0x1 << 20) @ Output - str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET - - ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET - bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit - orr r1, r1, #(0x2 << 10) @ Pull-up enabled - str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET - - ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET - orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit - str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET - - b 200f -110: - /* - * Note that the following address - * 0xE020'0360 is reserved address at S5PC100 - */ - /* UART_SEL MP0_5[7] at S5PC110 */ - add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET - ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET - bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit - orr r1, r1, #(0x1 << 28) @ Output - str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET - - ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET - bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit - orr r1, r1, #(0x2 << 14) @ Pull-up enabled - str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET - - ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit - str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET -200: - mov pc, lr diff --git a/qemu/roms/u-boot/board/samsung/goni/onenand.c b/qemu/roms/u-boot/board/samsung/goni/onenand.c deleted file mode 100644 index b74d8e8ac..000000000 --- a/qemu/roms/u-boot/board/samsung/goni/onenand.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2008-2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/onenand.h> -#include <linux/mtd/samsung_onenand.h> -#include <onenand_uboot.h> - -void onenand_board_init(struct mtd_info *mtd) -{ - struct onenand_chip *this = mtd->priv; - - this->base = (void *)CONFIG_SYS_ONENAND_BASE; - this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; - this->chip_probe = s5pc110_chip_probe; -} diff --git a/qemu/roms/u-boot/board/samsung/origen/Makefile b/qemu/roms/u-boot/board/samsung/origen/Makefile deleted file mode 100644 index 1add9fe62..000000000 --- a/qemu/roms/u-boot/board/samsung/origen/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (C) 2011 Samsung Electronics -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o - -hostprogs-y := tools/mkorigenspl -always := $(hostprogs-y) - -# omit -O2 option to suppress -# warning: dereferencing type-punned pointer will break strict-aliasing rules -# -# TODO: -# Fix the root cause in tools/mkorigenspl.c and delete the following work-around -$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS)) -else -obj-y += origen.o -endif diff --git a/qemu/roms/u-boot/board/samsung/origen/origen.c b/qemu/roms/u-boot/board/samsung/origen/origen.c deleted file mode 100644 index a539267a1..000000000 --- a/qemu/roms/u-boot/board/samsung/origen/origen.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <asm/arch/periph.h> -#include <asm/arch/pinmux.h> -#include <usb.h> - -DECLARE_GLOBAL_DATA_PTR; - -u32 get_board_rev(void) -{ - return 0; -} - -int exynos_init(void) -{ - return 0; -} - -int board_usb_init(int index, enum usb_init_type init) -{ - return 0; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int exynos_early_init_f(void) -{ - return 0; -} -#endif diff --git a/qemu/roms/u-boot/board/samsung/origen/tools/mkorigenspl.c b/qemu/roms/u-boot/board/samsung/origen/tools/mkorigenspl.c deleted file mode 100644 index 3ed20efce..000000000 --- a/qemu/roms/u-boot/board/samsung/origen/tools/mkorigenspl.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <stdio.h> -#include <stdlib.h> -#include <unistd.h> -#include <fcntl.h> -#include <errno.h> -#include <string.h> -#include <sys/stat.h> - -#define BUFSIZE (16*1024) -#define IMG_SIZE (16*1024) -#define SPL_HEADER_SIZE 16 -#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ - | S_IWGRP | S_IROTH | S_IWOTH) -#define SPL_HEADER "S5PC210 HEADER " -/* -* Requirement: -* IROM code reads first 14K bytes from boot device. -* It then calculates the checksum of 14K-4 bytes and compare with data at -* 14K-4 offset. -* -* This function takes two filenames: -* IN "u-boot-spl.bin" and -* OUT "$(BOARD)-spl.bin as filenames. -* It reads the "u-boot-spl.bin" in 16K buffer. -* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. -* It writes the buffer to "$(BOARD)-spl.bin" file. -*/ - -int main(int argc, char **argv) -{ - int i, len; - unsigned char buffer[BUFSIZE] = {0}; - int ifd, ofd; - unsigned int checksum = 0, count; - - if (argc != 3) { - printf(" %d Wrong number of arguments\n", argc); - exit(EXIT_FAILURE); - } - - ifd = open(argv[1], O_RDONLY); - if (ifd < 0) { - fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[1], strerror(errno)); - exit(EXIT_FAILURE); - } - - ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); - if (ifd < 0) { - fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[2], strerror(errno)); - if (ifd) - close(ifd); - exit(EXIT_FAILURE); - } - - len = lseek(ifd, 0, SEEK_END); - lseek(ifd, 0, SEEK_SET); - - memcpy(&buffer[0], SPL_HEADER, SPL_HEADER_SIZE); - - count = (len < (IMG_SIZE - SPL_HEADER_SIZE)) - ? len : (IMG_SIZE - SPL_HEADER_SIZE); - - if (read(ifd, buffer + SPL_HEADER_SIZE, count) != count) { - fprintf(stderr, "%s: Can't read %s: %s\n", - argv[0], argv[1], strerror(errno)); - - if (ifd) - close(ifd); - if (ofd) - close(ofd); - - exit(EXIT_FAILURE); - } - - for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++) - checksum += buffer[i+16]; - - *(ulong *)buffer ^= 0x1f; - *(ulong *)(buffer+4) ^= checksum; - - for (i = 1; i < SPL_HEADER_SIZE; i++) - buffer[i] ^= buffer[i-1]; - - if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { - fprintf(stderr, "%s: Can't write %s: %s\n", - argv[0], argv[2], strerror(errno)); - - if (ifd) - close(ifd); - if (ofd) - close(ofd); - - exit(EXIT_FAILURE); - } - - if (ifd) - close(ifd); - if (ofd) - close(ofd); - - return EXIT_SUCCESS; -} diff --git a/qemu/roms/u-boot/board/samsung/smdk2410/Makefile b/qemu/roms/u-boot/board/samsung/smdk2410/Makefile deleted file mode 100644 index 1939a217a..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk2410/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := smdk2410.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/samsung/smdk2410/lowlevel_init.S b/qemu/roms/u-boot/board/samsung/smdk2410/lowlevel_init.S deleted file mode 100644 index 5de04f10e..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk2410/lowlevel_init.S +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <config.h> -#include <version.h> - - -/* some parameters for the board */ - -/* - * - * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S - * - * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com> - * - */ - -#define BWSCON 0x48000000 - -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW32) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x0 /* 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 /* 0clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x0 /* 0clk */ -#define B3_Tacp 0x3 /* 6clk */ -#define B3_PMC 0x0 /* normal */ - -#define B4_Tacs 0x0 /* 0clk */ -#define B4_Tcos 0x0 /* 0clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x0 /* 0clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x0 /* 0clk */ -#define B5_Tacc 0x7 /* 14clk */ -#define B5_Tcoh 0x0 /* 0clk */ -#define B5_Tah 0x0 /* 0clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 -#define B6_SCAN 0x1 /* 9bit */ - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9bit */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ -/**************************************/ - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, =CONFIG_SYS_TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #13*4 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 - .word 0x30 - .word 0x30 diff --git a/qemu/roms/u-boot/board/samsung/smdk2410/smdk2410.c b/qemu/roms/u-boot/board/samsung/smdk2410/smdk2410.c deleted file mode 100644 index b75a0e34d..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk2410/smdk2410.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002, 2010 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/s3c24x0_cpu.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void pll_delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_early_init_f(void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - writel(0xFFFFFF, &clk_power->locktime); - - /* configure MPLL */ - writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, - &clk_power->mpllcon); - - /* some delay between MPLL and UPLL */ - pll_delay(4000); - - /* configure UPLL */ - writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, - &clk_power->upllcon); - - /* some delay between MPLL and UPLL */ - pll_delay(8000); - - /* set up the I/O ports */ - writel(0x007FFFFF, &gpio->gpacon); - writel(0x00044555, &gpio->gpbcon); - writel(0x000007FF, &gpio->gpbup); - writel(0xAAAAAAAA, &gpio->gpccon); - writel(0x0000FFFF, &gpio->gpcup); - writel(0xAAAAAAAA, &gpio->gpdcon); - writel(0x0000FFFF, &gpio->gpdup); - writel(0xAAAAAAAA, &gpio->gpecon); - writel(0x0000FFFF, &gpio->gpeup); - writel(0x000055AA, &gpio->gpfcon); - writel(0x000000FF, &gpio->gpfup); - writel(0xFF95FFBA, &gpio->gpgcon); - writel(0x0000FFFF, &gpio->gpgup); - writel(0x002AFAAA, &gpio->gphcon); - writel(0x000007FF, &gpio->gphup); - - return 0; -} - -int board_init(void) -{ - /* arch number of SMDK2410-Board */ - gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x30000100; - - icache_enable(); - dcache_enable(); - - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI AMD AM29LV800BB flash. - */ -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; -} diff --git a/qemu/roms/u-boot/board/samsung/smdk5250/Makefile b/qemu/roms/u-boot/board/samsung/smdk5250/Makefile deleted file mode 100644 index 6a586553e..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk5250/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (C) 2012 Samsung Electronics -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += smdk5250_spl.o - -ifndef CONFIG_SPL_BUILD -ifdef CONFIG_OF_CONTROL -obj-y += exynos5-dt.o -else -obj-y += smdk5250.o -endif -endif diff --git a/qemu/roms/u-boot/board/samsung/smdk5250/exynos5-dt.c b/qemu/roms/u-boot/board/samsung/smdk5250/exynos5-dt.c deleted file mode 100644 index 379a45cc2..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk5250/exynos5-dt.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <fdtdec.h> -#include <asm/io.h> -#include <errno.h> -#include <i2c.h> -#include <netdev.h> -#include <spi.h> -#include <asm/arch/cpu.h> -#include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/power.h> -#include <asm/arch/sromc.h> -#include <power/pmic.h> -#include <power/max77686_pmic.h> -#include <tmu.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) -{ - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); -} -#endif - -int exynos_init(void) -{ -#ifdef CONFIG_SOUND_MAX98095 - board_enable_audio_codec(); -#endif - return 0; -} - -#ifdef CONFIG_LCD -void exynos_cfg_lcd_gpio(void) -{ - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); - - /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); - - /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); -} - -void exynos_set_dp_phy(unsigned int onoff) -{ - set_dp_phy_ctrl(onoff); -} -#endif diff --git a/qemu/roms/u-boot/board/samsung/smdk5250/smdk5250.c b/qemu/roms/u-boot/board/samsung/smdk5250/smdk5250.c deleted file mode 100644 index 28a6d9e71..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk5250/smdk5250.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <cros_ec.h> -#include <fdtdec.h> -#include <asm/io.h> -#include <errno.h> -#include <i2c.h> -#include <lcd.h> -#include <netdev.h> -#include <spi.h> -#include <asm/arch/cpu.h> -#include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/power.h> -#include <asm/arch/sromc.h> -#include <asm/arch/dp_info.h> -#include <power/pmic.h> -#include <power/max77686_pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) -{ - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); -} -#endif - -int exynos_init(void) -{ -#ifdef CONFIG_SOUND_MAX98095 - board_enable_audio_codec(); -#endif - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - - /* Non-FDT configuration - bank number and timing parameters*/ - config.bank = CONFIG_ENV_SROM_BANK; - config.width = 2; - - config.timing[FDT_SROM_TACS] = 0x01; - config.timing[FDT_SROM_TCOS] = 0x01; - config.timing[FDT_SROM_TACC] = 0x06; - config.timing[FDT_SROM_TCOH] = 0x01; - config.timing[FDT_SROM_TAH] = 0x0C; - config.timing[FDT_SROM_TACP] = 0x09; - config.timing[FDT_SROM_PMC] = 0x01; - base_addr = CONFIG_SMC911X_BASE; - - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\ - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\ - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\ - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\ - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\ - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\ - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("\nBoard: SMDK5250\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int err, ret = 0, index, bus_width; - u32 base; - - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - ret |= err; - - /*EMMC: dwmmc Channel-0 with 8 bit bus width */ - index = 0; - base = samsung_get_base_mmc() + (0x10000 * index); - bus_width = 8; - err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); - if (err) - debug("dwmmc Channel-0 init failed\n"); - ret |= err; - - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - ret |= err; - - /*SD: dwmmc Channel-2 with 4 bit bus width */ - index = 2; - base = samsung_get_base_mmc() + (0x10000 * index); - bus_width = 4; - err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); - if (err) - debug("dwmmc Channel-2 init failed\n"); - ret |= err; - - return ret; -} -#endif - -void board_i2c_init(const void *blob) -{ - int i; - - for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) { - exynos_pinmux_config((PERIPH_ID_I2C0 + i), - PINMUX_FLAG_NONE); - } -} - -#if defined(CONFIG_POWER) -#ifdef CONFIG_POWER_MAX77686 -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -static int max77686_init(void) -{ - struct pmic *p; - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif /* CONFIG_POWER_MAX77686 */ - -int exynos_power_init(void) -{ - int ret = 0; - -#ifdef CONFIG_POWER_MAX77686 - ret = max77686_init(); -#endif - return ret; -} -#endif /* CONFIG_POWER */ - -#ifdef CONFIG_LCD -void exynos_cfg_lcd_gpio(void) -{ - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); - - /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); - - /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); -} - -void exynos_set_dp_phy(unsigned int onoff) -{ - set_dp_phy_ctrl(onoff); -} - -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 2560, - .vl_row = 1600, - .vl_width = 2560, - .vl_height = 1600, - .vl_clkp = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ - - /* wDP panel timing infomation */ - .vl_hspw = 32, - .vl_hbpd = 80, - .vl_hfpd = 48, - - .vl_vspw = 6, - .vl_vbpd = 37, - .vl_vfpd = 3, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .dp_enabled = 1, -}; - -static struct edp_device_info edp_info = { - .disp_info = { - .h_res = 2560, - .h_sync_width = 32, - .h_back_porch = 80, - .h_front_porch = 48, - .v_res = 1600, - .v_sync_width = 6, - .v_back_porch = 37, - .v_front_porch = 3, - .v_sync_rate = 60, - }, - .lt_info = { - .lt_status = DP_LT_NONE, - }, - .video_info = { - .master_mode = 0, - .bist_mode = DP_DISABLE, - .bist_pattern = NO_PATTERN, - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - }, -}; - -static struct exynos_dp_platform_data dp_platform_data = { - .edp_dev_info = &edp_info, -}; - -void init_panel_info(vidinfo_t *vid) -{ - vid->rgb_mode = MODE_RGB_P; - exynos_set_dp_platform_data(&dp_platform_data); -} -#endif diff --git a/qemu/roms/u-boot/board/samsung/smdk5250/smdk5250_spl.c b/qemu/roms/u-boot/board/samsung/smdk5250/smdk5250_spl.c deleted file mode 100644 index 7f3916a94..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk5250/smdk5250_spl.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/spl.h> -#include <asm/arch/clk.h> - -#define SIGNATURE 0xdeadbeef - -/* Parameters of early board initialization in SPL */ -static struct spl_machine_param machine_param - __attribute__((section(".machine_param"))) = { - .signature = SIGNATURE, - .version = 1, - .params = "vmubfasirM", - .size = sizeof(machine_param), - - .mem_iv_size = 0x1f, - .mem_type = DDR_MODE_DDR3, - - /* - * Set uboot_size to 0x100000 bytes. - * - * This is an overly conservative value chosen to accommodate all - * possible U-Boot image. You are advised to set this value to a - * smaller realistic size via scripts that modifies the .machine_param - * section of output U-Boot image. - */ - .uboot_size = 0x100000, - - .boot_source = BOOT_MODE_OM, - .frequency_mhz = 800, - .arm_freq_mhz = 1700, - .serial_base = 0x12c30000, - .i2c_base = 0x12c60000, - .mem_manuf = MEM_MANUF_SAMSUNG, -}; - -struct spl_machine_param *spl_get_machine_params(void) -{ - if (machine_param.signature != SIGNATURE) { - /* Will hang if SIGNATURE dont match */ - while (1) - ; - } - - return &machine_param; -} diff --git a/qemu/roms/u-boot/board/samsung/smdk5420/Makefile b/qemu/roms/u-boot/board/samsung/smdk5420/Makefile deleted file mode 100644 index c2f8886c9..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk5420/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (C) 2013 Samsung Electronics -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += smdk5420_spl.o - -ifndef CONFIG_SPL_BUILD -obj-y += smdk5420.o -endif diff --git a/qemu/roms/u-boot/board/samsung/smdk5420/smdk5420.c b/qemu/roms/u-boot/board/samsung/smdk5420/smdk5420.c deleted file mode 100644 index e4606ecd2..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk5420/smdk5420.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <fdtdec.h> -#include <asm/io.h> -#include <i2c.h> -#include <lcd.h> -#include <spi.h> -#include <asm/arch/board.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/dp_info.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_USB_EHCI_EXYNOS -static int board_usb_vbus_init(void) -{ - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - - /* Enable VBUS power switch */ - s5p_gpio_direction_output(&gpio1->x2, 6, 1); - - /* VBUS turn ON time */ - mdelay(3); - - return 0; -} -#endif - -int exynos_init(void) -{ -#ifdef CONFIG_USB_EHCI_EXYNOS - board_usb_vbus_init(); -#endif - return 0; -} - -#ifdef CONFIG_LCD -void cfg_lcd_gpio(void) -{ - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); - - /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); - - /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); -} - -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 2560, - .vl_row = 1600, - .vl_width = 2560, - .vl_height = 1600, - .vl_clkp = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ - - /* wDP panel timing infomation */ - .vl_hspw = 32, - .vl_hbpd = 80, - .vl_hfpd = 48, - - .vl_vspw = 6, - .vl_vbpd = 37, - .vl_vfpd = 3, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .cfg_gpio = cfg_lcd_gpio, - .backlight_on = NULL, - .lcd_power_on = NULL, - .reset_lcd = NULL, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .dp_enabled = 1, -}; - -static struct edp_device_info edp_info = { - .disp_info = { - .h_res = 2560, - .h_sync_width = 32, - .h_back_porch = 80, - .h_front_porch = 48, - .v_res = 1600, - .v_sync_width = 6, - .v_back_porch = 37, - .v_front_porch = 3, - .v_sync_rate = 60, - }, - .lt_info = { - .lt_status = DP_LT_NONE, - }, - .video_info = { - .master_mode = 0, - .bist_mode = DP_DISABLE, - .bist_pattern = NO_PATTERN, - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - }, -}; - -static struct exynos_dp_platform_data dp_platform_data = { - .phy_enable = set_dp_phy_ctrl, - .edp_dev_info = &edp_info, -}; - -void init_panel_info(vidinfo_t *vid) -{ - vid->rgb_mode = MODE_RGB_P; - - exynos_set_dp_platform_data(&dp_platform_data); -} -#endif - -int board_get_revision(void) -{ - return 0; -} diff --git a/qemu/roms/u-boot/board/samsung/smdk5420/smdk5420_spl.c b/qemu/roms/u-boot/board/samsung/smdk5420/smdk5420_spl.c deleted file mode 100644 index 73359f784..000000000 --- a/qemu/roms/u-boot/board/samsung/smdk5420/smdk5420_spl.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2013 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/spl.h> -#include <asm/arch/clk.h> - -#define SIGNATURE 0xdeadbeef - -/* Parameters of early board initialization in SPL */ -static struct spl_machine_param machine_param - __attribute__((section(".machine_param"))) = { - .signature = SIGNATURE, - .version = 1, - .params = "vmubfasirM", - .size = sizeof(machine_param), - - .mem_iv_size = 0x1f, - .mem_type = DDR_MODE_DDR3, - - /* - * Set uboot_size to 0x100000 bytes. - * - * This is an overly conservative value chosen to accommodate all - * possible U-Boot image. You are advised to set this value to a - * smaller realistic size via scripts that modifies the .machine_param - * section of output U-Boot image. - */ - .uboot_size = 0x100000, - - .boot_source = BOOT_MODE_OM, - .frequency_mhz = 800, - .arm_freq_mhz = 900, - .serial_base = 0x12c30000, - .i2c_base = 0x12c60000, - .mem_manuf = MEM_MANUF_SAMSUNG, -}; - -struct spl_machine_param *spl_get_machine_params(void) -{ - if (machine_param.signature != SIGNATURE) { - /* Will hang if SIGNATURE dont match */ - while (1) - ; - } - - return &machine_param; -} diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/Makefile b/qemu/roms/u-boot/board/samsung/smdkc100/Makefile deleted file mode 100644 index 0bcf4e5de..000000000 --- a/qemu/roms/u-boot/board/samsung/smdkc100/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := smdkc100.o -obj-$(CONFIG_SAMSUNG_ONENAND) += onenand.o -obj-y += lowlevel_init.o diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S b/qemu/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S deleted file mode 100644 index 65e6b7a73..000000000 --- a/qemu/roms/u-boot/board/samsung/smdkc100/lowlevel_init.S +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/cpu.h> -#include <asm/arch/power.h> - -/* - * Register usages: - * - * r5 has zero always - */ - - .globl lowlevel_init -lowlevel_init: - mov r9, lr - - /* r5 has always zero */ - mov r5, #0 - - ldr r8, =S5PC100_GPIO_BASE - - /* Disable Watchdog */ - ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000 - orr r0, r0, #0x0 - str r5, [r0] - - /* setting SRAM */ - ldr r0, =S5PC100_SROMC_BASE - ldr r1, =0x9 - str r1, [r0] - - /* S5PC100 has 3 groups of interrupt sources */ - ldr r0, =S5PC100_VIC0_BASE @0xE4000000 - ldr r1, =S5PC100_VIC1_BASE @0xE4000000 - ldr r2, =S5PC100_VIC2_BASE @0xE4000000 - - /* Disable all interrupts (VIC0, VIC1 and VIC2) */ - mvn r3, #0x0 - str r3, [r0, #0x14] @INTENCLEAR - str r3, [r1, #0x14] @INTENCLEAR - str r3, [r2, #0x14] @INTENCLEAR - - /* Set all interrupts as IRQ */ - str r5, [r0, #0xc] @INTSELECT - str r5, [r1, #0xc] @INTSELECT - str r5, [r2, #0xc] @INTSELECT - - /* Pending Interrupt Clear */ - str r5, [r0, #0xf00] @INTADDRESS - str r5, [r1, #0xf00] @INTADDRESS - str r5, [r2, #0xf00] @INTADDRESS - - /* for UART */ - bl uart_asm_init - - /* for TZPC */ - bl tzpc_asm_init - -1: - mov lr, r9 - mov pc, lr - -/* - * system_clock_init: Initialize core clock and bus clock. - * void system_clock_init(void) - */ -system_clock_init: - ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000 - - /* Set Clock divider */ - ldr r1, =0x00011110 - str r1, [r8, #0x304] - ldr r1, =0x1 - str r1, [r8, #0x308] - ldr r1, =0x00011301 - str r1, [r8, #0x300] - - /* Set Lock Time */ - ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 - str r1, [r8, #0x000] @ APLL_LOCK - str r1, [r8, #0x004] @ MPLL_LOCK - str r1, [r8, #0x008] @ EPLL_LOCK - str r1, [r8, #0x00C] @ HPLL_LOCK - - /* APLL_CON */ - ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz) - str r1, [r8, #0x100] - /* MPLL_CON */ - ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) - str r1, [r8, #0x104] - /* EPLL_CON */ - ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) - str r1, [r8, #0x108] - /* HPLL_CON */ - ldr r1, =0x80600603 - str r1, [r8, #0x10C] - - /* Set Source Clock */ - ldr r1, =0x1111 @ A, M, E, HPLL Muxing - str r1, [r8, #0x200] @ CLK_SRC0 - - ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing - str r1, [r8, #0x204] @ CLK_SRC1 - - ldr r1, =0x9000 @ ARMCLK/4 - str r1, [r8, #0x400] @ CLK_OUT - - /* wait at least 200us to stablize all clock */ - mov r2, #0x10000 -1: subs r2, r2, #1 - bne 1b - - mov pc, lr - -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - mov r0, r8 - ldr r1, =0x22222222 - str r1, [r0, #0x0] @ GPA0_CON - ldr r1, =0x00022222 - str r1, [r0, #0x20] @ GPA1_CON - - mov pc, lr - -/* - * tzpc_asm_init: Initialize TZPC - */ -tzpc_asm_init: - ldr r0, =0xE3800000 - mov r1, #0x0 - str r1, [r0] - mov r1, #0xff - str r1, [r0, #0x804] - str r1, [r0, #0x810] - - ldr r0, =0xE2800000 - str r1, [r0, #0x804] - str r1, [r0, #0x810] - str r1, [r0, #0x81C] - - ldr r0, =0xE2900000 - str r1, [r0, #0x804] - str r1, [r0, #0x810] - - mov pc, lr diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/onenand.c b/qemu/roms/u-boot/board/samsung/smdkc100/onenand.c deleted file mode 100644 index 577c1a546..000000000 --- a/qemu/roms/u-boot/board/samsung/smdkc100/onenand.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2008-2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/compat.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/onenand.h> -#include <linux/mtd/samsung_onenand.h> - -#include <onenand_uboot.h> - -#include <asm/io.h> -#include <asm/arch/clock.h> - -void onenand_board_init(struct mtd_info *mtd) -{ - struct onenand_chip *this = mtd->priv; - struct s5pc100_clock *clk = - (struct s5pc100_clock *)samsung_get_base_clock(); - struct samsung_onenand *onenand; - int value; - - this->base = (void *)S5PC100_ONENAND_BASE; - onenand = (struct samsung_onenand *)this->base; - - /* D0 Domain memory clock gating */ - value = readl(&clk->gate_d01); - value &= ~(1 << 2); /* CLK_ONENANDC */ - value |= (1 << 2); - writel(value, &clk->gate_d01); - - value = readl(&clk->src0); - value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ - value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ - writel(value, &clk->src0); - - value = readl(&clk->div1); - value &= ~(3 << 16); /* PCLKD1_RATIO */ - value |= (1 << 16); - writel(value, &clk->div1); - - writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset); - - while (!(readl(&onenand->int_err_stat) & RST_CMP)) - continue; - - writel(RST_CMP, &onenand->int_err_ack); - - /* - * Access_Clock [2:0] - * 166 MHz, 134 Mhz : 3 - * 100 Mhz, 60 Mhz : 2 - */ - writel(0x3, &onenand->acc_clock); - - writel(INT_ERR_ALL, &onenand->int_err_mask); - writel(1 << 0, &onenand->int_pin_en); /* Enable */ - - value = readl(&onenand->int_err_mask); - value &= ~RDY_ACT; - writel(value, &onenand->int_err_mask); - - s3c_onenand_init(mtd); -} diff --git a/qemu/roms/u-boot/board/samsung/smdkc100/smdkc100.c b/qemu/roms/u-boot/board/samsung/smdkc100/smdkc100.c deleted file mode 100644 index 860c851b2..000000000 --- a/qemu/roms/u-boot/board/samsung/smdkc100/smdkc100.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2008-2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sromc.h> -#include <asm/arch/gpio.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ -static void smc9115_pre_init(void) -{ - u32 smc_bw_conf, smc_bc_conf; - - struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)samsung_get_base_gpio(); - - /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); - - /* Ethernet needs bus width of 16 bits */ - smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); - smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe) - | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4) - | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0); - - /* Select and configure the SROMC bank */ - s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); -} - -int board_init(void) -{ - smc9115_pre_init(); - - gd->bd->bi_arch_number = MACH_TYPE_SMDKC100; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("Board:\tSMDKC100\n"); - return 0; -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/qemu/roms/u-boot/board/samsung/smdkv310/Makefile b/qemu/roms/u-boot/board/samsung/smdkv310/Makefile deleted file mode 100644 index de0da167b..000000000 --- a/qemu/roms/u-boot/board/samsung/smdkv310/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (C) 2011 Samsung Electronics -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o - -hostprogs-y := tools/mksmdkv310spl -always := $(hostprogs-y) -else -obj-y += smdkv310.o -endif diff --git a/qemu/roms/u-boot/board/samsung/smdkv310/smdkv310.c b/qemu/roms/u-boot/board/samsung/smdkv310/smdkv310.c deleted file mode 100644 index 81a306082..000000000 --- a/qemu/roms/u-boot/board/samsung/smdkv310/smdkv310.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <netdev.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <asm/arch/periph.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/sromc.h> - -DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; - -static void smc9115_pre_init(void) -{ - u32 smc_bw_conf, smc_bc_conf; - - /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); - - /* Ethernet needs bus width of 16 bits */ - smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); - smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F) - | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F) - | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F) - | SROMC_BC_PMC(0x0F); - - /* Select and configure the SROMC bank */ - s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); -} - -int board_init(void) -{ - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - smc9115_pre_init(); - - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) - + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) - + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ - PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ - PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ - PHYS_SDRAM_4_SIZE); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("\nBoard: SMDKV310\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); - - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); - } - err = s5p_mmc_init(2, 4); - return err; -} -#endif - -static int board_uart_init(void) -{ - int err; - - err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); - if (err) { - debug("UART0 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); - if (err) { - debug("UART1 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); - if (err) { - debug("UART2 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - if (err) { - debug("UART3 not configured\n"); - return err; - } - - return 0; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } - return err; -} -#endif diff --git a/qemu/roms/u-boot/board/samsung/smdkv310/tools/mksmdkv310spl.c b/qemu/roms/u-boot/board/samsung/smdkv310/tools/mksmdkv310spl.c deleted file mode 100644 index 9a64ca6ad..000000000 --- a/qemu/roms/u-boot/board/samsung/smdkv310/tools/mksmdkv310spl.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <stdio.h> -#include <stdlib.h> -#include <unistd.h> -#include <fcntl.h> -#include <errno.h> -#include <string.h> -#include <sys/stat.h> - -#define CHECKSUM_OFFSET (14*1024-4) -#define BUFSIZE (16*1024) -#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ - | S_IWGRP | S_IROTH | S_IWOTH) -/* -* Requirement: -* IROM code reads first 14K bytes from boot device. -* It then calculates the checksum of 14K-4 bytes and compare with data at -* 14K-4 offset. -* -* This function takes two filenames: -* IN "u-boot-spl.bin" and -* OUT "u-boot-mmc-spl.bin" as filenames. -* It reads the "u-boot-spl.bin" in 16K buffer. -* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. -* It writes the buffer to "u-boot-mmc-spl.bin" file. -*/ - -int main(int argc, char **argv) -{ - int i, len; - unsigned char buffer[BUFSIZE] = {0}; - int ifd, ofd; - unsigned int checksum = 0, count; - - if (argc != 3) { - printf(" %d Wrong number of arguments\n", argc); - exit(EXIT_FAILURE); - } - - ifd = open(argv[1], O_RDONLY); - if (ifd < 0) { - fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[1], strerror(errno)); - exit(EXIT_FAILURE); - } - - ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); - if (ifd < 0) { - fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[2], strerror(errno)); - if (ifd) - close(ifd); - exit(EXIT_FAILURE); - } - - len = lseek(ifd, 0, SEEK_END); - lseek(ifd, 0, SEEK_SET); - - count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET; - - if (read(ifd, buffer, count) != count) { - fprintf(stderr, "%s: Can't read %s: %s\n", - argv[0], argv[1], strerror(errno)); - - if (ifd) - close(ifd); - if (ofd) - close(ofd); - - exit(EXIT_FAILURE); - } - - for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++) - checksum += buffer[i]; - - memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum)); - - if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { - fprintf(stderr, "%s: Can't write %s: %s\n", - argv[0], argv[2], strerror(errno)); - - if (ifd) - close(ifd); - if (ofd) - close(ofd); - - exit(EXIT_FAILURE); - } - - if (ifd) - close(ifd); - if (ofd) - close(ofd); - - return EXIT_SUCCESS; -} diff --git a/qemu/roms/u-boot/board/samsung/trats/Makefile b/qemu/roms/u-boot/board/samsung/trats/Makefile deleted file mode 100644 index 5dc8a1f7d..000000000 --- a/qemu/roms/u-boot/board/samsung/trats/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2011 Samsung Electronics -# Heungjun Kim <riverful.kim@samsung.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += trats.o diff --git a/qemu/roms/u-boot/board/samsung/trats/setup.h b/qemu/roms/u-boot/board/samsung/trats/setup.h deleted file mode 100644 index 2f5ccb14c..000000000 --- a/qemu/roms/u-boot/board/samsung/trats/setup.h +++ /dev/null @@ -1,621 +0,0 @@ -/* - * Machine Specific Values for TRATS board based on EXYNOS4210 - * - * Copyright (C) 2011 Samsung Electronics - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TRATS_SETUP_H -#define _TRATS_SETUP_H - -#include <config.h> -#include <version.h> -#include <asm/arch/cpu.h> - -/* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */ -#define MUX_HPM_SEL_MOUTAPLL 0x0 -#define MUX_HPM_SEL_SCLKMPLL 0x1 -#define MUX_CORE_SEL_MOUTAPLL 0x0 -#define MUX_CORE_SEL_SCLKMPLL 0x1 -#define MUX_MPLL_SEL_FILPLL 0x0 -#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1 -#define MUX_APLL_SEL_FILPLL 0x0 -#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1 -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \ - | (MUX_CORE_SEL_MOUTAPLL << 16) \ - | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\ - | (MUX_APLL_SEL_MOUTMPLLFOUT << 0)) - -/* CLK_DIV_CPU0 */ -#define APLL_RATIO 0x0 -#define PCLK_DBG_RATIO 0x1 -#define ATB_RATIO 0x3 -#define PERIPH_RATIO 0x3 -#define COREM1_RATIO 0x7 -#define COREM0_RATIO 0x3 -#define CORE_RATIO 0x0 -#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (COREM1_RATIO << 8) \ - | (COREM0_RATIO << 4) \ - | (CORE_RATIO << 0)) - -/* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x0 -#define COPY_RATIO 0x3 -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) - -/* CLK_DIV_DMC0 */ -#define CORE_TIMERS_RATIO 0x1 -#define COPY2_RATIO 0x3 -#define DMCP_RATIO 0x1 -#define DMCD_RATIO 0x1 -#define DMC_RATIO 0x1 -#define DPHY_RATIO 0x1 -#define ACP_PCLK_RATIO 0x1 -#define ACP_RATIO 0x3 -#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ - | (COPY2_RATIO << 24) \ - | (DMCP_RATIO << 20) \ - | (DMCD_RATIO << 16) \ - | (DMC_RATIO << 12) \ - | (DPHY_RATIO << 8) \ - | (ACP_PCLK_RATIO << 4) \ - | (ACP_RATIO << 0)) - -/* CLK_DIV_DMC1 */ -#define DPM_RATIO 0x1 -#define DVSEM_RATIO 0x1 -#define PWI_RATIO 0x1 -#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ - | (DVSEM_RATIO << 16) \ - | (PWI_RATIO << 8)) - -/* CLK_SRC_TOP0 */ -#define MUX_ONENAND_SEL_ACLK_133 0x0 -#define MUX_ONENAND_SEL_ACLK_160 0x1 -#define MUX_ACLK_133_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_133_SEL_SCLKAPLL 0x1 -#define MUX_ACLK_160_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_160_SEL_SCLKAPLL 0x1 -#define MUX_ACLK_100_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_100_SEL_SCLKAPLL 0x1 -#define MUX_ACLK_200_SEL_SCLKMPLL 0x0 -#define MUX_ACLK_200_SEL_SCLKAPLL 0x1 -#define MUX_VPLL_SEL_FINPLL 0x0 -#define MUX_VPLL_SEL_FOUTVPLL 0x1 -#define MUX_EPLL_SEL_FINPLL 0x0 -#define MUX_EPLL_SEL_FOUTEPLL 0x1 -#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0 -#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1 -#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \ - | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \ - | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \ - | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \ - | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \ - | (MUX_VPLL_SEL_FOUTVPLL << 8) \ - | (MUX_EPLL_SEL_FOUTEPLL << 4) \ - | (MUX_ONENAND_1_SEL_MOUTONENAND << 0)) - -/* CLK_DIV_TOP */ -#define ONENAND_RATIO 0x0 -#define ACLK_133_RATIO 0x5 -#define ACLK_160_RATIO 0x4 -#define ACLK_100_RATIO 0x7 -#define ACLK_200_RATIO 0x3 -#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ - | (ACLK_133_RATIO << 12)\ - | (ACLK_160_RATIO << 8) \ - | (ACLK_100_RATIO << 4) \ - | (ACLK_200_RATIO << 0)) - -/* CLK_DIV_LEFTBUS */ -#define GPL_RATIO 0x1 -#define GDL_RATIO 0x3 -#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) - -/* CLK_DIV_RIGHTBUS */ -#define GPR_RATIO 0x1 -#define GDR_RATIO 0x3 -#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) - -/* CLK_SRS_FSYS: 6 = SCLKMPLL */ -#define SATA_SEL_SCLKMPLL 0 -#define SATA_SEL_SCLKAPLL 1 - -#define MMC_SEL_XXTI 0 -#define MMC_SEL_XUSBXTI 1 -#define MMC_SEL_SCLK_HDMI24M 2 -#define MMC_SEL_SCLK_USBPHY0 3 -#define MMC_SEL_SCLK_USBPHY1 4 -#define MMC_SEL_SCLK_HDMIPHY 5 -#define MMC_SEL_SCLKMPLL 6 -#define MMC_SEL_SCLKEPLL 7 -#define MMC_SEL_SCLKVPLL 8 - -#define MMCC0_SEL MMC_SEL_SCLKMPLL -#define MMCC1_SEL MMC_SEL_SCLKMPLL -#define MMCC2_SEL MMC_SEL_SCLKMPLL -#define MMCC3_SEL MMC_SEL_SCLKMPLL -#define MMCC4_SEL MMC_SEL_SCLKMPLL -#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \ - | (MMCC4_SEL << 16) \ - | (MMCC3_SEL << 12) \ - | (MMCC2_SEL << 8) \ - | (MMCC1_SEL << 4) \ - | (MMCC0_SEL << 0)) - -/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */ -/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */ -#define MMC0_RATIO 0xF -#define MMC0_PRE_RATIO 0x0 -#define MMC1_RATIO 0xF -#define MMC1_PRE_RATIO 0x0 -#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ - | (MMC1_RATIO << 16) \ - | (MMC0_PRE_RATIO << 8) \ - | (MMC0_RATIO << 0)) - -/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */ -#define MMC2_RATIO 0xF -#define MMC2_PRE_RATIO 0x0 -#define MMC3_RATIO 0xF -#define MMC3_PRE_RATIO 0x0 -#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ - | (MMC3_RATIO << 16) \ - | (MMC2_PRE_RATIO << 8) \ - | (MMC2_RATIO << 0)) - -/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */ -#define MMC4_RATIO 0xF -#define MMC4_PRE_RATIO 0x0 -#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ - | (MMC4_RATIO << 0)) - -/* CLK_SRC_PERIL0 */ -#define UART_SEL_XXTI 0 -#define UART_SEL_XUSBXTI 1 -#define UART_SEL_SCLK_HDMI24M 2 -#define UART_SEL_SCLK_USBPHY0 3 -#define UART_SEL_SCLK_USBPHY1 4 -#define UART_SEL_SCLK_HDMIPHY 5 -#define UART_SEL_SCLKMPLL 6 -#define UART_SEL_SCLKEPLL 7 -#define UART_SEL_SCLKVPLL 8 - -#define UART0_SEL UART_SEL_SCLKMPLL -#define UART1_SEL UART_SEL_SCLKMPLL -#define UART2_SEL UART_SEL_SCLKMPLL -#define UART3_SEL UART_SEL_SCLKMPLL -#define UART4_SEL UART_SEL_SCLKMPLL -#define UART5_SEL UART_SEL_SCLKMPLL -#define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \ - | (UART4_SEL << 12) \ - | (UART3_SEL << 12) \ - | (UART2_SEL << 8) \ - | (UART1_SEL << 4) \ - | (UART0_SEL << 0)) - -/* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */ -/* CLK_DIV_PERIL0 */ -#define UART0_RATIO 7 -#define UART1_RATIO 7 -#define UART2_RATIO 7 -#define UART3_RATIO 4 -#define UART4_RATIO 7 -#define UART5_RATIO 7 -#define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \ - | (UART4_RATIO << 12) \ - | (UART3_RATIO << 12) \ - | (UART2_RATIO << 8) \ - | (UART1_RATIO << 4) \ - | (UART0_RATIO << 0)) - -/* CLK_DIV_PERIL3 */ -#define SLIMBUS_RATIO 0x0 -#define PWM_RATIO 0x8 -#define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \ - | (PWM_RATIO << 0)) - -/* Required period to generate a stable clock output */ -/* PLL_LOCK_TIME */ -#define PLL_LOCKTIME 0x1C20 - -/* PLL Values */ -#define DISABLE 0 -#define ENABLE 1 -#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ - | (mdiv << 16) \ - | (pdiv << 8) \ - | (sdiv << 0)) - -/* APLL_CON0: 800MHz */ -#define APLL_MDIV 0xC8 -#define APLL_PDIV 0x6 -#define APLL_SDIV 0x1 -#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV) - -/* APLL_CON1 */ -#define APLL_AFC_ENB 0x1 -#define APLL_AFC 0x1C -#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0)) - -/* MPLL_CON0: 800MHz */ -#define MPLL_MDIV 0xC8 -#define MPLL_PDIV 0x6 -#define MPLL_SDIV 0x1 -#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) - -/* MPLL_CON1 */ -#define MPLL_AFC_ENB 0x1 -#define MPLL_AFC 0x1C -#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) - -/* EPLL_CON0: 96MHz */ -#define EPLL_MDIV 0x30 -#define EPLL_PDIV 0x3 -#define EPLL_SDIV 0x2 -#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) - -/* EPLL_CON1 */ -#define EPLL_K 0x0 -#define EPLL_CON1_VAL (EPLL_K >> 0) - -/* VPLL_CON0: 108MHz */ -#define VPLL_MDIV 0x35 -#define VPLL_PDIV 0x3 -#define VPLL_SDIV 0x2 -#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) - -/* VPLL_CON1 */ -#define VPLL_SSCG_EN DISABLE -#define VPLL_SEL_PF_DN_SPREAD 0x0 -#define VPLL_MRR 0x11 -#define VPLL_MFR 0x0 -#define VPLL_K 0x400 -#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\ - | (VPLL_SEL_PF_DN_SPREAD << 29) \ - | (VPLL_MRR << 24) \ - | (VPLL_MFR << 16) \ - | (VPLL_K << 0)) - -/* CLOCK GATE */ -#define CLK_DIS 0x0 -#define CLK_EN 0x1 - -#define BIT_CAM_CLK_PIXELASYNCM1 18 -#define BIT_CAM_CLK_PIXELASYNCM0 17 -#define BIT_CAM_CLK_PPMUCAMIF 16 -#define BIT_CAM_CLK_QEFIMC3 15 -#define BIT_CAM_CLK_QEFIMC2 14 -#define BIT_CAM_CLK_QEFIMC1 13 -#define BIT_CAM_CLK_QEFIMC0 12 -#define BIT_CAM_CLK_SMMUJPEG 11 -#define BIT_CAM_CLK_SMMUFIMC3 10 -#define BIT_CAM_CLK_SMMUFIMC2 9 -#define BIT_CAM_CLK_SMMUFIMC1 8 -#define BIT_CAM_CLK_SMMUFIMC0 7 -#define BIT_CAM_CLK_JPEG 6 -#define BIT_CAM_CLK_CSIS1 5 -#define BIT_CAM_CLK_CSIS0 4 -#define BIT_CAM_CLK_FIMC3 3 -#define BIT_CAM_CLK_FIMC2 2 -#define BIT_CAM_CLK_FIMC1 1 -#define BIT_CAM_CLK_FIMC0 0 -#define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\ - | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\ - | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\ - | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\ - | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\ - | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\ - | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\ - | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\ - | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\ - | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\ - | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\ - | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\ - | (CLK_EN << BIT_CAM_CLK_JPEG)\ - | (CLK_EN << BIT_CAM_CLK_CSIS1)\ - | (CLK_EN << BIT_CAM_CLK_CSIS0)\ - | (CLK_EN << BIT_CAM_CLK_FIMC3)\ - | (CLK_EN << BIT_CAM_CLK_FIMC2)\ - | (CLK_EN << BIT_CAM_CLK_FIMC1)\ - | (CLK_EN << BIT_CAM_CLK_FIMC0)) -#define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN - -#define BIT_VP_CLK_PPMUTV 5 -#define BIT_VP_CLK_SMMUTV 4 -#define BIT_VP_CLK_HDMI 3 -#define BIT_VP_CLK_TVENC 2 -#define BIT_VP_CLK_MIXER 1 -#define BIT_VP_CLK_VP 0 -#define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\ - | (CLK_EN << BIT_VP_CLK_SMMUTV)\ - | (CLK_EN << BIT_VP_CLK_HDMI)\ - | (CLK_EN << BIT_VP_CLK_TVENC)\ - | (CLK_EN << BIT_VP_CLK_MIXER)\ - | (CLK_EN << BIT_VP_CLK_VP)) -#define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN - -#define BIT_MFC_CLK_PPMUMFC_R 4 -#define BIT_MFC_CLK_PPMUMFC_L 3 -#define BIT_MFC_CLK_SMMUMFC_R 2 -#define BIT_MFC_CLK_SMMUMFC_L 1 -#define BIT_MFC_CLK_MFC 0 -#define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\ - | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\ - | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\ - | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\ - | (CLK_EN << BIT_MFC_CLK_MFC)) -#define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN - -#define BIT_G3D_CLK_QEG3D 2 -#define BIT_G3D_CLK_PPMUG3D 1 -#define BIT_G3D_CLK_G3D 0 -#define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\ - | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\ - | (CLK_EN << BIT_G3D_CLK_G3D)) -#define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN - -#define BIT_IMAGE_CLK_PPMUIMAGE 9 -#define BIT_IMAGE_CLK_QEMDMA 8 -#define BIT_IMAGE_CLK_QEROTATOR 7 -#define BIT_IMAGE_CLK_QEG2D 6 -#define BIT_IMAGE_CLK_SMMUMDMA 5 -#define BIT_IMAGE_CLK_SMMUROTATOR 4 -#define BIT_IMAGE_CLK_SMMUG2D 3 -#define BIT_IMAGE_CLK_MDMA 2 -#define BIT_IMAGE_CLK_ROTATOR 1 -#define BIT_IMAGE_CLK_G2D 0 -#define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\ - | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\ - | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\ - | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\ - | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\ - | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\ - | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\ - | (CLK_EN << BIT_IMAGE_CLK_MDMA)\ - | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\ - | (CLK_EN << BIT_IMAGE_CLK_G2D)) -#define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN - -#define BIT_LCD0_CLK_PPMULCD0 5 -#define BIT_LCD0_CLK_SMMUFIMD0 4 -#define BIT_LCD0_CLK_DSIM0 3 -#define BIT_LCD0_CLK_MDNIE0 2 -#define BIT_LCD0_CLK_MIE0 1 -#define BIT_LCD0_CLK_FIMD0 0 -#define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\ - | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\ - | (CLK_EN << BIT_LCD0_CLK_DSIM0)\ - | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\ - | (CLK_EN << BIT_LCD0_CLK_MIE0)\ - | (CLK_EN << BIT_LCD0_CLK_FIMD0)) -#define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN - -#define BIT_LCD1_CLK_PPMULCD1 5 -#define BIT_LCD1_CLK_SMMUFIMD1 4 -#define BIT_LCD1_CLK_DSIM1 3 -#define BIT_LCD1_CLK_MDNIE1 2 -#define BIT_LCD1_CLK_MIE1 1 -#define BIT_LCD1_CLK_FIMD1 0 -#define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\ - | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\ - | (CLK_EN << BIT_LCD1_CLK_DSIM1)\ - | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\ - | (CLK_EN << BIT_LCD1_CLK_MIE1)\ - | (CLK_EN << BIT_LCD1_CLK_FIMD1)) -#define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN - -#define BIT_FSYS_CLK_SMMUPCIE 18 -#define BIT_FSYS_CLK_PPMUFILE 17 -#define BIT_FSYS_CLK_NFCON 16 -#define BIT_FSYS_CLK_ONENAND 15 -#define BIT_FSYS_CLK_PCIE 14 -#define BIT_FSYS_CLK_USBDEVICE 13 -#define BIT_FSYS_CLK_USBHOST 12 -#define BIT_FSYS_CLK_SROMC 11 -#define BIT_FSYS_CLK_SATA 10 -#define BIT_FSYS_CLK_SDMMC4 9 -#define BIT_FSYS_CLK_SDMMC3 8 -#define BIT_FSYS_CLK_SDMMC2 7 -#define BIT_FSYS_CLK_SDMMC1 6 -#define BIT_FSYS_CLK_SDMMC0 5 -#define BIT_FSYS_CLK_TSI 4 -#define BIT_FSYS_CLK_SATAPHY 3 -#define BIT_FSYS_CLK_PCIEPHY 2 -#define BIT_FSYS_CLK_PDMA1 1 -#define BIT_FSYS_CLK_PDMA0 0 -#define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\ - | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\ - | (CLK_EN << BIT_FSYS_CLK_NFCON)\ - | (CLK_EN << BIT_FSYS_CLK_ONENAND)\ - | (CLK_EN << BIT_FSYS_CLK_PCIE)\ - | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\ - | (CLK_EN << BIT_FSYS_CLK_USBHOST)\ - | (CLK_EN << BIT_FSYS_CLK_SROMC)\ - | (CLK_EN << BIT_FSYS_CLK_SATA)\ - | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\ - | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\ - | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\ - | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\ - | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\ - | (CLK_EN << BIT_FSYS_CLK_TSI)\ - | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\ - | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\ - | (CLK_EN << BIT_FSYS_CLK_PDMA1)\ - | (CLK_EN << BIT_FSYS_CLK_PDMA0)) -#define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN - -#define BIT_GPS_CLK_SMMUGPS 1 -#define BIT_GPS_CLK_GPS 0 -#define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\ - | (CLK_EN << BIT_GPS_CLK_GPS)) -#define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN - -#define BIT_PERIL_CLK_MODEMIF 28 -#define BIT_PERIL_CLK_AC97 27 -#define BIT_PERIL_CLK_SPDIF 26 -#define BIT_PERIL_CLK_SLIMBUS 25 -#define BIT_PERIL_CLK_PWM 24 -#define BIT_PERIL_CLK_PCM2 23 -#define BIT_PERIL_CLK_PCM1 22 -#define BIT_PERIL_CLK_I2S2 21 -#define BIT_PERIL_CLK_I2S1 20 -#define BIT_PERIL_CLK_RESERVED0 19 -#define BIT_PERIL_CLK_SPI2 18 -#define BIT_PERIL_CLK_SPI1 17 -#define BIT_PERIL_CLK_SPI0 16 -#define BIT_PERIL_CLK_TSADC 15 -#define BIT_PERIL_CLK_I2CHDMI 14 -#define BIT_PERIL_CLK_I2C7 13 -#define BIT_PERIL_CLK_I2C6 12 -#define BIT_PERIL_CLK_I2C5 11 -#define BIT_PERIL_CLK_I2C4 10 -#define BIT_PERIL_CLK_I2C3 9 -#define BIT_PERIL_CLK_I2C2 8 -#define BIT_PERIL_CLK_I2C1 7 -#define BIT_PERIL_CLK_I2C0 6 -#define BIT_PERIL_CLK_RESERVED1 5 -#define BIT_PERIL_CLK_UART4 4 -#define BIT_PERIL_CLK_UART3 3 -#define BIT_PERIL_CLK_UART2 2 -#define BIT_PERIL_CLK_UART1 1 -#define BIT_PERIL_CLK_UART0 0 -#define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\ - | (CLK_EN << BIT_PERIL_CLK_AC97)\ - | (CLK_EN << BIT_PERIL_CLK_SPDIF)\ - | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\ - | (CLK_EN << BIT_PERIL_CLK_PWM)\ - | (CLK_EN << BIT_PERIL_CLK_PCM2)\ - | (CLK_EN << BIT_PERIL_CLK_PCM1)\ - | (CLK_EN << BIT_PERIL_CLK_I2S2)\ - | (CLK_EN << BIT_PERIL_CLK_I2S1)\ - | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\ - | (CLK_EN << BIT_PERIL_CLK_SPI2)\ - | (CLK_EN << BIT_PERIL_CLK_SPI1)\ - | (CLK_EN << BIT_PERIL_CLK_SPI0)\ - | (CLK_EN << BIT_PERIL_CLK_TSADC)\ - | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\ - | (CLK_EN << BIT_PERIL_CLK_I2C7)\ - | (CLK_EN << BIT_PERIL_CLK_I2C6)\ - | (CLK_EN << BIT_PERIL_CLK_I2C5)\ - | (CLK_EN << BIT_PERIL_CLK_I2C4)\ - | (CLK_EN << BIT_PERIL_CLK_I2C3)\ - | (CLK_EN << BIT_PERIL_CLK_I2C2)\ - | (CLK_EN << BIT_PERIL_CLK_I2C1)\ - | (CLK_EN << BIT_PERIL_CLK_I2C0)\ - | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\ - | (CLK_EN << BIT_PERIL_CLK_UART4)\ - | (CLK_EN << BIT_PERIL_CLK_UART3)\ - | (CLK_EN << BIT_PERIL_CLK_UART2)\ - | (CLK_EN << BIT_PERIL_CLK_UART1)\ - | (CLK_EN << BIT_PERIL_CLK_UART0)) -#define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN - -#define BIT_PERIR_CLK_TMU_APBIF 17 -#define BIT_PERIR_CLK_KEYIF 16 -#define BIT_PERIR_CLK_RTC 15 -#define BIT_PERIR_CLK_WDT 14 -#define BIT_PERIR_CLK_MCT 13 -#define BIT_PERIR_CLK_SECKEY 12 -#define BIT_PERIR_CLK_HDMI_CEC 11 -#define BIT_PERIR_CLK_TZPC5 10 -#define BIT_PERIR_CLK_TZPC4 9 -#define BIT_PERIR_CLK_TZPC3 8 -#define BIT_PERIR_CLK_TZPC2 7 -#define BIT_PERIR_CLK_TZPC1 6 -#define BIT_PERIR_CLK_TZPC0 5 -#define BIT_PERIR_CLK_CMU_DMCPART 4 -#define BIT_PERIR_CLK_RESERVED 3 -#define BIT_PERIR_CLK_CMU_APBIF 2 -#define BIT_PERIR_CLK_SYSREG 1 -#define BIT_PERIR_CLK_CHIP_ID 0 -#define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\ - | (CLK_EN << BIT_PERIR_CLK_KEYIF)\ - | (CLK_EN << BIT_PERIR_CLK_RTC)\ - | (CLK_EN << BIT_PERIR_CLK_WDT)\ - | (CLK_EN << BIT_PERIR_CLK_MCT)\ - | (CLK_EN << BIT_PERIR_CLK_SECKEY)\ - | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\ - | (CLK_EN << BIT_PERIR_CLK_TZPC5)\ - | (CLK_EN << BIT_PERIR_CLK_TZPC4)\ - | (CLK_EN << BIT_PERIR_CLK_TZPC3)\ - | (CLK_EN << BIT_PERIR_CLK_TZPC2)\ - | (CLK_EN << BIT_PERIR_CLK_TZPC1)\ - | (CLK_EN << BIT_PERIR_CLK_TZPC0)\ - | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\ - | (CLK_EN << BIT_PERIR_CLK_RESERVED)\ - | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\ - | (CLK_EN << BIT_PERIR_CLK_SYSREG)\ - | (CLK_EN << BIT_PERIR_CLK_CHIP_ID)) -#define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN - -#define BIT_BLOCK_CLK_GPS 7 -#define BIT_BLOCK_CLK_RESERVED 6 -#define BIT_BLOCK_CLK_LCD1 5 -#define BIT_BLOCK_CLK_LCD0 4 -#define BIT_BLOCK_CLK_G3D 3 -#define BIT_BLOCK_CLK_MFC 2 -#define BIT_BLOCK_CLK_TV 1 -#define BIT_BLOCK_CLK_CAM 0 -#define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\ - | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\ - | (CLK_EN << BIT_BLOCK_CLK_LCD1)\ - | (CLK_EN << BIT_BLOCK_CLK_LCD0)\ - | (CLK_EN << BIT_BLOCK_CLK_G3D)\ - | (CLK_EN << BIT_BLOCK_CLK_MFC)\ - | (CLK_EN << BIT_BLOCK_CLK_TV)\ - | (CLK_EN << BIT_BLOCK_CLK_CAM)) -#define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN - -/* - * GATE CAM : All block - * GATE VP : All block - * GATE MFC : All block - * GATE G3D : All block - * GATE IMAGE : All block - * GATE LCD0 : All block - * GATE LCD1 : All block - * GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE - * GATE GPS : All block - * GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97 - * GATE PERI Right : All Enable, Block - KEYIF - * GATE Block : All block - */ -#define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS -#define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS -#define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS -#define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS -#define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS -#define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS -#define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS -#define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \ - | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\ - | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\ - | (CLK_EN << BIT_FSYS_CLK_USBHOST)\ - | (CLK_EN << BIT_FSYS_CLK_SROMC)\ - | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\ - | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\ - | (CLK_EN << BIT_FSYS_CLK_PDMA1)\ - | (CLK_EN << BIT_FSYS_CLK_PDMA0)) -#define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS -#define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \ - | ~((CLK_EN << BIT_PERIL_CLK_AC97)\ - | (CLK_EN << BIT_PERIL_CLK_SPDIF)\ - | (CLK_EN << BIT_PERIL_CLK_I2C2)\ - | (CLK_EN << BIT_PERIL_CLK_SLIMBUS))) -#define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \ - | ~((CLK_EN << BIT_PERIR_CLK_KEYIF))) -#define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS - -/* PS_HOLD: Data Hight, Output En */ -#define BIT_DAT 8 -#define BIT_EN 9 -#define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN) - -#endif diff --git a/qemu/roms/u-boot/board/samsung/trats/trats.c b/qemu/roms/u-boot/board/samsung/trats/trats.c deleted file mode 100644 index ab0ad1d65..000000000 --- a/qemu/roms/u-boot/board/samsung/trats/trats.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * Heungjun Kim <riverful.kim@samsung.com> - * Kyungmin Park <kyungmin.park@samsung.com> - * Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <lcd.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/clock.h> -#include <asm/arch/mipi_dsim.h> -#include <asm/arch/watchdog.h> -#include <asm/arch/power.h> -#include <power/pmic.h> -#include <usb/s3c_udc.h> -#include <power/max8997_pmic.h> -#include <power/max8997_muic.h> -#include <power/battery.h> -#include <power/max17042_fg.h> -#include <libtizen.h> -#include <usb.h> -#include <usb_mass_storage.h> - -#include "setup.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int board_rev; - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - return board_rev; -} -#endif - -static void check_hw_revision(void); -struct s3c_plat_otg_data s5pc210_otg_data; - -int exynos_init(void) -{ - check_hw_revision(); - printf("HW Revision:\t0x%x\n", board_rev); - - return 0; -} - -void i2c_init_board(void) -{ - int err; - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* I2C_5 -> PMIC */ - err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE); - if (err) { - debug("I2C%d not configured\n", (I2C_5)); - return; - } - - /* I2C_8 -> FG */ - s5p_gpio_direction_output(&gpio2->y4, 0, 1); - s5p_gpio_direction_output(&gpio2->y4, 1, 1); -} - -static void trats_low_power_mode(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - struct exynos4_power *pwr = - (struct exynos4_power *)samsung_get_base_power(); - - /* Power down CORE1 */ - /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ - writel(0x0, &pwr->arm_core1_configuration); - - /* Change the APLL frequency */ - /* ENABLE (1 enable) | LOCKED (1 locked) */ - /* [31] | [29] */ - /* FSEL | MDIV | PDIV | SDIV */ - /* [27] | [25:16] | [13:8] | [2:0] */ - writel(0xa0c80604, &clk->apll_con0); - - /* Change CPU0 clock divider */ - /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ - /* [30:28] | [26:24] | [22:20] | [18:16] */ - /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ - /* [14:12] | [10:8] | [6:4] | [2:0] */ - writel(0x00000100, &clk->div_cpu0); - - /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ - while (readl(&clk->div_stat_cpu0) & 0x1111111) - continue; - - /* Change clock divider ratio for DMC */ - /* DMCP_RATIO | DMCD_RATIO */ - /* [22:20] | [18:16] */ - /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ - /* [14:12] | [10:8] | [6:4] | [2:0] */ - writel(0x13113117, &clk->div_dmc0); - - /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ - while (readl(&clk->div_stat_dmc0) & 0x11111111) - continue; - - /* Turn off unnecessary power domains */ - writel(0x0, &pwr->xxti_configuration); /* XXTI */ - writel(0x0, &pwr->cam_configuration); /* CAM */ - writel(0x0, &pwr->tv_configuration); /* TV */ - writel(0x0, &pwr->mfc_configuration); /* MFC */ - writel(0x0, &pwr->g3d_configuration); /* G3D */ - writel(0x0, &pwr->gps_configuration); /* GPS */ - writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ - - /* Turn off unnecessary clocks */ - writel(0x0, &clk->gate_ip_cam); /* CAM */ - writel(0x0, &clk->gate_ip_tv); /* TV */ - writel(0x0, &clk->gate_ip_mfc); /* MFC */ - writel(0x0, &clk->gate_ip_g3d); /* G3D */ - writel(0x0, &clk->gate_ip_image); /* IMAGE */ - writel(0x0, &clk->gate_ip_gps); /* GPS */ -} - -static int pmic_init_max8997(void) -{ - struct pmic *p = pmic_get("MAX8997_PMIC"); - int i = 0, ret = 0; - u32 val; - - if (pmic_probe(p)) - return -1; - - /* BUCK1 VARM: 1.2V */ - val = (1200000 - 650000) / 25000; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val); - val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val); - - /* BUCK2 VINT: 1.1V */ - val = (1100000 - 650000) / 25000; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val); - val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val); - - - /* BUCK3 G3D: 1.1V - OFF */ - ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val); - val &= ~ENBUCK; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val); - - val = (1100000 - 750000) / 50000; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val); - - /* BUCK4 CAMISP: 1.2V - OFF */ - ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val); - val &= ~ENBUCK; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val); - - val = (1200000 - 650000) / 25000; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val); - - /* BUCK5 VMEM: 1.2V */ - val = (1200000 - 650000) / 25000; - for (i = 0; i < 8; i++) - ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val); - - val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val); - - /* BUCK6 CAM AF: 2.8V */ - /* No Voltage Setting Register */ - /* GNSLCT 3.0X */ - val = GNSLCT; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val); - - /* BUCK7 VCC_SUB: 2.0V */ - val = (2000000 - 750000) / 50000; - ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val); - - /* LDO1 VADC: 3.3V */ - val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val); - - /* LDO1 Disable active discharging */ - ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val); - val &= ~LDO_ADE; - ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val); - - /* LDO2 VALIVE: 1.1V */ - val = max8997_reg_ldo(1100000) | EN_LDO; - ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val); - - /* LDO3 VUSB/MIPI: 1.1V */ - val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val); - - /* LDO4 VMIPI: 1.8V */ - val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val); - - /* LDO5 VHSIC: 1.2V */ - val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val); - - /* LDO6 VCC_1.8V_PDA: 1.8V */ - val = max8997_reg_ldo(1800000) | EN_LDO; - ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val); - - /* LDO7 CAM_ISP: 1.8V */ - val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val); - - /* LDO8 VDAC/VUSB: 3.3V */ - val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val); - - /* LDO9 VCC_2.8V_PDA: 2.8V */ - val = max8997_reg_ldo(2800000) | EN_LDO; - ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val); - - /* LDO10 VPLL: 1.1V */ - val = max8997_reg_ldo(1100000) | EN_LDO; - ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val); - - /* LDO11 TOUCH: 2.8V */ - val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val); - - /* LDO12 VTCAM: 1.8V */ - val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val); - - /* LDO13 VCC_3.0_LCD: 3.0V */ - val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val); - - /* LDO14 MOTOR: 3.0V */ - val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val); - - /* LDO15 LED_A: 2.8V */ - val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val); - - /* LDO16 CAM_SENSOR: 1.8V */ - val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val); - - /* LDO17 VTF: 2.8V */ - val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val); - - /* LDO18 TOUCH_LED 3.3V */ - val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val); - - /* LDO21 VDDQ: 1.2V */ - val = max8997_reg_ldo(1200000) | EN_LDO; - ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val); - - /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */ - val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) | - ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2; - ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val); - - if (ret) { - puts("MAX8997 PMIC setting error!\n"); - return -1; - } - return 0; -} - -int exynos_power_init(void) -{ - int chrg, ret; - struct power_battery *pb; - struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; - - /* - * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected - * to logical I2C adapter 0 - * - * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected - * to logical I2C adapter 1 - */ - ret = pmic_init(I2C_5); - ret |= pmic_init_max8997(); - ret |= power_fg_init(I2C_9); - ret |= power_muic_init(I2C_5); - ret |= power_bat_init(0); - if (ret) - return ret; - - p_fg = pmic_get("MAX17042_FG"); - if (!p_fg) { - puts("MAX17042_FG: Not found\n"); - return -ENODEV; - } - - p_chrg = pmic_get("MAX8997_PMIC"); - if (!p_chrg) { - puts("MAX8997_PMIC: Not found\n"); - return -ENODEV; - } - - p_muic = pmic_get("MAX8997_MUIC"); - if (!p_muic) { - puts("MAX8997_MUIC: Not found\n"); - return -ENODEV; - } - - p_bat = pmic_get("BAT_TRATS"); - if (!p_bat) { - puts("BAT_TRATS: Not found\n"); - return -ENODEV; - } - - p_fg->parent = p_bat; - p_chrg->parent = p_bat; - p_muic->parent = p_bat; - - p_bat->low_power_mode = trats_low_power_mode; - p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); - - pb = p_bat->pbat; - chrg = p_muic->chrg->chrg_type(p_muic); - debug("CHARGER TYPE: %d\n", chrg); - - if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { - puts("No battery detected\n"); - return -1; - } - - p_fg->fg->fg_battery_check(p_fg, p_bat); - - if (pb->bat->state == CHARGE && chrg == CHARGER_USB) - puts("CHARGE Battery !\n"); - - return 0; -} - -static unsigned int get_hw_revision(void) -{ - struct exynos4_gpio_part1 *gpio = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - int hwrev = 0; - int i; - - /* hw_rev[3:0] == GPE1[3:0] */ - for (i = 0; i < 4; i++) { - s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); - } - - udelay(1); - - for (i = 0; i < 4; i++) - hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); - - debug("hwrev 0x%x\n", hwrev); - - return hwrev; -} - -static void check_hw_revision(void) -{ - int hwrev; - - hwrev = get_hw_revision(); - - board_rev |= hwrev; -} - - -#ifdef CONFIG_USB_GADGET -static int s5pc210_phy_control(int on) -{ - int ret = 0; - u32 val = 0; - struct pmic *p = pmic_get("MAX8997_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (on) { - ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, - ENSAFEOUT1, LDO_ON); - ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); - - ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); - } else { - ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); - - ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); - ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, - ENSAFEOUT1, LDO_OFF); - } - - if (ret) { - puts("MAX8997 LDO setting error!\n"); - return -1; - } - - return 0; -} - -struct s3c_plat_otg_data s5pc210_otg_data = { - .phy_control = s5pc210_phy_control, - .regs_phy = EXYNOS4_USBPHY_BASE, - .regs_otg = EXYNOS4_USBOTG_BASE, - .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, - .usb_flags = PHY0_SLEEP, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - struct pmic *muic = pmic_get("MAX8997_MUIC"); - if (!muic) - return 0; - - return !!muic->chrg->chrg_type(muic); -} -#endif - -static void pmic_reset(void) -{ - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio->x0, 7, 1); - s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); -} - -static void board_clock_init(void) -{ - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - - writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); - writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); - writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); - writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); - - writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); - writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); - writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); - writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); - writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); - writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); - writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); - writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); - writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); - writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); - writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); - writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); - - writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); - writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); - writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); - writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); - writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); - writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); - writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); - writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); - writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); - writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); - writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); - writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); - - writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); - writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); - writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); - writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); - writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); - writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); - writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); - writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); - writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); - writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); - writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); - writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); -} - -static void board_power_init(void) -{ - struct exynos4_power *pwr = - (struct exynos4_power *)samsung_get_base_power(); - - /* PS HOLD */ - writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); - - /* Set power down */ - writel(0, (unsigned int)&pwr->cam_configuration); - writel(0, (unsigned int)&pwr->tv_configuration); - writel(0, (unsigned int)&pwr->mfc_configuration); - writel(0, (unsigned int)&pwr->g3d_configuration); - writel(0, (unsigned int)&pwr->lcd1_configuration); - writel(0, (unsigned int)&pwr->gps_configuration); - writel(0, (unsigned int)&pwr->gps_alive_configuration); - - /* It is necessary to power down core 1 */ - /* to successfully boot CPU1 in kernel */ - writel(0, (unsigned int)&pwr->arm_core1_configuration); -} - -static void exynos_uart_init(void) -{ - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); - s5p_gpio_direction_output(&gpio2->y4, 7, 1); -} - -int exynos_early_init_f(void) -{ - wdt_stop(); - pmic_reset(); - board_clock_init(); - exynos_uart_init(); - board_power_init(); - - return 0; -} - -void exynos_reset_lcd(void) -{ - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio2->y4, 5, 1); - udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 0); - udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 1); -} - -int lcd_power(void) -{ - int ret = 0; - struct pmic *p = pmic_get("MAX8997_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return 0; - - /* LDO15 voltage: 2.2v */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); - /* LDO13 voltage: 3.0v */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); - - if (ret) { - puts("MAX8997 LDO setting error!\n"); - return -1; - } - - return 0; -} - -int mipi_power(void) -{ - int ret = 0; - struct pmic *p = pmic_get("MAX8997_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return 0; - - /* LDO3 voltage: 1.1v */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); - /* LDO4 voltage: 1.8v */ - ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); - - if (ret) { - puts("MAX8997 LDO setting error!\n"); - return -1; - } - - return 0; -} - -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif -#ifdef CONFIG_S6E8AX0 - s6e8ax0_init(); - setenv("lcdinfo", "lcd=s6e8ax0"); -#endif -} diff --git a/qemu/roms/u-boot/board/samsung/trats2/Makefile b/qemu/roms/u-boot/board/samsung/trats2/Makefile deleted file mode 100644 index f501761a4..000000000 --- a/qemu/roms/u-boot/board/samsung/trats2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2000 - 2013 Samsung Electronics Co., Ltd. All rights reserved. -# Sanghee Kim <sh0130.kim@samsung.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := trats2.o diff --git a/qemu/roms/u-boot/board/samsung/trats2/trats2.c b/qemu/roms/u-boot/board/samsung/trats2/trats2.c deleted file mode 100644 index 47095252a..000000000 --- a/qemu/roms/u-boot/board/samsung/trats2/trats2.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. - * Sanghee Kim <sh0130.kim@samsung.com> - * Piotr Wilczek <p.wilczek@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <lcd.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/power.h> -#include <asm/arch/mipi_dsim.h> -#include <power/pmic.h> -#include <power/max77686_pmic.h> -#include <power/battery.h> -#include <power/max77693_pmic.h> -#include <power/max77693_muic.h> -#include <power/max77693_fg.h> -#include <libtizen.h> -#include <errno.h> -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -DECLARE_GLOBAL_DATA_PTR; - -static struct exynos4x12_gpio_part1 *gpio1; -static struct exynos4x12_gpio_part2 *gpio2; - -static unsigned int board_rev = -1; - -static inline u32 get_model_rev(void); - -static void check_hw_revision(void) -{ - int modelrev = 0; - int i; - - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* - * GPM1[1:0]: MODEL_REV[1:0] - * Don't set as pull-none for these N/C pin. - * TRM say that it may cause unexcepted state and leakage current. - * and pull-none is only for output function. - */ - for (i = 0; i < 2; i++) - s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); - - /* GPM1[5:2]: HW_REV[3:0] */ - for (i = 2; i < 6; i++) { - s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE); - } - - /* GPM1[1:0]: MODEL_REV[1:0] */ - for (i = 0; i < 2; i++) - modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i); - - /* board_rev[15:8] = model */ - board_rev = modelrev << 8; -} - -u32 get_board_rev(void) -{ - return board_rev; -} - -static inline u32 get_model_rev(void) -{ - return (board_rev >> 8) & 0xff; -} - -static void board_external_gpio_init(void) -{ - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* - * some pins which in alive block are connected with external pull-up - * but it's default setting is pull-down. - * if that pin set as input then that floated - */ - - s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */ - s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */ - s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ - s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ - s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */ - s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */ - s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */ - s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */ - s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */ - s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */ - s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */ - s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */ -} - -#ifdef CONFIG_SYS_I2C_INIT_BOARD -static void board_init_i2c(void) -{ - int err; - - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* I2C_7 */ - err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE); - if (err) { - debug("I2C%d not configured\n", (I2C_7)); - return; - } - - /* I2C_8 */ - s5p_gpio_direction_output(&gpio1->f1, 4, 1); - s5p_gpio_direction_output(&gpio1->f1, 5, 1); - - /* I2C_9 */ - s5p_gpio_direction_output(&gpio2->m2, 1, 1); - s5p_gpio_direction_output(&gpio2->m2, 0, 1); -} -#endif - -#ifdef CONFIG_SYS_I2C_SOFT -int get_soft_i2c_scl_pin(void) -{ - if (I2C_ADAP_HWNR) - return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */ - else - return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */ -} - -int get_soft_i2c_sda_pin(void) -{ - if (I2C_ADAP_HWNR) - return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */ - else - return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */ -} -#endif - -int exynos_early_init_f(void) -{ - board_external_gpio_init(); - - return 0; -} - -static int pmic_init_max77686(void); - -int exynos_init(void) -{ - struct exynos4_power *pwr = - (struct exynos4_power *)samsung_get_base_power(); - - check_hw_revision(); - printf("HW Revision:\t0x%04x\n", board_rev); - - /* - * First bootloader on the TRATS2 platform uses - * INFORM4 and INFORM5 registers for recovery - * - * To indicate correct boot chain - those two - * registers must be cleared out - */ - writel(0, &pwr->inform4); - writel(0, &pwr->inform5); - - return 0; -} - -int exynos_power_init(void) -{ - int chrg; - struct power_battery *pb; - struct pmic *p_chrg, *p_muic, *p_fg, *p_bat; - -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_init_i2c(); -#endif - pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */ - pmic_init_max77686(); - pmic_init_max77693(I2C_10); /* I2C adapter 10 - bus name soft1 */ - power_muic_init(I2C_10); /* I2C adapter 10 - bus name soft1 */ - power_fg_init(I2C_9); /* I2C adapter 9 - bus name soft0 */ - power_bat_init(0); - - p_chrg = pmic_get("MAX77693_PMIC"); - if (!p_chrg) { - puts("MAX77693_PMIC: Not found\n"); - return -ENODEV; - } - - p_muic = pmic_get("MAX77693_MUIC"); - if (!p_muic) { - puts("MAX77693_MUIC: Not found\n"); - return -ENODEV; - } - - p_fg = pmic_get("MAX77693_FG"); - if (!p_fg) { - puts("MAX17042_FG: Not found\n"); - return -ENODEV; - } - - if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0) - puts("No battery detected\n"); - - p_bat = pmic_get("BAT_TRATS2"); - if (!p_bat) { - puts("BAT_TRATS2: Not found\n"); - return -ENODEV; - } - - p_fg->parent = p_bat; - p_chrg->parent = p_bat; - p_muic->parent = p_bat; - - p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); - - pb = p_bat->pbat; - chrg = p_muic->chrg->chrg_type(p_muic); - debug("CHARGER TYPE: %d\n", chrg); - - if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { - puts("No battery detected\n"); - return -1; - } - - p_fg->fg->fg_battery_check(p_fg, p_bat); - - if (pb->bat->state == CHARGE && chrg == CHARGER_USB) - puts("CHARGE Battery !\n"); - - return 0; -} - -#ifdef CONFIG_USB_GADGET -static int s5pc210_phy_control(int on) -{ - int ret = 0; - unsigned int val; - struct pmic *p, *p_pmic, *p_muic; - - p_pmic = pmic_get("MAX77686_PMIC"); - if (!p_pmic) - return -ENODEV; - - if (pmic_probe(p_pmic)) - return -1; - - p_muic = pmic_get("MAX77693_MUIC"); - if (!p_muic) - return -ENODEV; - - if (pmic_probe(p_muic)) - return -1; - - if (on) { - ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON); - if (ret) - return -1; - - p = pmic_get("MAX77693_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - /* SAFEOUT */ - ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val); - if (ret) - return -1; - - val |= MAX77693_ENSAFEOUT1; - ret = pmic_reg_write(p, MAX77693_SAFEOUT, val); - if (ret) - return -1; - - /* PATH: USB */ - ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1, - MAX77693_MUIC_CTRL1_DN1DP2); - - } else { - ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM); - if (ret) - return -1; - - /* PATH: UART */ - ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1, - MAX77693_MUIC_CTRL1_UT1UR2); - } - - if (ret) - return -1; - - return 0; -} - -struct s3c_plat_otg_data s5pc210_otg_data = { - .phy_control = s5pc210_phy_control, - .regs_phy = EXYNOS4X12_USBPHY_BASE, - .regs_otg = EXYNOS4X12_USBOTG_BASE, - .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, - .usb_flags = PHY0_SLEEP, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - struct pmic *muic = pmic_get("MAX77693_MUIC"); - if (!muic) - return 0; - - return !!muic->chrg->chrg_type(muic); -} -#endif - -static int pmic_init_max77686(void) -{ - struct pmic *p = pmic_get("MAX77686_PMIC"); - - if (pmic_probe(p)) - return -1; - - /* BUCK/LDO Output Voltage */ - max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */ - max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/ - max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */ - - /* BUCK/LDO Output Mode */ - max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */ - max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */ - max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */ - max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */ - max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */ - max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/ - max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */ - max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */ - max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/ - - max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/ - max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */ - max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */ - max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */ - max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */ - max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */ - max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */ - max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */ - max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/ - max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/ - max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/ - max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/ - max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */ - max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */ - max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/ - max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/ - max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/ - max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/ - max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */ - max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/ - max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */ - max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/ - max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/ - max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */ - max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */ - max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/ - - return 0; -} - -/* - * LCD - */ - -#ifdef CONFIG_LCD -int mipi_power(void) -{ - struct pmic *p = pmic_get("MAX77686_PMIC"); - - /* LDO8 VMIPI_1.0V_AP */ - max77686_set_ldo_mode(p, 8, OPMODE_ON); - /* LDO10 VMIPI_1.8V_AP */ - max77686_set_ldo_mode(p, 10, OPMODE_ON); - - return 0; -} - -void exynos_lcd_power_on(void) -{ - struct pmic *p = pmic_get("MAX77686_PMIC"); - - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - - /* LCD_2.2V_EN: GPC0[1] */ - s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP); - s5p_gpio_direction_output(&gpio1->c0, 1, 1); - - /* LDO25 VCC_3.1V_LCD */ - pmic_probe(p); - max77686_set_ldo_voltage(p, 25, 3100000); - max77686_set_ldo_mode(p, 25, OPMODE_LPM); -} - -void exynos_reset_lcd(void) -{ - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - - /* reset lcd */ - s5p_gpio_direction_output(&gpio1->f2, 1, 0); - udelay(10); - s5p_gpio_set_value(&gpio1->f2, 1, 1); -} - -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif -#ifdef CONFIG_S6E8AX0 - s6e8ax0_init(); -#endif -} -#endif /* LCD */ diff --git a/qemu/roms/u-boot/board/samsung/universal_c210/Makefile b/qemu/roms/u-boot/board/samsung/universal_c210/Makefile deleted file mode 100644 index 4ceeeb62b..000000000 --- a/qemu/roms/u-boot/board/samsung/universal_c210/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2010 Samsung Electronics -# Minkyu Kang <mk7.kang@samsung.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := universal.o onenand.o diff --git a/qemu/roms/u-boot/board/samsung/universal_c210/onenand.c b/qemu/roms/u-boot/board/samsung/universal_c210/onenand.c deleted file mode 100644 index 28bc8114f..000000000 --- a/qemu/roms/u-boot/board/samsung/universal_c210/onenand.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2010 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/onenand.h> -#include <linux/mtd/samsung_onenand.h> - -void onenand_board_init(struct mtd_info *mtd) -{ - struct onenand_chip *this = mtd->priv; - - this->base = (void *)CONFIG_SYS_ONENAND_BASE; - this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; - this->chip_probe = s5pc210_chip_probe; -} diff --git a/qemu/roms/u-boot/board/samsung/universal_c210/universal.c b/qemu/roms/u-boot/board/samsung/universal_c210/universal.c deleted file mode 100644 index 8e49195fe..000000000 --- a/qemu/roms/u-boot/board/samsung/universal_c210/universal.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (C) 2010 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <spi.h> -#include <lcd.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/adc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/watchdog.h> -#include <ld9040.h> -#include <power/pmic.h> -#include <usb.h> -#include <usb/s3c_udc.h> -#include <asm/arch/cpu.h> -#include <power/max8998_pmic.h> -#include <libtizen.h> -#include <samsung/misc.h> -#include <usb_mass_storage.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; -unsigned int board_rev; - -u32 get_board_rev(void) -{ - return board_rev; -} - -static int get_hwrev(void) -{ - return board_rev & 0xFF; -} - -static void init_pmic_lcd(void); - -int exynos_power_init(void) -{ - int ret; - - /* - * For PMIC the I2C bus is named as I2C5, but it is connected - * to logical I2C adapter 0 - */ - ret = pmic_init(I2C_0); - if (ret) - return ret; - - init_pmic_lcd(); - - return 0; -} - -static unsigned short get_adc_value(int channel) -{ - struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); - unsigned short ret = 0; - unsigned int reg; - unsigned int loop = 0; - - writel(channel & 0xF, &adc->adcmux); - writel((1 << 14) | (49 << 6), &adc->adccon); - writel(1000 & 0xffff, &adc->adcdly); - writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */ - udelay(10); - writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */ - udelay(10); - - do { - udelay(1); - reg = readl(&adc->adccon); - } while (!(reg & (1 << 15)) && (loop++ < 1000)); - - ret = readl(&adc->adcdat0) & 0xFFF; - - return ret; -} - -static int adc_power_control(int on) -{ - int ret; - struct pmic *p = pmic_get("MAX8998_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - ret = pmic_set_output(p, - MAX8998_REG_ONOFF1, - MAX8998_LDO4, !!on); - - return ret; -} - -static unsigned int get_hw_revision(void) -{ - int hwrev, mode0, mode1; - - adc_power_control(1); - - mode0 = get_adc_value(1); /* HWREV_MODE0 */ - mode1 = get_adc_value(2); /* HWREV_MODE1 */ - - /* - * XXX Always set the default hwrev as the latest board - * ADC = (voltage) / 3.3 * 4096 - */ - hwrev = 3; - -#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max)) - if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200)) - hwrev = 0x0; /* 0.01V 0.01V */ - if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200)) - hwrev = 0x1; /* 610mV 0.01V */ - if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200)) - hwrev = 0x2; /* 1.16V 0.01V */ - if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200)) - hwrev = 0x3; /* 1.79V 0.01V */ -#undef IS_RANGE - - debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev); - - adc_power_control(0); - - return hwrev; -} - -static void check_hw_revision(void) -{ - int hwrev; - - hwrev = get_hw_revision(); - - board_rev |= hwrev; -} - -#ifdef CONFIG_USB_GADGET -static int s5pc210_phy_control(int on) -{ - int ret = 0; - struct pmic *p = pmic_get("MAX8998_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (on) { - ret |= pmic_set_output(p, - MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, - MAX8998_SAFEOUT1, LDO_ON); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_ON); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_ON); - - } else { - ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_OFF); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_OFF); - ret |= pmic_set_output(p, - MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, - MAX8998_SAFEOUT1, LDO_OFF); - } - - if (ret) { - puts("MAX8998 LDO setting error!\n"); - return -1; - } - - return 0; -} - -struct s3c_plat_otg_data s5pc210_otg_data = { - .phy_control = s5pc210_phy_control, - .regs_phy = EXYNOS4_USBPHY_BASE, - .regs_otg = EXYNOS4_USBOTG_BASE, - .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, - .usb_flags = PHY0_SLEEP, -}; -#endif - -int board_usb_init(int index, enum usb_init_type init) -{ - debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); -} - -int exynos_early_init_f(void) -{ - wdt_stop(); - - return 0; -} - -#ifdef CONFIG_SOFT_SPI -static void soft_spi_init(void) -{ - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK, - CONFIG_SOFT_SPI_MODE & SPI_CPOL); - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1); - gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO); - gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); - SPI_SCL(1); - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, - !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void universal_spi_scl(int bit) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit); -} - -void universal_spi_sda(int bit) -{ - gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit); -} - -int universal_spi_read(void) -{ - return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO); -} -#endif - -static void init_pmic_lcd(void) -{ - unsigned char val; - int ret = 0; - - struct pmic *p = pmic_get("MAX8998_PMIC"); - - if (!p) - return; - - if (pmic_probe(p)) - return; - - /* LDO7 1.8V */ - val = 0x02; /* (1800 - 1600) / 100; */ - ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val); - - /* LDO17 3.0V */ - val = 0xe; /* (3000 - 1600) / 100; */ - ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val); - - /* Disable unneeded regulators */ - /* - * ONOFF1 - * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON - * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON - */ - val = 0xB9; - ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val); - - /* ONOFF2 - * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON, - * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF - */ - val = 0x50; - ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val); - - /* ONOFF3 - * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF - * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF - */ - val = 0x00; - ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val); - - if (ret) - puts("LCD pmic initialisation error!\n"); -} - -void exynos_cfg_lcd_gpio(void) -{ - unsigned int i, f3_end = 4; - - for (i = 0; i < 8; i++) { - /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2)); - /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE); - - /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); - } - - for (i = 0; i < f3_end; i++) { - /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2)); - /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE); - /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW); - } - - /* gpio pad configuration for LCD reset. */ - s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT); - - spi_init(); -} - -int mipi_power(void) -{ - return 0; -} - -void exynos_reset_lcd(void) -{ - s5p_gpio_set_value(&gpio2->y4, 5, 1); - udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 0); - udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 1); - udelay(100); -} - -void exynos_lcd_power_on(void) -{ - struct pmic *p = pmic_get("MAX8998_PMIC"); - - if (!p) - return; - - if (pmic_probe(p)) - return; - - pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON); - pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON); -} - -void exynos_cfg_ldo(void) -{ - ld9040_cfg_ldo(); -} - -void exynos_enable_ldo(unsigned int onoff) -{ - ld9040_enable_ldo(onoff); -} - -int exynos_init(void) -{ - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; - - switch (get_hwrev()) { - case 0: - /* - * Set the low to enable LDO_EN - * But when you use the test board for eMMC booting - * you should set it HIGH since it removes the inverter - */ - /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - s5p_gpio_direction_output(&gpio1->e3, 6, 0); - break; - default: - /* - * Default reset state is High and there's no inverter - * But set it as HIGH to ensure - */ - /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - s5p_gpio_direction_output(&gpio1->e1, 3, 1); - break; - } - -#ifdef CONFIG_SOFT_SPI - soft_spi_init(); -#endif - check_hw_revision(); - printf("HW Revision:\t0x%x\n", board_rev); - - return 0; -} - -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif - - /* for LD9040. */ - vid->pclk_name = 1; /* MPLL */ - vid->sclk_div = 1; - - setenv("lcdinfo", "lcd=ld9040"); -} |