Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

3 files changed, 1241 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/samsung/trats/Makefile b/qemu/roms/u-boot/board/samsung/trats/Makefile
new file mode 100644
index 000000000..5dc8a1f7d
--- /dev/null
+++ b/qemu/roms/u-boot/board/samsung/trats/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011 Samsung Electronics
+# Heungjun Kim <riverful.kim@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= trats.o
diff --git a/qemu/roms/u-boot/board/samsung/trats/setup.h b/qemu/roms/u-boot/board/samsung/trats/setup.h
new file mode 100644
index 000000000..2f5ccb14c
--- /dev/null
+++ b/qemu/roms/u-boot/board/samsung/trats/setup.h
@@ -0,0 +1,621 @@
+/*
+ * Machine Specific Values for TRATS board based on EXYNOS4210
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TRATS_SETUP_H
+#define _TRATS_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
+#define MUX_HPM_SEL_MOUTAPLL		0x0
+#define MUX_HPM_SEL_SCLKMPLL		0x1
+#define MUX_CORE_SEL_MOUTAPLL		0x0
+#define MUX_CORE_SEL_SCLKMPLL		0x1
+#define MUX_MPLL_SEL_FILPLL		0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
+#define MUX_APLL_SEL_FILPLL		0x0
+#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
+#define CLK_SRC_CPU_VAL			((MUX_HPM_SEL_MOUTAPLL << 20) \
+					| (MUX_CORE_SEL_MOUTAPLL << 16) \
+					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
+					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+
+/* CLK_DIV_CPU0 */
+#define APLL_RATIO			0x0
+#define PCLK_DBG_RATIO			0x1
+#define ATB_RATIO			0x3
+#define PERIPH_RATIO			0x3
+#define COREM1_RATIO			0x7
+#define COREM0_RATIO			0x3
+#define CORE_RATIO			0x0
+#define CLK_DIV_CPU0_VAL		((APLL_RATIO << 24) \
+					| (PCLK_DBG_RATIO << 20) \
+					| (ATB_RATIO << 16) \
+					| (PERIPH_RATIO << 12) \
+					| (COREM1_RATIO << 8) \
+					| (COREM0_RATIO << 4) \
+					| (CORE_RATIO << 0))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO			0x0
+#define COPY_RATIO			0x3
+#define CLK_DIV_CPU1_VAL		((HPM_RATIO << 4) | (COPY_RATIO))
+
+/* CLK_DIV_DMC0 */
+#define CORE_TIMERS_RATIO		0x1
+#define COPY2_RATIO			0x3
+#define DMCP_RATIO			0x1
+#define DMCD_RATIO			0x1
+#define DMC_RATIO			0x1
+#define DPHY_RATIO			0x1
+#define ACP_PCLK_RATIO			0x1
+#define ACP_RATIO			0x3
+#define CLK_DIV_DMC0_VAL		((CORE_TIMERS_RATIO << 28) \
+					| (COPY2_RATIO << 24) \
+					| (DMCP_RATIO << 20) \
+					| (DMCD_RATIO << 16) \
+					| (DMC_RATIO << 12) \
+					| (DPHY_RATIO << 8) \
+					| (ACP_PCLK_RATIO << 4)	\
+					| (ACP_RATIO << 0))
+
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO			0x1
+#define DVSEM_RATIO			0x1
+#define PWI_RATIO			0x1
+#define CLK_DIV_DMC1_VAL		((DPM_RATIO << 24) \
+					| (DVSEM_RATIO << 16) \
+					| (PWI_RATIO << 8))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL_ACLK_133	0x0
+#define MUX_ONENAND_SEL_ACLK_160	0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
+#define MUX_VPLL_SEL_FINPLL		0x0
+#define MUX_VPLL_SEL_FOUTVPLL		0x1
+#define MUX_EPLL_SEL_FINPLL		0x0
+#define MUX_EPLL_SEL_FOUTEPLL		0x1
+#define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
+#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
+#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_160 << 28) \
+					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
+					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
+					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
+					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
+					| (MUX_VPLL_SEL_FOUTVPLL << 8) \
+					| (MUX_EPLL_SEL_FOUTEPLL << 4) \
+					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+
+/* CLK_DIV_TOP */
+#define ONENAND_RATIO			0x0
+#define ACLK_133_RATIO			0x5
+#define ACLK_160_RATIO			0x4
+#define ACLK_100_RATIO			0x7
+#define ACLK_200_RATIO			0x3
+#define CLK_DIV_TOP_VAL			((ONENAND_RATIO << 16)	\
+					| (ACLK_133_RATIO << 12)\
+					| (ACLK_160_RATIO << 8)	\
+					| (ACLK_100_RATIO << 4)	\
+					| (ACLK_200_RATIO << 0))
+
+/* CLK_DIV_LEFTBUS */
+#define GPL_RATIO			0x1
+#define GDL_RATIO			0x3
+#define CLK_DIV_LEFTBUS_VAL		((GPL_RATIO << 4) | (GDL_RATIO))
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO			0x1
+#define GDR_RATIO			0x3
+#define CLK_DIV_RIGHTBUS_VAL		((GPR_RATIO << 4) | (GDR_RATIO))
+
+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
+#define SATA_SEL_SCLKMPLL		0
+#define SATA_SEL_SCLKAPLL		1
+
+#define MMC_SEL_XXTI			0
+#define MMC_SEL_XUSBXTI			1
+#define MMC_SEL_SCLK_HDMI24M		2
+#define MMC_SEL_SCLK_USBPHY0		3
+#define MMC_SEL_SCLK_USBPHY1		4
+#define MMC_SEL_SCLK_HDMIPHY		5
+#define MMC_SEL_SCLKMPLL		6
+#define MMC_SEL_SCLKEPLL		7
+#define MMC_SEL_SCLKVPLL		8
+
+#define MMCC0_SEL			MMC_SEL_SCLKMPLL
+#define MMCC1_SEL			MMC_SEL_SCLKMPLL
+#define MMCC2_SEL			MMC_SEL_SCLKMPLL
+#define MMCC3_SEL			MMC_SEL_SCLKMPLL
+#define MMCC4_SEL			MMC_SEL_SCLKMPLL
+#define CLK_SRC_FSYS_VAL		((SATA_SEL_SCLKMPLL << 24) \
+					| (MMCC4_SEL << 16) \
+					| (MMCC3_SEL << 12) \
+					| (MMCC2_SEL << 8) \
+					| (MMCC1_SEL << 4) \
+					| (MMCC0_SEL << 0))
+
+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
+/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
+#define MMC0_RATIO			0xF
+#define MMC0_PRE_RATIO			0x0
+#define MMC1_RATIO			0xF
+#define MMC1_PRE_RATIO			0x0
+#define CLK_DIV_FSYS1_VAL		((MMC1_PRE_RATIO << 24) \
+					| (MMC1_RATIO << 16) \
+					| (MMC0_PRE_RATIO << 8) \
+					| (MMC0_RATIO << 0))
+
+/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
+#define MMC2_RATIO			0xF
+#define MMC2_PRE_RATIO			0x0
+#define MMC3_RATIO			0xF
+#define MMC3_PRE_RATIO			0x0
+#define CLK_DIV_FSYS2_VAL		((MMC3_PRE_RATIO << 24) \
+					| (MMC3_RATIO << 16) \
+					| (MMC2_PRE_RATIO << 8) \
+					| (MMC2_RATIO << 0))
+
+/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
+#define MMC4_RATIO			0xF
+#define MMC4_PRE_RATIO			0x0
+#define CLK_DIV_FSYS3_VAL		((MMC4_PRE_RATIO << 8) \
+					| (MMC4_RATIO << 0))
+
+/* CLK_SRC_PERIL0 */
+#define UART_SEL_XXTI			0
+#define UART_SEL_XUSBXTI		1
+#define UART_SEL_SCLK_HDMI24M		2
+#define UART_SEL_SCLK_USBPHY0		3
+#define UART_SEL_SCLK_USBPHY1		4
+#define UART_SEL_SCLK_HDMIPHY		5
+#define UART_SEL_SCLKMPLL		6
+#define UART_SEL_SCLKEPLL		7
+#define UART_SEL_SCLKVPLL		8
+
+#define UART0_SEL			UART_SEL_SCLKMPLL
+#define UART1_SEL			UART_SEL_SCLKMPLL
+#define UART2_SEL			UART_SEL_SCLKMPLL
+#define UART3_SEL			UART_SEL_SCLKMPLL
+#define UART4_SEL			UART_SEL_SCLKMPLL
+#define UART5_SEL			UART_SEL_SCLKMPLL
+#define CLK_SRC_PERIL0_VAL		((UART5_SEL << 16) \
+					| (UART4_SEL << 12) \
+					| (UART3_SEL << 12) \
+					| (UART2_SEL << 8) \
+					| (UART1_SEL << 4) \
+					| (UART0_SEL << 0))
+
+/* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO			7
+#define UART1_RATIO			7
+#define UART2_RATIO			7
+#define UART3_RATIO			4
+#define UART4_RATIO			7
+#define UART5_RATIO			7
+#define CLK_DIV_PERIL0_VAL		((UART5_RATIO << 16) \
+					| (UART4_RATIO << 12) \
+					| (UART3_RATIO << 12) \
+					| (UART2_RATIO << 8) \
+					| (UART1_RATIO << 4) \
+					| (UART0_RATIO << 0))
+
+/* CLK_DIV_PERIL3 */
+#define SLIMBUS_RATIO			0x0
+#define PWM_RATIO			0x8
+#define CLK_DIV_PERIL3_VAL		((SLIMBUS_RATIO << 4) \
+					| (PWM_RATIO << 0))
+
+/* Required period to generate a stable clock output */
+/* PLL_LOCK_TIME */
+#define PLL_LOCKTIME			0x1C20
+
+/* PLL Values */
+#define DISABLE				0
+#define ENABLE				1
+#define SET_PLL(mdiv, pdiv, sdiv)	((ENABLE << 31)\
+					| (mdiv << 16) \
+					| (pdiv << 8) \
+					| (sdiv << 0))
+
+/* APLL_CON0: 800MHz */
+#define APLL_MDIV			0xC8
+#define APLL_PDIV			0x6
+#define APLL_SDIV			0x1
+#define APLL_CON0_VAL			SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+
+/* APLL_CON1 */
+#define APLL_AFC_ENB			0x1
+#define APLL_AFC			0x1C
+#define APLL_CON1_VAL			((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
+
+/* MPLL_CON0: 800MHz */
+#define MPLL_MDIV			0xC8
+#define MPLL_PDIV			0x6
+#define MPLL_SDIV			0x1
+#define MPLL_CON0_VAL			SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+
+/* MPLL_CON1 */
+#define MPLL_AFC_ENB			0x1
+#define MPLL_AFC			0x1C
+#define MPLL_CON1_VAL			((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
+
+/* EPLL_CON0: 96MHz */
+#define EPLL_MDIV			0x30
+#define EPLL_PDIV			0x3
+#define EPLL_SDIV			0x2
+#define EPLL_CON0_VAL			SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+
+/* EPLL_CON1 */
+#define EPLL_K				0x0
+#define EPLL_CON1_VAL			(EPLL_K >> 0)
+
+/* VPLL_CON0: 108MHz */
+#define VPLL_MDIV			0x35
+#define VPLL_PDIV			0x3
+#define VPLL_SDIV			0x2
+#define VPLL_CON0_VAL			SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+
+/* VPLL_CON1 */
+#define VPLL_SSCG_EN			DISABLE
+#define VPLL_SEL_PF_DN_SPREAD		0x0
+#define VPLL_MRR			0x11
+#define VPLL_MFR			0x0
+#define VPLL_K				0x400
+#define VPLL_CON1_VAL			((VPLL_SSCG_EN << 31)\
+					| (VPLL_SEL_PF_DN_SPREAD << 29) \
+					| (VPLL_MRR << 24) \
+					| (VPLL_MFR << 16) \
+					| (VPLL_K << 0))
+
+/* CLOCK GATE */
+#define CLK_DIS				0x0
+#define CLK_EN				0x1
+
+#define BIT_CAM_CLK_PIXELASYNCM1	18
+#define BIT_CAM_CLK_PIXELASYNCM0	17
+#define BIT_CAM_CLK_PPMUCAMIF		16
+#define BIT_CAM_CLK_QEFIMC3		15
+#define BIT_CAM_CLK_QEFIMC2		14
+#define BIT_CAM_CLK_QEFIMC1		13
+#define BIT_CAM_CLK_QEFIMC0		12
+#define BIT_CAM_CLK_SMMUJPEG		11
+#define BIT_CAM_CLK_SMMUFIMC3		10
+#define BIT_CAM_CLK_SMMUFIMC2		9
+#define BIT_CAM_CLK_SMMUFIMC1		8
+#define BIT_CAM_CLK_SMMUFIMC0		7
+#define BIT_CAM_CLK_JPEG		6
+#define BIT_CAM_CLK_CSIS1		5
+#define BIT_CAM_CLK_CSIS0		4
+#define BIT_CAM_CLK_FIMC3		3
+#define BIT_CAM_CLK_FIMC2		2
+#define BIT_CAM_CLK_FIMC1		1
+#define BIT_CAM_CLK_FIMC0		0
+#define CLK_GATE_IP_CAM_ALL_EN		((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
+					| (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
+					| (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
+					| (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
+					| (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
+					| (CLK_EN << BIT_CAM_CLK_JPEG)\
+					| (CLK_EN << BIT_CAM_CLK_CSIS1)\
+					| (CLK_EN << BIT_CAM_CLK_CSIS0)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC3)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC2)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC1)\
+					| (CLK_EN << BIT_CAM_CLK_FIMC0))
+#define CLK_GATE_IP_CAM_ALL_DIS		~CLK_GATE_IP_CAM_ALL_EN
+
+#define BIT_VP_CLK_PPMUTV		5
+#define BIT_VP_CLK_SMMUTV		4
+#define BIT_VP_CLK_HDMI			3
+#define BIT_VP_CLK_TVENC		2
+#define BIT_VP_CLK_MIXER		1
+#define BIT_VP_CLK_VP			0
+#define CLK_GATE_IP_VP_ALL_EN		((CLK_EN << BIT_VP_CLK_PPMUTV)\
+					| (CLK_EN << BIT_VP_CLK_SMMUTV)\
+					| (CLK_EN << BIT_VP_CLK_HDMI)\
+					| (CLK_EN << BIT_VP_CLK_TVENC)\
+					| (CLK_EN << BIT_VP_CLK_MIXER)\
+					| (CLK_EN << BIT_VP_CLK_VP))
+#define CLK_GATE_IP_VP_ALL_DIS		~CLK_GATE_IP_VP_ALL_EN
+
+#define BIT_MFC_CLK_PPMUMFC_R		4
+#define BIT_MFC_CLK_PPMUMFC_L		3
+#define BIT_MFC_CLK_SMMUMFC_R		2
+#define BIT_MFC_CLK_SMMUMFC_L		1
+#define BIT_MFC_CLK_MFC			0
+#define CLK_GATE_IP_MFC_ALL_EN		((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
+					| (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
+					| (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
+					| (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
+					| (CLK_EN << BIT_MFC_CLK_MFC))
+#define CLK_GATE_IP_MFC_ALL_DIS		~CLK_GATE_IP_MFC_ALL_EN
+
+#define BIT_G3D_CLK_QEG3D		2
+#define BIT_G3D_CLK_PPMUG3D		1
+#define BIT_G3D_CLK_G3D			0
+#define CLK_GATE_IP_G3D_ALL_EN		((CLK_EN << BIT_G3D_CLK_QEG3D)\
+					| (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
+					| (CLK_EN << BIT_G3D_CLK_G3D))
+#define CLK_GATE_IP_G3D_ALL_DIS		~CLK_GATE_IP_G3D_ALL_EN
+
+#define BIT_IMAGE_CLK_PPMUIMAGE		9
+#define BIT_IMAGE_CLK_QEMDMA		8
+#define BIT_IMAGE_CLK_QEROTATOR		7
+#define BIT_IMAGE_CLK_QEG2D		6
+#define BIT_IMAGE_CLK_SMMUMDMA		5
+#define BIT_IMAGE_CLK_SMMUROTATOR	4
+#define BIT_IMAGE_CLK_SMMUG2D		3
+#define BIT_IMAGE_CLK_MDMA		2
+#define BIT_IMAGE_CLK_ROTATOR		1
+#define BIT_IMAGE_CLK_G2D		0
+#define CLK_GATE_IP_IMAGE_ALL_EN	((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
+					| (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
+					| (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
+					| (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
+					| (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
+					| (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
+					| (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
+					| (CLK_EN << BIT_IMAGE_CLK_MDMA)\
+					| (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
+					| (CLK_EN << BIT_IMAGE_CLK_G2D))
+#define CLK_GATE_IP_IMAGE_ALL_DIS	~CLK_GATE_IP_IMAGE_ALL_EN
+
+#define BIT_LCD0_CLK_PPMULCD0		5
+#define BIT_LCD0_CLK_SMMUFIMD0		4
+#define BIT_LCD0_CLK_DSIM0		3
+#define BIT_LCD0_CLK_MDNIE0		2
+#define BIT_LCD0_CLK_MIE0		1
+#define BIT_LCD0_CLK_FIMD0		0
+#define CLK_GATE_IP_LCD0_ALL_EN		((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
+					| (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
+					| (CLK_EN << BIT_LCD0_CLK_DSIM0)\
+					| (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
+					| (CLK_EN << BIT_LCD0_CLK_MIE0)\
+					| (CLK_EN << BIT_LCD0_CLK_FIMD0))
+#define CLK_GATE_IP_LCD0_ALL_DIS	~CLK_GATE_IP_LCD0_ALL_EN
+
+#define BIT_LCD1_CLK_PPMULCD1		5
+#define BIT_LCD1_CLK_SMMUFIMD1		4
+#define BIT_LCD1_CLK_DSIM1		3
+#define BIT_LCD1_CLK_MDNIE1		2
+#define BIT_LCD1_CLK_MIE1		1
+#define BIT_LCD1_CLK_FIMD1		0
+#define CLK_GATE_IP_LCD1_ALL_EN		((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
+					| (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
+					| (CLK_EN << BIT_LCD1_CLK_DSIM1)\
+					| (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
+					| (CLK_EN << BIT_LCD1_CLK_MIE1)\
+					| (CLK_EN << BIT_LCD1_CLK_FIMD1))
+#define CLK_GATE_IP_LCD1_ALL_DIS	~CLK_GATE_IP_LCD1_ALL_EN
+
+#define BIT_FSYS_CLK_SMMUPCIE		18
+#define BIT_FSYS_CLK_PPMUFILE		17
+#define BIT_FSYS_CLK_NFCON		16
+#define BIT_FSYS_CLK_ONENAND		15
+#define BIT_FSYS_CLK_PCIE		14
+#define BIT_FSYS_CLK_USBDEVICE		13
+#define BIT_FSYS_CLK_USBHOST		12
+#define BIT_FSYS_CLK_SROMC		11
+#define BIT_FSYS_CLK_SATA		10
+#define BIT_FSYS_CLK_SDMMC4		9
+#define BIT_FSYS_CLK_SDMMC3		8
+#define BIT_FSYS_CLK_SDMMC2		7
+#define BIT_FSYS_CLK_SDMMC1		6
+#define BIT_FSYS_CLK_SDMMC0		5
+#define BIT_FSYS_CLK_TSI		4
+#define BIT_FSYS_CLK_SATAPHY		3
+#define BIT_FSYS_CLK_PCIEPHY		2
+#define BIT_FSYS_CLK_PDMA1		1
+#define BIT_FSYS_CLK_PDMA0		0
+#define CLK_GATE_IP_FSYS_ALL_EN		((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
+					| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
+					| (CLK_EN << BIT_FSYS_CLK_NFCON)\
+					| (CLK_EN << BIT_FSYS_CLK_ONENAND)\
+					| (CLK_EN << BIT_FSYS_CLK_PCIE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
+					| (CLK_EN << BIT_FSYS_CLK_SROMC)\
+					| (CLK_EN << BIT_FSYS_CLK_SATA)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
+					| (CLK_EN << BIT_FSYS_CLK_TSI)\
+					| (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
+					| (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA0))
+#define CLK_GATE_IP_FSYS_ALL_DIS	~CLK_GATE_IP_FSYS_ALL_EN
+
+#define BIT_GPS_CLK_SMMUGPS		1
+#define BIT_GPS_CLK_GPS			0
+#define CLK_GATE_IP_GPS_ALL_EN		((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
+					| (CLK_EN << BIT_GPS_CLK_GPS))
+#define CLK_GATE_IP_GPS_ALL_DIS		~CLK_GATE_IP_GPS_ALL_EN
+
+#define BIT_PERIL_CLK_MODEMIF		28
+#define BIT_PERIL_CLK_AC97		27
+#define BIT_PERIL_CLK_SPDIF		26
+#define BIT_PERIL_CLK_SLIMBUS		25
+#define BIT_PERIL_CLK_PWM		24
+#define BIT_PERIL_CLK_PCM2		23
+#define BIT_PERIL_CLK_PCM1		22
+#define BIT_PERIL_CLK_I2S2		21
+#define BIT_PERIL_CLK_I2S1		20
+#define BIT_PERIL_CLK_RESERVED0		19
+#define BIT_PERIL_CLK_SPI2		18
+#define BIT_PERIL_CLK_SPI1		17
+#define BIT_PERIL_CLK_SPI0		16
+#define BIT_PERIL_CLK_TSADC		15
+#define BIT_PERIL_CLK_I2CHDMI		14
+#define BIT_PERIL_CLK_I2C7		13
+#define BIT_PERIL_CLK_I2C6		12
+#define BIT_PERIL_CLK_I2C5		11
+#define BIT_PERIL_CLK_I2C4		10
+#define BIT_PERIL_CLK_I2C3		9
+#define BIT_PERIL_CLK_I2C2		8
+#define BIT_PERIL_CLK_I2C1		7
+#define BIT_PERIL_CLK_I2C0		6
+#define BIT_PERIL_CLK_RESERVED1		5
+#define BIT_PERIL_CLK_UART4		4
+#define BIT_PERIL_CLK_UART3		3
+#define BIT_PERIL_CLK_UART2		2
+#define BIT_PERIL_CLK_UART1		1
+#define BIT_PERIL_CLK_UART0		0
+#define CLK_GATE_IP_PERIL_ALL_EN	((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
+					| (CLK_EN << BIT_PERIL_CLK_AC97)\
+					| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
+					| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
+					| (CLK_EN << BIT_PERIL_CLK_PWM)\
+					| (CLK_EN << BIT_PERIL_CLK_PCM2)\
+					| (CLK_EN << BIT_PERIL_CLK_PCM1)\
+					| (CLK_EN << BIT_PERIL_CLK_I2S2)\
+					| (CLK_EN << BIT_PERIL_CLK_I2S1)\
+					| (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
+					| (CLK_EN << BIT_PERIL_CLK_SPI2)\
+					| (CLK_EN << BIT_PERIL_CLK_SPI1)\
+					| (CLK_EN << BIT_PERIL_CLK_SPI0)\
+					| (CLK_EN << BIT_PERIL_CLK_TSADC)\
+					| (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C7)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C6)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C5)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C4)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C3)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C2)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C1)\
+					| (CLK_EN << BIT_PERIL_CLK_I2C0)\
+					| (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
+					| (CLK_EN << BIT_PERIL_CLK_UART4)\
+					| (CLK_EN << BIT_PERIL_CLK_UART3)\
+					| (CLK_EN << BIT_PERIL_CLK_UART2)\
+					| (CLK_EN << BIT_PERIL_CLK_UART1)\
+					| (CLK_EN << BIT_PERIL_CLK_UART0))
+#define CLK_GATE_IP_PERIL_ALL_DIS	~CLK_GATE_IP_PERIL_ALL_EN
+
+#define BIT_PERIR_CLK_TMU_APBIF		17
+#define BIT_PERIR_CLK_KEYIF		16
+#define BIT_PERIR_CLK_RTC		15
+#define BIT_PERIR_CLK_WDT		14
+#define BIT_PERIR_CLK_MCT		13
+#define BIT_PERIR_CLK_SECKEY		12
+#define BIT_PERIR_CLK_HDMI_CEC		11
+#define BIT_PERIR_CLK_TZPC5		10
+#define BIT_PERIR_CLK_TZPC4		9
+#define BIT_PERIR_CLK_TZPC3		8
+#define BIT_PERIR_CLK_TZPC2		7
+#define BIT_PERIR_CLK_TZPC1		6
+#define BIT_PERIR_CLK_TZPC0		5
+#define BIT_PERIR_CLK_CMU_DMCPART	4
+#define BIT_PERIR_CLK_RESERVED		3
+#define BIT_PERIR_CLK_CMU_APBIF		2
+#define BIT_PERIR_CLK_SYSREG		1
+#define BIT_PERIR_CLK_CHIP_ID		0
+#define CLK_GATE_IP_PERIR_ALL_EN	((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
+					| (CLK_EN << BIT_PERIR_CLK_KEYIF)\
+					| (CLK_EN << BIT_PERIR_CLK_RTC)\
+					| (CLK_EN << BIT_PERIR_CLK_WDT)\
+					| (CLK_EN << BIT_PERIR_CLK_MCT)\
+					| (CLK_EN << BIT_PERIR_CLK_SECKEY)\
+					| (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC5)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC4)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC3)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC2)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC1)\
+					| (CLK_EN << BIT_PERIR_CLK_TZPC0)\
+					| (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
+					| (CLK_EN << BIT_PERIR_CLK_RESERVED)\
+					| (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
+					| (CLK_EN << BIT_PERIR_CLK_SYSREG)\
+					| (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
+#define CLK_GATE_IP_PERIR_ALL_DIS	~CLK_GATE_IP_PERIR_ALL_EN
+
+#define BIT_BLOCK_CLK_GPS		7
+#define BIT_BLOCK_CLK_RESERVED		6
+#define BIT_BLOCK_CLK_LCD1		5
+#define BIT_BLOCK_CLK_LCD0		4
+#define BIT_BLOCK_CLK_G3D		3
+#define BIT_BLOCK_CLK_MFC		2
+#define BIT_BLOCK_CLK_TV		1
+#define BIT_BLOCK_CLK_CAM		0
+#define CLK_GATE_BLOCK_ALL_EN		((CLK_EN << BIT_BLOCK_CLK_GPS)\
+					| (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
+					| (CLK_EN << BIT_BLOCK_CLK_LCD1)\
+					| (CLK_EN << BIT_BLOCK_CLK_LCD0)\
+					| (CLK_EN << BIT_BLOCK_CLK_G3D)\
+					| (CLK_EN << BIT_BLOCK_CLK_MFC)\
+					| (CLK_EN << BIT_BLOCK_CLK_TV)\
+					| (CLK_EN << BIT_BLOCK_CLK_CAM))
+#define CLK_GATE_BLOCK_ALL_DIS		~CLK_GATE_BLOCK_ALL_EN
+
+/*
+ * GATE CAM	: All block
+ * GATE VP	: All block
+ * GATE MFC	: All block
+ * GATE G3D	: All block
+ * GATE IMAGE	: All block
+ * GATE LCD0	: All block
+ * GATE LCD1	: All block
+ * GATE FSYS	: Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
+ * GATE GPS	: All block
+ * GATE PERI Left	: All Enable, Block - SLIMBUS, SPDIF, AC97
+ * GATE PERI Right	: All Enable, Block - KEYIF
+ * GATE Block	: All block
+ */
+#define CLK_GATE_IP_CAM_VAL		CLK_GATE_IP_CAM_ALL_DIS
+#define CLK_GATE_IP_VP_VAL		CLK_GATE_IP_VP_ALL_DIS
+#define CLK_GATE_IP_MFC_VAL		CLK_GATE_IP_MFC_ALL_DIS
+#define CLK_GATE_IP_G3D_VAL		CLK_GATE_IP_G3D_ALL_DIS
+#define CLK_GATE_IP_IMAGE_VAL		CLK_GATE_IP_IMAGE_ALL_DIS
+#define CLK_GATE_IP_LCD0_VAL		CLK_GATE_IP_LCD0_ALL_DIS
+#define CLK_GATE_IP_LCD1_VAL		CLK_GATE_IP_LCD1_ALL_DIS
+#define CLK_GATE_IP_FSYS_VAL		(CLK_GATE_IP_FSYS_ALL_DIS \
+					| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
+					| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
+					| (CLK_EN << BIT_FSYS_CLK_SROMC)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
+					| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
+					| (CLK_EN << BIT_FSYS_CLK_PDMA0))
+#define CLK_GATE_IP_GPS_VAL		CLK_GATE_IP_GPS_ALL_DIS
+#define CLK_GATE_IP_PERIL_VAL		(CLK_GATE_IP_PERIL_ALL_DIS \
+					| ~((CLK_EN << BIT_PERIL_CLK_AC97)\
+					  | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
+					  | (CLK_EN << BIT_PERIL_CLK_I2C2)\
+					  | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
+#define CLK_GATE_IP_PERIR_VAL		(CLK_GATE_IP_PERIR_ALL_DIS \
+					| ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
+#define CLK_GATE_BLOCK_VAL		CLK_GATE_BLOCK_ALL_DIS
+
+/* PS_HOLD: Data Hight, Output En */
+#define BIT_DAT				8
+#define BIT_EN				9
+#define EXYNOS4_PS_HOLD_CON_VAL		(0x1 << BIT_DAT | 0x1 << BIT_EN)
+
+#endif
diff --git a/qemu/roms/u-boot/board/samsung/trats/trats.c b/qemu/roms/u-boot/board/samsung/trats/trats.c
new file mode 100644
index 000000000..ab0ad1d65
--- /dev/null
+++ b/qemu/roms/u-boot/board/samsung/trats/trats.c
@@ -0,0 +1,612 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/watchdog.h>
+#include <asm/arch/power.h>
+#include <power/pmic.h>
+#include <usb/s3c_udc.h>
+#include <power/max8997_pmic.h>
+#include <power/max8997_muic.h>
+#include <power/battery.h>
+#include <power/max17042_fg.h>
+#include <libtizen.h>
+#include <usb.h>
+#include <usb_mass_storage.h>
+
+#include "setup.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int board_rev;
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return board_rev;
+}
+#endif
+
+static void check_hw_revision(void);
+struct s3c_plat_otg_data s5pc210_otg_data;
+
+int exynos_init(void)
+{
+	check_hw_revision();
+	printf("HW Revision:\t0x%x\n", board_rev);
+
+	return 0;
+}
+
+void i2c_init_board(void)
+{
+	int err;
+	struct exynos4_gpio_part2 *gpio2 =
+		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+
+	/* I2C_5 -> PMIC */
+	err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("I2C%d not configured\n", (I2C_5));
+		return;
+	}
+
+	/* I2C_8 -> FG */
+	s5p_gpio_direction_output(&gpio2->y4, 0, 1);
+	s5p_gpio_direction_output(&gpio2->y4, 1, 1);
+}
+
+static void trats_low_power_mode(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+	struct exynos4_power *pwr =
+	    (struct exynos4_power *)samsung_get_base_power();
+
+	/* Power down CORE1 */
+	/* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
+	writel(0x0, &pwr->arm_core1_configuration);
+
+	/* Change the APLL frequency */
+	/* ENABLE (1 enable) | LOCKED (1 locked)  */
+	/* [31]              | [29]               */
+	/* FSEL      | MDIV          | PDIV            | SDIV */
+	/* [27]      | [25:16]       | [13:8]          | [2:0]      */
+	writel(0xa0c80604, &clk->apll_con0);
+
+	/* Change CPU0 clock divider */
+	/* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
+	/* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
+	/* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
+	/* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
+	writel(0x00000100, &clk->div_cpu0);
+
+	/* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
+	while (readl(&clk->div_stat_cpu0) & 0x1111111)
+		continue;
+
+	/* Change clock divider ratio for DMC */
+	/* DMCP_RATIO                  | DMCD_RATIO  */
+	/* [22:20]                     | [18:16]     */
+	/* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
+	/* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
+	writel(0x13113117, &clk->div_dmc0);
+
+	/* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
+	while (readl(&clk->div_stat_dmc0) & 0x11111111)
+		continue;
+
+	/* Turn off unnecessary power domains */
+	writel(0x0, &pwr->xxti_configuration);	/* XXTI */
+	writel(0x0, &pwr->cam_configuration);	/* CAM */
+	writel(0x0, &pwr->tv_configuration);    /* TV */
+	writel(0x0, &pwr->mfc_configuration);   /* MFC */
+	writel(0x0, &pwr->g3d_configuration);   /* G3D */
+	writel(0x0, &pwr->gps_configuration);   /* GPS */
+	writel(0x0, &pwr->gps_alive_configuration);	/* GPS_ALIVE */
+
+	/* Turn off unnecessary clocks */
+	writel(0x0, &clk->gate_ip_cam);	/* CAM */
+	writel(0x0, &clk->gate_ip_tv);          /* TV */
+	writel(0x0, &clk->gate_ip_mfc);	/* MFC */
+	writel(0x0, &clk->gate_ip_g3d);	/* G3D */
+	writel(0x0, &clk->gate_ip_image);	/* IMAGE */
+	writel(0x0, &clk->gate_ip_gps);	/* GPS */
+}
+
+static int pmic_init_max8997(void)
+{
+	struct pmic *p = pmic_get("MAX8997_PMIC");
+	int i = 0, ret = 0;
+	u32 val;
+
+	if (pmic_probe(p))
+		return -1;
+
+	/* BUCK1 VARM: 1.2V */
+	val = (1200000 - 650000) / 25000;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
+	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
+
+	/* BUCK2 VINT: 1.1V */
+	val = (1100000 - 650000) / 25000;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
+	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
+
+
+	/* BUCK3 G3D: 1.1V - OFF */
+	ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
+	val &= ~ENBUCK;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
+
+	val = (1100000 - 750000) / 50000;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
+
+	/* BUCK4 CAMISP: 1.2V - OFF */
+	ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
+	val &= ~ENBUCK;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
+
+	val = (1200000 - 650000) / 25000;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
+
+	/* BUCK5 VMEM: 1.2V */
+	val = (1200000 - 650000) / 25000;
+	for (i = 0; i < 8; i++)
+		ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
+
+	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
+
+	/* BUCK6 CAM AF: 2.8V */
+	/* No Voltage Setting Register */
+	/* GNSLCT 3.0X */
+	val = GNSLCT;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
+
+	/* BUCK7 VCC_SUB: 2.0V */
+	val = (2000000 - 750000) / 50000;
+	ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
+
+	/* LDO1 VADC: 3.3V */
+	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
+
+	/* LDO1 Disable active discharging */
+	ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
+	val &= ~LDO_ADE;
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
+
+	/* LDO2 VALIVE: 1.1V */
+	val = max8997_reg_ldo(1100000) | EN_LDO;
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
+
+	/* LDO3 VUSB/MIPI: 1.1V */
+	val = max8997_reg_ldo(1100000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
+
+	/* LDO4 VMIPI: 1.8V */
+	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
+
+	/* LDO5 VHSIC: 1.2V */
+	val = max8997_reg_ldo(1200000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
+
+	/* LDO6 VCC_1.8V_PDA: 1.8V */
+	val = max8997_reg_ldo(1800000) | EN_LDO;
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
+
+	/* LDO7 CAM_ISP: 1.8V */
+	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
+
+	/* LDO8 VDAC/VUSB: 3.3V */
+	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
+
+	/* LDO9 VCC_2.8V_PDA: 2.8V */
+	val = max8997_reg_ldo(2800000) | EN_LDO;
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
+
+	/* LDO10 VPLL: 1.1V */
+	val = max8997_reg_ldo(1100000) | EN_LDO;
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
+
+	/* LDO11 TOUCH: 2.8V */
+	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
+
+	/* LDO12 VTCAM: 1.8V */
+	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
+
+	/* LDO13 VCC_3.0_LCD: 3.0V */
+	val = max8997_reg_ldo(3000000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
+
+	/* LDO14 MOTOR: 3.0V */
+	val = max8997_reg_ldo(3000000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
+
+	/* LDO15 LED_A: 2.8V */
+	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
+
+	/* LDO16 CAM_SENSOR: 1.8V */
+	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
+
+	/* LDO17 VTF: 2.8V */
+	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
+
+	/* LDO18 TOUCH_LED 3.3V */
+	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
+
+	/* LDO21 VDDQ: 1.2V */
+	val = max8997_reg_ldo(1200000) | EN_LDO;
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
+
+	/* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
+	val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
+		ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
+	ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
+
+	if (ret) {
+		puts("MAX8997 PMIC setting error!\n");
+		return -1;
+	}
+	return 0;
+}
+
+int exynos_power_init(void)
+{
+	int chrg, ret;
+	struct power_battery *pb;
+	struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
+
+	/*
+	 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
+	 * to logical I2C adapter 0
+	 *
+	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
+	 * to logical I2C adapter 1
+	 */
+	ret = pmic_init(I2C_5);
+	ret |= pmic_init_max8997();
+	ret |= power_fg_init(I2C_9);
+	ret |= power_muic_init(I2C_5);
+	ret |= power_bat_init(0);
+	if (ret)
+		return ret;
+
+	p_fg = pmic_get("MAX17042_FG");
+	if (!p_fg) {
+		puts("MAX17042_FG: Not found\n");
+		return -ENODEV;
+	}
+
+	p_chrg = pmic_get("MAX8997_PMIC");
+	if (!p_chrg) {
+		puts("MAX8997_PMIC: Not found\n");
+		return -ENODEV;
+	}
+
+	p_muic = pmic_get("MAX8997_MUIC");
+	if (!p_muic) {
+		puts("MAX8997_MUIC: Not found\n");
+		return -ENODEV;
+	}
+
+	p_bat = pmic_get("BAT_TRATS");
+	if (!p_bat) {
+		puts("BAT_TRATS: Not found\n");
+		return -ENODEV;
+	}
+
+	p_fg->parent =  p_bat;
+	p_chrg->parent = p_bat;
+	p_muic->parent = p_bat;
+
+	p_bat->low_power_mode = trats_low_power_mode;
+	p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
+
+	pb = p_bat->pbat;
+	chrg = p_muic->chrg->chrg_type(p_muic);
+	debug("CHARGER TYPE: %d\n", chrg);
+
+	if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
+		puts("No battery detected\n");
+		return -1;
+	}
+
+	p_fg->fg->fg_battery_check(p_fg, p_bat);
+
+	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
+		puts("CHARGE Battery !\n");
+
+	return 0;
+}
+
+static unsigned int get_hw_revision(void)
+{
+	struct exynos4_gpio_part1 *gpio =
+		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+	int hwrev = 0;
+	int i;
+
+	/* hw_rev[3:0] == GPE1[3:0] */
+	for (i = 0; i < 4; i++) {
+		s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
+		s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
+	}
+
+	udelay(1);
+
+	for (i = 0; i < 4; i++)
+		hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
+
+	debug("hwrev 0x%x\n", hwrev);
+
+	return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+	int hwrev;
+
+	hwrev = get_hw_revision();
+
+	board_rev |= hwrev;
+}
+
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+	int ret = 0;
+	u32 val = 0;
+	struct pmic *p = pmic_get("MAX8997_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	if (pmic_probe(p))
+		return -1;
+
+	if (on) {
+		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
+				      ENSAFEOUT1, LDO_ON);
+		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
+
+		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
+	} else {
+		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
+
+		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
+		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
+				      ENSAFEOUT1, LDO_OFF);
+	}
+
+	if (ret) {
+		puts("MAX8997 LDO setting error!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+struct s3c_plat_otg_data s5pc210_otg_data = {
+	.phy_control	= s5pc210_phy_control,
+	.regs_phy	= EXYNOS4_USBPHY_BASE,
+	.regs_otg	= EXYNOS4_USBOTG_BASE,
+	.usb_phy_ctrl	= EXYNOS4_USBPHY_CONTROL,
+	.usb_flags	= PHY0_SLEEP,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+	struct pmic *muic = pmic_get("MAX8997_MUIC");
+	if (!muic)
+		return 0;
+
+	return !!muic->chrg->chrg_type(muic);
+}
+#endif
+
+static void pmic_reset(void)
+{
+	struct exynos4_gpio_part2 *gpio =
+		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+
+	s5p_gpio_direction_output(&gpio->x0, 7, 1);
+	s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
+}
+
+static void board_clock_init(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+
+	writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
+	writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
+	writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
+	writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
+
+	writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
+	writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
+	writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
+	writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
+	writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
+	writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
+	writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
+	writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
+	writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
+	writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
+	writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
+
+	writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
+	writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
+	writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
+	writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
+	writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
+	writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
+	writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
+	writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
+	writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
+	writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
+	writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
+	writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
+
+	writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
+	writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
+	writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
+	writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
+	writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
+	writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
+	writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
+	writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
+	writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
+	writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
+	writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
+	writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
+}
+
+static void board_power_init(void)
+{
+	struct exynos4_power *pwr =
+		(struct exynos4_power *)samsung_get_base_power();
+
+	/* PS HOLD */
+	writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
+
+	/* Set power down */
+	writel(0, (unsigned int)&pwr->cam_configuration);
+	writel(0, (unsigned int)&pwr->tv_configuration);
+	writel(0, (unsigned int)&pwr->mfc_configuration);
+	writel(0, (unsigned int)&pwr->g3d_configuration);
+	writel(0, (unsigned int)&pwr->lcd1_configuration);
+	writel(0, (unsigned int)&pwr->gps_configuration);
+	writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+	/* It is necessary to power down core 1 */
+	/* to successfully boot CPU1 in kernel */
+	writel(0, (unsigned int)&pwr->arm_core1_configuration);
+}
+
+static void exynos_uart_init(void)
+{
+	struct exynos4_gpio_part2 *gpio2 =
+		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+
+	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
+	s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
+	s5p_gpio_direction_output(&gpio2->y4, 7, 1);
+}
+
+int exynos_early_init_f(void)
+{
+	wdt_stop();
+	pmic_reset();
+	board_clock_init();
+	exynos_uart_init();
+	board_power_init();
+
+	return 0;
+}
+
+void exynos_reset_lcd(void)
+{
+	struct exynos4_gpio_part2 *gpio2 =
+		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+
+	s5p_gpio_direction_output(&gpio2->y4, 5, 1);
+	udelay(10000);
+	s5p_gpio_direction_output(&gpio2->y4, 5, 0);
+	udelay(10000);
+	s5p_gpio_direction_output(&gpio2->y4, 5, 1);
+}
+
+int lcd_power(void)
+{
+	int ret = 0;
+	struct pmic *p = pmic_get("MAX8997_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	if (pmic_probe(p))
+		return 0;
+
+	/* LDO15 voltage: 2.2v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
+	/* LDO13 voltage: 3.0v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
+
+	if (ret) {
+		puts("MAX8997 LDO setting error!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int mipi_power(void)
+{
+	int ret = 0;
+	struct pmic *p = pmic_get("MAX8997_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	if (pmic_probe(p))
+		return 0;
+
+	/* LDO3 voltage: 1.1v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
+	/* LDO4 voltage: 1.8v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
+
+	if (ret) {
+		puts("MAX8997 LDO setting error!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+	get_tizen_logo_info(vid);
+#endif
+#ifdef CONFIG_S6E8AX0
+	s6e8ax0_init();
+	setenv("lcdinfo", "lcd=s6e8ax0");
+#endif
+}