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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/qemu-mips/lowlevel_init.S
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/qemu-mips/lowlevel_init.S')
-rw-r--r--qemu/roms/u-boot/board/qemu-mips/lowlevel_init.S40
1 files changed, 40 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/qemu-mips/lowlevel_init.S b/qemu/roms/u-boot/board/qemu-mips/lowlevel_init.S
new file mode 100644
index 000000000..b0f707270
--- /dev/null
+++ b/qemu/roms/u-boot/board/qemu-mips/lowlevel_init.S
@@ -0,0 +1,40 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set K0=3)
+ */
+ li t1, 0x00000003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+ jr ra
+ nop