Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

4 files changed, 1014 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/ifm/ac14xx/Makefile b/qemu/roms/u-boot/board/ifm/ac14xx/Makefile
new file mode 100644
index 000000000..55def6041
--- /dev/null
+++ b/qemu/roms/u-boot/board/ifm/ac14xx/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= ac14xx.o
diff --git a/qemu/roms/u-boot/board/ifm/ac14xx/ac14xx.c b/qemu/roms/u-boot/board/ifm/ac14xx/ac14xx.c
new file mode 100644
index 000000000..0fbdfdbf7
--- /dev/null
+++ b/qemu/roms/u-boot/board/ifm/ac14xx/ac14xx.c
@@ -0,0 +1,615 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2010 ifm ecomatic GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+static int eeprom_diag;
+static int mac_diag;
+static int gpio_diag;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_configure(void)
+{
+	immap_t *im;
+	gpio512x_t *gpioregs;
+
+	im = (immap_t *) CONFIG_SYS_IMMR;
+	gpioregs = &im->gpio;
+	out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
+	out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
+
+	/*
+	 * out_be32(&gpioregs->gpdir, 0xC2293020);
+	 * workaround for a hardware effect: configure direction in pieces,
+	 * setting all outputs at once drops the reset line too low and
+	 * makes us lose the MII connection (breaks ethernet for us)
+	 */
+	out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
+	setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
+	udelay(10);
+	setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
+	udelay(10);
+	setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
+	udelay(10);
+	setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
+
+	/* to turn from red to yellow when U-Boot runs */
+	setbits_be32(&gpioregs->gpdat, 0x00002020);
+	out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
+	out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
+	out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
+	out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
+}
+
+/* the physical location of the pins */
+#define GPIOKEY_ROW_BITMASK	0x40000000
+#define GPIOKEY_ROW_UPPER	0
+#define GPIOKEY_ROW_LOWER	1
+
+#define GPIOKEY_COL0_BITMASK	0x20000000
+#define GPIOKEY_COL1_BITMASK	0x10000000
+#define GPIOKEY_COL2_BITMASK	0x08000000
+
+/* the logical presentation of pressed keys */
+#define GPIOKEY_BIT_FNLEFT	(1 << 5)
+#define GPIOKEY_BIT_FNRIGHT	(1 << 4)
+#define GPIOKEY_BIT_DIRUP	(1 << 3)
+#define GPIOKEY_BIT_DIRLEFT	(1 << 2)
+#define GPIOKEY_BIT_DIRRIGHT	(1 << 1)
+#define GPIOKEY_BIT_DIRDOWN	(1 << 0)
+
+/* the hotkey combination which starts recovery */
+#define GPIOKEY_BITS_RECOVERY	(GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
+				 GPIOKEY_BIT_DIRDOWN)
+
+static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
+{
+
+	if (row)
+		setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+	else
+		clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+	udelay(10);
+}
+
+static u32 gpio_querykbd(void)
+{
+	immap_t *im;
+	gpio512x_t *gpioregs;
+	u32 keybits;
+	u32 input;
+
+	im = (immap_t *)CONFIG_SYS_IMMR;
+	gpioregs = &im->gpio;
+	keybits = 0;
+
+	/* query upper row */
+	gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
+	input = in_be32(&gpioregs->gpdat);
+	if ((input & GPIOKEY_COL0_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_FNLEFT;
+	if ((input & GPIOKEY_COL1_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRUP;
+	if ((input & GPIOKEY_COL2_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_FNRIGHT;
+
+	/* query lower row */
+	gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
+	input = in_be32(&gpioregs->gpdat);
+	if ((input & GPIOKEY_COL0_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRLEFT;
+	if ((input & GPIOKEY_COL1_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRRIGHT;
+	if ((input & GPIOKEY_COL2_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRDOWN;
+
+	/* return bit pattern for keys */
+	return keybits;
+}
+
+/* excerpt from the recovery's hw_info.h */
+
+struct __attribute__ ((__packed__)) eeprom_layout {
+	char	magic[3];	/** 'ifm' */
+	u8	len[2];		/** content length without magic/len fields */
+	u8	version[3];	/** structure version */
+	u8	type;		/** type of PCB */
+	u8	reserved[0x37];	/** padding up to offset 0x40 */
+	u8	macaddress[6];	/** ethernet MAC (for the mainboard) @0x40 */
+};
+
+#define HW_COMP_MAINCPU 2
+
+static struct eeprom_layout eeprom_content;
+static int eeprom_was_read;	/* has_been_read */
+static int eeprom_is_valid;
+static int eeprom_version;
+
+#define get_eeprom_field_int(name) ({ \
+	int value; \
+	int idx; \
+	value = 0; \
+	for (idx = 0; idx < sizeof(name); idx++) { \
+		value <<= 8; \
+		value |= name[idx]; \
+	} \
+	value; \
+})
+
+static int read_eeprom(void)
+{
+	int eeprom_datalen;
+	int ret;
+
+	if (eeprom_was_read)
+		return 0;
+
+	eeprom_is_valid = 0;
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+			(uchar *)&eeprom_content, sizeof(eeprom_content));
+	if (eeprom_diag) {
+		printf("DIAG: %s() read rc[%d], size[%d]\n",
+			__func__, ret, sizeof(eeprom_content));
+	}
+
+	if (ret != 0)
+		return -1;
+
+	eeprom_was_read = 1;
+
+	/*
+	 * check validity of EEPROM content
+	 * (check version, length, optionally checksum)
+	 */
+	eeprom_is_valid = 1;
+	eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
+	eeprom_version = get_eeprom_field_int(eeprom_content.version);
+
+	if (eeprom_diag) {
+		printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
+			__func__, eeprom_content.magic[0],
+			eeprom_content.magic[1], eeprom_content.magic[2],
+			eeprom_datalen, eeprom_version, eeprom_content.type);
+	}
+	if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
+		eeprom_is_valid = 0;
+	if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
+		eeprom_is_valid = 0;
+	if ((eeprom_version != 1) && (eeprom_version != 2))
+		eeprom_is_valid = 0;
+	if (eeprom_content.type != HW_COMP_MAINCPU)
+		eeprom_is_valid = 0;
+
+	if (eeprom_diag)
+		printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
+
+	return ret;
+}
+
+int mac_read_from_eeprom(void)
+{
+	const u8 *mac;
+	const char *mac_txt;
+
+	if (read_eeprom()) {
+		printf("I2C EEPROM read failed.\n");
+		return -1;
+	}
+
+	if (!eeprom_is_valid) {
+		printf("I2C EEPROM content not valid\n");
+		return -1;
+	}
+
+	mac = NULL;
+	switch (eeprom_version) {
+	case 1:
+	case 2:
+		mac = (const u8 *)&eeprom_content.macaddress;
+		break;
+	}
+
+	if (mac && is_valid_ether_addr(mac)) {
+		eth_setenv_enetaddr("ethaddr", mac);
+		if (mac_diag) {
+			mac_txt = getenv("ethaddr");
+			if (mac_txt)
+				printf("DIAG: MAC value [%s]\n", mac_txt);
+			else
+				printf("DIAG: failed to setup MAC env\n");
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * BEWARE!
+ * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
+ * which the ADS, Aria or PDM360NG boards are using
+ * (the steps outlined here refer to the Micron datasheet)
+ */
+u32 sdram_init_seq[] = {
+	/* item 6, at least one NOP after CKE went high */
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 7, precharge all; item 8, tRP (20ns) */
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 9, extended mode register; item 10, tMRD 10ns) */
+	CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 11, (base) mode register _with_ reset DLL;
+	 * item 12, tMRD (10ns)
+	 */
+	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
+	CONFIG_SYS_MICRON_BMODE_PARAM,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 13, precharge all; item 14, tRP (20ns) */
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 15, auto refresh (i.e. refresh with CKE held high);
+	 * item 16, tRFC (70ns)
+	 */
+	CONFIG_SYS_DDRCMD_RFSH,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 17, auto refresh (i.e. refresh with CKE held high);
+	 * item 18, tRFC (70ns)
+	 */
+	CONFIG_SYS_DDRCMD_RFSH,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
+	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 21, "actually done", but make sure 200 DRAM clock cycles
+	 * have passed after DLL reset before READ requests are issued
+	 * (200 cycles at 160MHz -> 1.25 usec)
+	 */
+	/* EMPTY, optional, we don't do it */
+};
+
+phys_size_t initdram(int board_type)
+{
+	return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
+}
+
+int misc_init_r(void)
+{
+	u32 keys;
+	char *s;
+	int want_recovery;
+
+	/* we use bus I2C-0 for the on-board eeprom */
+	i2c_set_bus_num(0);
+
+	/* setup GPIO directions and initial values */
+	gpio_configure();
+
+	/*
+	 * enforce the start of the recovery system when
+	 * - the appropriate keys were pressed
+	 * - "some" external software told us to
+	 * - a previous installation was aborted or has failed
+	 */
+	want_recovery = 0;
+	keys = gpio_querykbd();
+	if (gpio_diag)
+		printf("GPIO keyboard status [0x%02X]\n", keys);
+	if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
+		printf("detected recovery request (keyboard)\n");
+		want_recovery = 1;
+	}
+	s = getenv("want_recovery");
+	if ((s != NULL) && (*s != '\0')) {
+		printf("detected recovery request (environment)\n");
+		want_recovery = 1;
+	}
+	s = getenv("install_in_progress");
+	if ((s != NULL) && (*s != '\0')) {
+		printf("previous installation has not completed\n");
+		want_recovery = 1;
+	}
+	s = getenv("install_failed");
+	if ((s != NULL) && (*s != '\0')) {
+		printf("previous installation has failed\n");
+		want_recovery = 1;
+	}
+	if (want_recovery) {
+		printf("enforced start of the recovery system\n");
+		setenv("bootcmd", "run recovery");
+	}
+
+	/*
+	 * boot the recovery system without waiting; boot the
+	 * production system without waiting by default, only
+	 * insert a pause (to provide a chance to get a prompt)
+	 * when GPIO keys were pressed during power on
+	 */
+	if (want_recovery)
+		setenv("bootdelay", "0");
+	else if (!keys)
+		setenv("bootdelay", "0");
+	else
+		setenv("bootdelay", "2");
+
+	/* get the ethernet MAC from I2C EEPROM */
+	mac_read_from_eeprom();
+
+	return 0;
+}
+
+/* setup specific IO pad configuration */
+static  iopin_t ioregs_init[] = {
+	{	/* LPC CS3 */
+		offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* LPC CS1 */
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC CS2 */
+		offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC CS4, CS5 */
+		offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* SDHC CLK, CMD, D0, D1, D2, D3 */
+		offsetof(struct ioctrl512x, io_control_pata_ior), 6,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* GPIO keyboard */
+		offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO DN1 PF, LCD power, DN2 PF */
+		offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO reset AS-i */
+		offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO reset safety */
+		offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO reset netX */
+		offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO ma2 en */
+		offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO SD CD, SD WP */
+		offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* FEC RX DV */
+		offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(2),
+	},
+	{	/* GPIO AS-i prog, AS-i done, LCD backlight */
+		offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO AS-i wdg */
+		offsetof(struct ioctrl512x, io_control_pci_req2), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO safety wdg */
+		offsetof(struct ioctrl512x, io_control_pci_req1), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO netX wdg */
+		offsetof(struct ioctrl512x, io_control_pci_req0), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO IRQ powerfail */
+		offsetof(struct ioctrl512x, io_control_pci_inta), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO AS-i PWRD */
+		offsetof(struct ioctrl512x, io_control_pci_frame), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO LED0, LED1 */
+		offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
+		offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* DIU clk */
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(2),
+	},
+	{	/* FEC TX ER, CRS */
+		offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
+		offsetof(struct ioctrl512x, io_control_irq0), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/*
+		 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
+		 * rdx 3-0, mdio, rx clk
+		 */
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	/* optional: make sure PSC3 remains the serial console */
+	{	/* LPC CS6 */
+		offsetof(struct ioctrl512x, io_control_psc3_4), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	/* make sure PSC4 remains available for SPI,
+	    *BUT* PSC4_1 is a GPIO kind of SS! */
+	{	/* enforce drive strength on the SPI pin */
+		offsetof(struct ioctrl512x, io_control_psc4_0), 5,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_psc4_1), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	/* optional: make sure PSC5 remains available for SPI */
+	{	/* enforce drive strength on the SPI pin */
+		offsetof(struct ioctrl512x, io_control_psc5_0), 5,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(1),
+	},
+	{	/* LPC TSIZ1 */
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* DIU hsync */
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* DIU vsync */
+		offsetof(struct ioctrl512x, io_control_psc6_4), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* PSC7, part of DIU RGB */
+		offsetof(struct ioctrl512x, io_control_psc7_0), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* PSC7, safety UART */
+		offsetof(struct ioctrl512x, io_control_psc7_2), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(0) | IO_PIN_DS(1),
+	},
+	{	/* DIU (part of) RGB[] */
+		offsetof(struct ioctrl512x, io_control_psc8_3), 16,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* DIU data enable */
+		offsetof(struct ioctrl512x, io_control_psc11_4), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	/* reduce LPB drive strength for improved EMI */
+	{	/* LPC OE, LPC RW */
+		offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC AX03 through LPC AD00 */
+		offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC CS5 */
+		offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* SDHC CLK */
+		offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* SDHC DATA */
+		offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+};
+
+int checkboard(void)
+{
+	puts("Board: ifm AC14xx\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+	iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/qemu/roms/u-boot/board/ifm/o2dnt2/Makefile b/qemu/roms/u-boot/board/ifm/o2dnt2/Makefile
new file mode 100644
index 000000000..64d6ba8c5
--- /dev/null
+++ b/qemu/roms/u-boot/board/ifm/o2dnt2/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= o2dnt2.o
diff --git a/qemu/roms/u-boot/board/ifm/o2dnt2/o2dnt2.c b/qemu/roms/u-boot/board/ifm/o2dnt2/o2dnt2.c
new file mode 100644
index 000000000..6716ffc9d
--- /dev/null
+++ b/qemu/roms/u-boot/board/ifm/o2dnt2/o2dnt2.c
@@ -0,0 +1,384 @@
+/*
+ * Partially derived from board code for digsyMTC,
+ * (C) Copyright 2009
+ * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+ *
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <net.h>
+#include <pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+enum ifm_sensor_type {
+	O2DNT		= 0x00,	/* !< O2DNT 32MB */
+	O2DNT2		= 0x01,	/* !< O2DNT2 64MB */
+	O3DNT		= 0x02,	/* !< O3DNT 32MB */
+	O3DNT_MIN	= 0x40,	/* !< O3DNT Minerva 32MB */
+	UNKNOWN		= 0xff,	/* !< Unknow sensor */
+};
+
+static enum ifm_sensor_type gt_ifm_sensor_type;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32(&sdram->ctrl, control | 0x80000000);
+
+	/* precharge all banks */
+	out_be32(&sdram->ctrl, control | 0x80000002);
+
+	/* auto refresh */
+	out_be32(&sdram->ctrl, control | 0x80000004);
+
+	/* set mode register */
+	out_be32(&sdram->mode, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32(&sdram->ctrl, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+phys_size_t initdram(int board_type)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+	if (gt_ifm_sensor_type == O2DNT2) {
+		/* activate SDRAM CS1 */
+		setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
+	}
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
+	out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
+
+	/* setup config registers */
+	out_be32(&sdram->config1, SDRAM_CONFIG1);
+	out_be32(&sdram->config2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32(&mmap_ctl->sdram0,
+			 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+		out_be32(&mmap_ctl->sdram0, 0); /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+					0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+					0x80000000);
+	}
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		out_be32(&mmap_ctl->sdram1, (dramsize |
+			 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
+	} else {
+		out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+		out_be32(&sdram->sdelay, 0x04);
+
+	return dramsize + dramsize2;
+}
+
+
+#define GPT_GPIO_IN	0x4
+
+int checkboard(void)
+{
+	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+	unsigned char board_config = 0;
+	int i;
+
+	/* switch gpt0 - gpt7 to input */
+	for (i = 0; i < 7; i++)
+		out_be32(&gpt[i].emsr, GPT_GPIO_IN);
+
+	/* get configuration byte on timer-port */
+	for (i = 0; i < 7; i++)
+		board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
+
+	puts("Board: ");
+
+	switch (board_config) {
+	case 0:
+		puts("O2DNT\n");
+		gt_ifm_sensor_type = O2DNT;
+		break;
+	case 1:
+		puts("O3DNT\n");
+		gt_ifm_sensor_type = O3DNT;
+		break;
+	case 2:
+		puts("O2DNT2\n");
+		gt_ifm_sensor_type = O2DNT2;
+		break;
+	case 64:
+		puts("O3DNT Minerva\n");
+		gt_ifm_sensor_type = O3DNT_MIN;
+		break;
+	default:
+		puts("Unknown\n");
+		gt_ifm_sensor_type = UNKNOWN;
+		break;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+	/*
+	 * Now, when we are in RAM, enable flash write access for detection
+	 * process. Note that CS_BOOT cannot be cleared when executing in flash.
+	 */
+	clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
+	/* disable CS_BOOT */
+	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
+	/* enable CS0 */
+	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
+
+	return 0;
+}
+
+#define MIIM_LXT971_LED_CFG_REG		0x14
+#define LXT971_LED_CFG_LINK_STATUS	0x4000
+#define LXT971_LED_CFG_RX_TX_ACTIVITY	0x0700
+#define LXT971_LED_CFG_LINK_ACTIVITY	0x00D0
+#define LXT971_LED_CFG_PULSE_STRETCH	0x0002
+/*
+ * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
+ */
+void reset_phy(void)
+{
+	/*
+	 * Set LED configuration bits.
+	 * It can't be done in misc_init_r() since FEC is not
+	 * initialized at this time. Therefore we do it here.
+	 */
+	miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
+			LXT971_LED_CFG_LINK_STATUS |
+			LXT971_LED_CFG_RX_TX_ACTIVITY |
+			LXT971_LED_CFG_LINK_ACTIVITY |
+			LXT971_LED_CFG_PULSE_STRETCH);
+}
+
+#if defined(CONFIG_POST)
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
+
+	/*
+	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+	 * CODEC or UART mode. Consumer IrDA should still be possible.
+	 */
+	clrbits_be32(&gpio->port_config, 0x07000000);
+	setbits_be32(&gpio->port_config, 0x03000000);
+
+	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+	setbits_be32(&gpio->simple_gpioe, 0x20000000);
+
+	/* Configure GPIO_IRDA_1 as input */
+	clrbits_be32(&gpio->simple_ddr, 0x20000000);
+
+	return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
+}
+#endif
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+	flash_info_t	*dev = &flash_info[0];
+	int off;
+	struct fdt_property *prop;
+	int len;
+	u32 *reg, *reg2;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+	if (off < 0) {
+		printf("Could not find fsl,mpc5200b-lpb node.\n");
+		return;
+	}
+
+	/* found compatible property */
+	prop = fdt_get_property_w(blob, off, "ranges", &len);
+	if (prop) {
+		reg = reg2 = (u32 *)&prop->data[0];
+
+		reg[2] = dev->start[0];
+		reg[3] = dev->size;
+		fdt_setprop(blob, off, "ranges", reg2, len);
+	} else
+		printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size(phys_addr_t base, int banknum);
+
+/* Update the flash baseaddr settings */
+int update_flash_size(int flash_size)
+{
+	struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+	flash_info_t *dev;
+	int i;
+	int size = 0;
+	unsigned long base = 0x0;
+	u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+	for (i = 0; i < 2; i++) {
+		dev = &flash_info[i];
+
+		if (dev->size) {
+			/* calculate new base addr for this chipselect */
+			base -= dev->size;
+			out_be32(cs_reg, START_REG(base));
+			cs_reg++;
+			out_be32(cs_reg, STOP_REG(base, dev->size));
+			cs_reg++;
+			/* recalculate the sectoraddr in the cfi driver */
+			size += flash_get_size(base, i);
+		}
+	}
+	flash_protect_default();
+	gd->bd->bi_flashstart = base;
+	return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int phy_addr = CONFIG_PHY_ADDR;
+	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
+
+	ft_cpu_setup(blob, bd);
+
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+	/* Update reg property in all nor flash nodes too */
+	fdt_fixup_nor_flash_size(blob);
+#endif
+	ft_adapt_flash_base(blob);
+#endif
+	/* fix up the phy address */
+	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */