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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c')
-rw-r--r--qemu/roms/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c71
1 files changed, 71 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/qemu/roms/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
new file mode 100644
index 000000000..8f4183b82
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ * Authors: York Sun <yorksun@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <fsl_diu_fb.h>
+#include "../common/pixis.h"
+
+#define PX_BRDCFG0_DLINK 0x10
+#define PX_BRDCFG0_DVISEL 0x08
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
+ unsigned long speed_ccb, temp, pixval;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000/pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ debug("DIU pixval = %lu\n", pixval);
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+ temp = *guts_clkdvdr & 0x2000FFFF;
+ *guts_clkdvdr = temp; /* turn off clock */
+ *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
+ debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ const char *name;
+ int gamma_fix = 0;
+ u32 pixel_format = 0x88883316;
+ u8 temp;
+
+ temp = in_8(&pixis->brdcfg0);
+
+ if (strncmp(port, "dlvds", 5) == 0) {
+ /* Dual link LVDS */
+ gamma_fix = 1;
+ temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL);
+ name = "Dual-Link LVDS";
+ } else if (strncmp(port, "lvds", 4) == 0) {
+ /* Single link LVDS */
+ temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK;
+ name = "Single-Link LVDS";
+ } else {
+ /* DVI */
+ if (in_8(&pixis->ver) == 1) /* Board version */
+ pixel_format = 0x88882317;
+ temp |= PX_BRDCFG0_DVISEL;
+ name = "DVI";
+ }
+
+ printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+ out_8(&pixis->brdcfg0, temp);
+
+ return fsl_diu_init(xres, yres, pixel_format, gamma_fix);
+}