Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

5 files changed, 0 insertions, 611 deletions

diff --git a/qemu/roms/u-boot/board/freescale/mpc837xemds/Makefile b/qemu/roms/u-boot/board/freescale/mpc837xemds/Makefile
deleted file mode 100644
index 70b2147c3..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc837xemds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc837xemds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/qemu/roms/u-boot/board/freescale/mpc837xemds/README b/qemu/roms/u-boot/board/freescale/mpc837xemds/README
deleted file mode 100644
index faf21c9ff..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc837xemds/README
+++ /dev/null
@@ -1,104 +0,0 @@
-Freescale MPC837xEMDS Board
------------------------------------------
-1.	Board Switches and Jumpers
-1.0	There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
-	For some reason, the HW designers describe the switch settings
-	in terms of 0 and 1, and then map that to physical switches where
-	the label "On" refers to logic 0 and "Off" is logic 1.
-
-	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
-	bits may contribute to signals that are numbered based at 0,
-	and some of those signals may be high-bit-number-0 too.  Heed
-	well the names and labels and do not get confused.
-
-		"Off" == 1
-		"On"  == 0
-
-	SW4[8] is the bit labeled 8 on Switch 4.
-	SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
-	SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
-		and bits labeled 8 is set as "Off".
-
-1.1	For the MPC837xEMDS Processor Board
-
-	First, make sure the board default setting is consistent with the
-	document shipped with your board. Then apply the following setting:
-	SW3[1-8]= 0011_0000  (BOOTSEQ, ROMLOC setting)
-	SW4[1-8]= 0000_0110  (core PLL setting)
-	SW5[1-8]= 1001_1000  (system PLL, boot up from low end of flash)
-	SW6[1-8]= 0000_1000  (HRCW is read from NOR FLASH)
-	SW7[1-8]= 0110_1101  (TSEC1/2 interface setting - RGMII)
-	J3 2-3, TSEC1 LVDD1 with 2.5V
-	J6 2-3, TSEC2 LVDD2 with 2.5V
-	J9 2-3, CLKIN from osc on board
-	J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
-	J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
-	    mounted, HRCW load from BCSR.
-
-	on board Oscillator: 66M
-
-2.	Memory Map
-
-2.1.	The memory map should look pretty much like this:
-
-	0x0000_0000	0x7fff_ffff	DDR			2G
-	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
-	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
-	0xc000_0000	0xdfff_ffff	Empty			512M
-	0xe000_0000	0xe00f_ffff	Int Mem Reg Space	1M
-	0xe010_0000	0xe02f_ffff	Empty			2M
-	0xe030_0000	0xe03f_ffff	PCI IO			1M
-	0xe040_0000	0xe05f_ffff	Empty			2M
-	0xe060_0000	0xe060_7fff	NAND Flash		32K
-	0xf400_0000	0xf7ff_ffff	Empty			64M
-	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
-	0xfe00_0000	0xffff_ffff	NOR Flash on CS0	32M
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
-	include/configs/MPC837XEMDS.h
-
-    CONFIG_MPC83xx	    MPC83xx family for both MPC837x and MPC8360
-    CONFIG_MPC837x	    MPC837x specific
-    CONFIG_MPC837XEMDS	    MPC837XEMDS board specific
-
-4. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-		make MPC837XEMDS_config
-		make
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
-	loadb
-	[Drop to kermit:
-	    ^\c
-	    send <u-boot-bin-image>
-	    c
-	]
-
-
-    Or via tftp:
-
-	tftp 40000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
-	tftp 40000 u-boot.bin
-	protect off fe000000 fe1fffff
-	erase fe000000 fe1fffff
-
-	cp.b 40000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-
-6. Notes
-	1) The console baudrate for MPC837XEMDS is 115200bps.
diff --git a/qemu/roms/u-boot/board/freescale/mpc837xemds/mpc837xemds.c b/qemu/roms/u-boot/board/freescale/mpc837xemds/mpc837xemds.c
deleted file mode 100644
index 0a3c9720d..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc837xemds/mpc837xemds.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <asm/fsl_enet.h>
-#include <spd_sdram.h>
-#include <tsec.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_esdhc.h>
-#include <fsl_mdio.h>
-#include <phy.h>
-#include "pci.h"
-#include "../common/pq-mds-pib.h"
-
-int board_early_init_f(void)
-{
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[0x9] &= ~0x04;
-	/* Clear all of the interrupt of BCSR */
-	bcsr[0xe] = 0xff;
-
-#ifdef CONFIG_FSL_SERDES
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	u32 spridr = in_be32(&immr->sysconf.spridr);
-
-	/* we check only part num, and don't look for CPU revisions */
-	switch (PARTID_NO_E(spridr)) {
-	case SPR_8377:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
-				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		break;
-	case SPR_8378:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
-				FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
-		break;
-	case SPR_8379:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
-				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
-				FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		break;
-	default:
-		printf("serdes not configured: unknown CPU part number: "
-				"%04x\n", spridr >> 16);
-		break;
-	}
-#endif /* CONFIG_FSL_SERDES */
-	return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bd)
-{
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
-	if (!hwconfig("esdhc"))
-		return 0;
-
-	/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
-	bcsr[0xc] |= 0x4c;
-
-	/* Set proper bits in SICR to allow SD signals through */
-	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
-	clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
-			SICRH_GPIO2_E_SD | SICRH_SPI_SD);
-
-	return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
-int board_eth_init(bd_t *bd)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	u32 rcwh = in_be32(&im->reset.rcwh);
-	u32 tsec_mode;
-	int num = 0;
-
-	/* New line after Net: */
-	printf("\n");
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-
-	printf(CONFIG_TSEC1_NAME ": ");
-
-	tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
-	if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
-		printf("RGMII\n");
-		/* this is default, no need to fixup */
-	} else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
-		printf("SGMII\n");
-		tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
-		tsec_info[num].flags = TSEC_GIGABIT;
-	} else {
-		printf("unsupported PHY type\n");
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-
-	printf(CONFIG_TSEC2_NAME ": ");
-
-	tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
-	if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
-		printf("RGMII\n");
-		/* this is default, no need to fixup */
-	} else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
-		printf("SGMII\n");
-		tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
-		tsec_info[num].flags = TSEC_GIGABIT;
-	} else {
-		printf("unsupported PHY type\n");
-	}
-	num++;
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bd, &mdio_info);
-
-	return tsec_eth_init(bd, tsec_info, num);
-}
-
-static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
-			    int phy_addr)
-{
-	const u32 *ph;
-	int off;
-	int err;
-
-	off = fdt_path_offset(blob, alias);
-	if (off < 0) {
-		printf("WARNING: could not find %s alias: %s.\n", alias,
-			fdt_strerror(off));
-		return;
-	}
-
-	err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
-
-	if (err) {
-		printf("WARNING: could not set phy-connection-type for %s: "
-			"%s.\n", alias, fdt_strerror(err));
-		return;
-	}
-
-	ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
-	if (!ph) {
-		printf("WARNING: could not get phy-handle for %s.\n",
-			alias);
-		return;
-	}
-
-	off = fdt_node_offset_by_phandle(blob, *ph);
-	if (off < 0) {
-		printf("WARNING: could not get phy node for %s: %s\n", alias,
-			fdt_strerror(off));
-		return;
-	}
-
-	phy_addr = cpu_to_fdt32(phy_addr);
-	err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
-	if (err < 0) {
-		printf("WARNING: could not set phy node's reg for %s: "
-			"%s.\n", alias, fdt_strerror(err));
-		return;
-	}
-}
-
-static void ft_tsec_fixup(void *blob, bd_t *bd)
-{
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	u32 rcwh = in_be32(&im->reset.rcwh);
-	u32 tsec_mode;
-
-#ifdef CONFIG_TSEC1
-	tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
-	if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
-		__ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
-#endif
-
-#ifdef CONFIG_TSEC2
-	tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
-	if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
-		__ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
-#endif
-}
-#else
-static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
-#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
-	pib_init();
-#endif
-	return 0;
-}
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-#if defined(CONFIG_SPD_EEPROM)
-	msize = spd_sdram();
-#else
-	msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/* Initialize DDR ECC byte */
-	ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
-	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
-#if (CONFIG_SYS_DDR_SIZE != 512)
-#warning Currenly any ddr size other than 512 is not supported
-#endif
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-	udelay(50000);
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-	udelay(1000);
-
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	udelay(1000);
-
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__("sync");
-	udelay(1000);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	udelay(2000);
-	return CONFIG_SYS_DDR_SIZE;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC837xEMDS\n");
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-int board_pci_host_broken(void)
-{
-	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
-	const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
-
-	/* It's always OK in case of external arbiter. */
-	if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
-		return 0;
-
-	if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
-		return 1;
-
-	return 0;
-}
-
-static void ft_pci_fixup(void *blob, bd_t *bd)
-{
-	const char *status = "broken (no arbiter)";
-	int off;
-	int err;
-
-	off = fdt_path_offset(blob, "pci0");
-	if (off < 0) {
-		printf("WARNING: could not find pci0 alias: %s.\n",
-			fdt_strerror(off));
-		return;
-	}
-
-	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
-	if (err) {
-		printf("WARNING: could not set status for pci0: %s.\n",
-			fdt_strerror(err));
-		return;
-	}
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	ft_tsec_fixup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
-	fdt_fixup_esdhc(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-	if (board_pci_host_broken())
-		ft_pci_fixup(blob, bd);
-	ft_pcie_fixup(blob, bd);
-#endif
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/qemu/roms/u-boot/board/freescale/mpc837xemds/pci.c b/qemu/roms/u-boot/board/freescale/mpc837xemds/pci.c
deleted file mode 100644
index 39c40e5cc..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc837xemds/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <asm/fsl_i2c.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static int is_pex_x2(void)
-{
-	const char *pex_x2 = getenv("pex_x2");
-
-	if (pex_x2 && !strcmp(pex_x2, "yes"))
-		return 1;
-	return 0;
-}
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-	u32 spridr = in_be32(&immr->sysconf.spridr);
-	int pex2 = is_pex_x2();
-
-	if (board_pci_host_broken())
-		goto skip_pci;
-
-	/* Enable all 5 PCI_CLK_OUTPUTS */
-	clk->occr |= 0xf8000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	udelay(2000);
-
-	mpc83xx_pci_init(1, reg);
-skip_pci:
-	/* There is no PEX in MPC8379 parts. */
-	if (PARTID_NO_E(spridr) == SPR_8379)
-		return;
-
-	if (pex2)
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-	else
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	if (!pex2)
-		out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
-}
-
-void ft_pcie_fixup(void *blob, bd_t *bd)
-{
-	const char *status = "disabled (PCIE1 is x2)";
-
-	if (!is_pex_x2())
-		return;
-
-	do_fixup_by_path(blob, "pci2", "status", status,
-			 strlen(status) + 1, 1);
-}
diff --git a/qemu/roms/u-boot/board/freescale/mpc837xemds/pci.h b/qemu/roms/u-boot/board/freescale/mpc837xemds/pci.h
deleted file mode 100644
index fd7a916af..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc837xemds/pci.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BOARD_MPC837XEMDS_PCI_H
-#define __BOARD_MPC837XEMDS_PCI_H
-
-extern void ft_pcie_fixup(void *blob, bd_t *bd);
-
-#endif /* __BOARD_MPC837XEMDS_PCI_H */