Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

4 files changed, 0 insertions, 586 deletions

diff --git a/qemu/roms/u-boot/board/freescale/mpc8349emds/Makefile b/qemu/roms/u-boot/board/freescale/mpc8349emds/Makefile
deleted file mode 100644
index 5c315f9f6..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8349emds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mpc8349emds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/qemu/roms/u-boot/board/freescale/mpc8349emds/ddr.c b/qemu/roms/u-boot/board/freescale/mpc8349emds/ddr.c
deleted file mode 100644
index aae003d12..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8349emds/ddr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{2,  300,    4,   4,    2,  0},
-	{2,  365,    4,   6,    2,  0},
-	{2,  450,    4,   7,    2,  0},
-	{2,  850,    4,  31,    2,  0},
-	{1,  300,    4,   4,    2,  0},
-	{1,  365,    4,   6,    2,  0},
-	{1,  450,    4,   7,    2,  0},
-	{1,  850,    4,  31,    2,  0},
-	{}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	unsigned int i;
-	ulong ddr_freq;
-
-	if (ctrl_num != 0)	/* we have only one controller */
-		return;
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-		if (pdimm[i].n_ranks)
-			break;
-	}
-	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)	/* no DIMM */
-		return;
-
-	pbsp = udimm0;
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks ==  pdimm[i].n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->twot_en = pbsp_highest->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	popts->dqs_config = 0;	/* only true DQS signal is used on board */
-}
diff --git a/qemu/roms/u-boot/board/freescale/mpc8349emds/mpc8349emds.c b/qemu/roms/u-boot/board/freescale/mpc8349emds/mpc8349emds.c
deleted file mode 100644
index d9092201a..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8349emds/mpc8349emds.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spi.h>
-#include <miiphy.h>
-#ifdef CONFIG_SYS_FSL_DDR2
-#include <fsl_ddr_sdram.h>
-#else
-#include <spd_sdram.h>
-#endif
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-int fixed_sdram(void);
-void sdram_init(void);
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-int board_early_init_f (void)
-{
-	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
-
-	/* Enable flash write */
-	bcsr[1] &= ~0x01;
-
-#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
-	/* Use USB PHY on SYS board */
-	bcsr[5] |= 0x02;
-#endif
-
-	return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	phys_size_t msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_SYS_FSL_DDR2
-	msize = spd_sdram() * 1024 * 1024;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	ddr_enable_ecc(msize);
-#endif
-#else
-	msize = fsl_ddr_sdram();
-#endif
-#else
-	msize = fixed_sdram() * 1024 * 1024;
-#endif
-	/*
-	 * Initialize SDRAM if it is on local bus.
-	 */
-	sdram_init();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE;
-	u32 ddr_size = msize << 20;	/* DDR size in bytes */
-	u32 ddr_size_log2 = __ilog2(ddr_size);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
-	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[2].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
-				CSBNDS_EA_SHIFT) & CSBNDS_EA);
-	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-
-	/* currently we use only one CS, so disable the other banks */
-	im->ddr.cs_config[0] = 0;
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
-	im->ddr.sdram_cfg =
-		SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
-		| SDRAM_CFG_2T_EN
-#endif
-		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
-#if defined (CONFIG_DDR_32BIT)
-	/* for 32-bit mode burst length is 8 */
-	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
-	udelay(200);
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	return msize;
-}
-#endif/*!CONFIG_SYS_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
-	/*
-	 * Warning: do not read the BCSR registers here
-	 *
-	 * There is a timing bug in the 8349E and 8349EA BCSR code
-	 * version 1.2 (read from BCSR 11) that will cause the CFI
-	 * flash initialization code to overwrite BCSR 0, disabling
-	 * the serial ports and gigabit ethernet
-	 */
-
-	puts("Board: Freescale MPC8349EMDS\n");
-	return 0;
-}
-
-/*
- * if MPC8349EMDS is soldered with SDRAM
- */
-#if defined(CONFIG_SYS_BR2_PRELIM)  \
-	&& defined(CONFIG_SYS_OR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
-	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void sdram_init(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &immap->im_lbc;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
-	/*
-	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
-	 */
-
-	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	asm("sync");
-
-	/*
-	 * Configure the SDRAM controller Machine Mode Register.
-	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
-	asm("sync");
-	/*1 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*2 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*3 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*4 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*5 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*6 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*7 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-	/*8 times*/
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
-	asm("sync");
-	*sdram_addr = 0xff;
-	udelay(100);
-}
-#else
-void sdram_init(void)
-{
-}
-#endif
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK	0x80000000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat &= ~SPI_CS_MASK;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat |=  SPI_CS_MASK;
-}
-#endif /* CONFIG_HARD_SPI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-}
-#endif
diff --git a/qemu/roms/u-boot/board/freescale/mpc8349emds/pci.c b/qemu/roms/u-boot/board/freescale/mpc8349emds/pci.c
deleted file mode 100644
index 9f7324fed..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8349emds/pci.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-#ifndef CONFIG_PCISLAVE
-void pib_init(void)
-{
-	u8 val8, orig_i2c_bus;
-	/*
-	 * Assign PIB PMC slot to desired PCI bus
-	 */
-	/* Switch temporarily to I2C bus #2 */
-	orig_i2c_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	val8 = 0;
-	i2c_write(0x23, 0x6, 1, &val8, 1);
-	i2c_write(0x23, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x23, 0x2, 1, &val8, 1);
-	i2c_write(0x23, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x26, 0x6, 1, &val8, 1);
-	val8 = 0x34;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(PCI_64BIT)
-	val8 = 0xf4;	/* PMC2:PCI1/64-bit */
-#elif defined(PCI_ALL_PCI1)
-	val8 = 0xf3;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(PCI_ONE_PCI1)
-	val8 = 0xf9;	/* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
-#else
-	val8 = 0xf5;	/* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
-#endif
-	i2c_write(0x26, 0x2, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-	val8 = 0;
-	i2c_write(0x27, 0x6, 1, &val8, 1);
-	i2c_write(0x27, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x27, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x27, 0x3, 1, &val8, 1);
-	asm("eieio");
-
-#if defined(PCI_64BIT)
-	printf("PCI1: 64-bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
-	printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(PCI_ONE_PCI1)
-	printf("PCI1: 32-bit on PMC1\n");
-	printf("PCI2: 32-bit on PMC2, PMC3\n");
-#else
-	printf("PCI1: 32-bit on PMC1, PMC2\n");
-	printf("PCI2: 32-bit on PMC3\n");
-#endif
-	/* Reset to original I2C bus */
-	i2c_set_bus_num(orig_i2c_bus);
-}
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-	/* Enable all 8 PCI_CLK_OUTPUTS */
-	clk->occr = 0xff000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-
-#else
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
-	pci_ctrl->pitar0 = 0x0;
-	pci_ctrl->pibar0 = 0x0;
-	pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			   PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar1  = 0x0;
-	pci_ctrl->pibar1  = 0x0;
-	pci_ctrl->piebar1 = 0x0;
-	pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar2  = 0x0;
-	pci_ctrl->pibar2  = 0x0;
-	pci_ctrl->piebar2 = 0x0;
-	pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
-#endif /* CONFIG_PCISLAVE */