diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/freescale/b4860qds/b4_pbi.cfg | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/freescale/b4860qds/b4_pbi.cfg')
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/b4860qds/b4_pbi.cfg | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/freescale/b4860qds/b4_pbi.cfg b/qemu/roms/u-boot/board/freescale/b4860qds/b4_pbi.cfg new file mode 100644 index 000000000..05377bac5 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/b4860qds/b4_pbi.cfg @@ -0,0 +1,30 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Flush PBL data +09138000 00000000 +091380c0 00000000 |