Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

4 files changed, 549 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/etin/kvme080/Makefile b/qemu/roms/u-boot/board/etin/kvme080/Makefile
new file mode 100644
index 000000000..d1b6f3044
--- /dev/null
+++ b/qemu/roms/u-boot/board/etin/kvme080/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= kvme080.o multiverse.o
diff --git a/qemu/roms/u-boot/board/etin/kvme080/kvme080.c b/qemu/roms/u-boot/board/etin/kvme080/kvme080.c
new file mode 100644
index 000000000..baf4cbc4d
--- /dev/null
+++ b/qemu/roms/u-boot/board/etin/kvme080/kvme080.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+int checkboard(void)
+{
+	puts ("Board: KVME080\n");
+	return 0;
+}
+
+unsigned long setdram(int m, int row, int col, int bank)
+{
+	int i;
+	unsigned long start, end;
+	uint32_t mccr1;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	start = CONFIG_SYS_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned int msr;
+	long int size = 0;
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
+	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
+	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
+	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
+	mtmsr(msr);
+
+	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
+		size = 0x20000000;	/* 512MB */
+	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
+		size = 0x10000000;	/* 256MB */
+	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
+		size = 0x10000000;	/* 256MB */
+	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
+		size = 0x08000000;	/* 128MB */
+	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
+		size = 0x08000000;	/* 128MB */
+	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
+		size = 0x04000000;	/* 64MB */
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
+	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
+	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
+	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
+	mtmsr(msr);
+
+	return size;
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_early_init_f(void)
+{
+	*(volatile unsigned char *)(0xff080120) = 0xfb;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	unsigned int msr;
+
+	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
+	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
+	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtmsr(msr);
+
+	return 0;
+}
+
+extern int multiverse_init(void);
+
+int misc_init_r(void)
+{
+	multiverse_init();
+	return 0;
+}
+
+void *nvram_read(void *dest, const long src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*) dest;
+	volatile uchar *s = (volatile uchar*) src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+	return dest;
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*)dest;
+	volatile uchar *s = (volatile uchar*)src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/qemu/roms/u-boot/board/etin/kvme080/multiverse.c b/qemu/roms/u-boot/board/etin/kvme080/multiverse.c
new file mode 100644
index 000000000..2bcfe2ea0
--- /dev/null
+++ b/qemu/roms/u-boot/board/etin/kvme080/multiverse.c
@@ -0,0 +1,184 @@
+/*
+ * multiverse.c
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ *	    dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <linux/compiler.h>
+
+#include "multiverse.h"
+
+static unsigned long vme_asi_addr;
+static unsigned long vme_iack_addr;
+static unsigned long pci_reg_addr;
+static unsigned long vme_reg_addr;
+
+int multiv_reset(unsigned long base)
+{
+	writeb(0x09, base + VME_SLAVE32_AM);
+	writeb(0x39, base + VME_SLAVE24_AM);
+	writeb(0x29, base + VME_SLAVE16_AM);
+	writeb(0x2f, base + VME_SLAVE_REG_AM);
+	writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
+	writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
+	writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
+#ifdef A32_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
+				base + VME_SLAVE32_MASK);
+		writeb(0x01, base + VME_SLAVE32_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE32_MASK);
+		writeb(0x00, base + VME_SLAVE32_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE32_MASK);
+	writeb(0x00, base + VME_SLAVE32_EN);
+#endif
+#ifdef A24_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
+				base + VME_SLAVE24_MASK);
+		writeb(0x01, base + VME_SLAVE24_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE24_MASK);
+		writeb(0x00, base + VME_SLAVE24_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE24_MASK);
+	writeb(0x00, base + VME_SLAVE24_EN);
+#endif
+#ifdef A16_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
+				base + VME_SLAVE16_MASK);
+		writeb(0x01, base + VME_SLAVE16_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE16_MASK);
+		writeb(0x00, base + VME_SLAVE16_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE16_MASK);
+	writeb(0x00, base + VME_SLAVE16_EN);
+#endif
+#ifdef REG_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
+				base + VME_SLAVE_REG_MASK);
+		writeb(0x01, base + VME_SLAVE_REG_EN);
+	} else {
+		writeb(0xf8, base + VME_SLAVE_REG_MASK);
+	}
+#else
+	writeb(0xf8, base + VME_SLAVE_REG_MASK);
+#endif
+	writeb(0x09, base + VME_MASTER32_AM);
+	writeb(0x39, base + VME_MASTER24_AM);
+	writeb(0x29, base + VME_MASTER16_AM);
+	writeb(0x2f, base + VME_MASTER_REG_AM);
+	writel(0x00000000, base + VME_RMW_ADRS);
+	writeb(0x00, base + VME_IRQ);
+	writeb(0x00, base + VME_INT_EN);
+	writel(0x00000000, base + VME_IRQ1_REG);
+	writel(0x00000000, base + VME_IRQ2_REG);
+	writel(0x00000000, base + VME_IRQ3_REG);
+	writel(0x00000000, base + VME_IRQ4_REG);
+	writel(0x00000000, base + VME_IRQ5_REG);
+	writel(0x00000000, base + VME_IRQ6_REG);
+	writel(0x00000000, base + VME_IRQ7_REG);
+	return 0;
+}
+
+void multiv_auto_slot_id(unsigned long base)
+{
+	__maybe_unused unsigned int vector;
+	int slot_id = 1;
+	if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
+		*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
+		writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
+		writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
+				base + VME_CTRL);
+		while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
+		if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+			while (readb(base + VME_INT) & 0x04) {
+				vector = *(volatile unsigned int*)
+					(vme_iack_addr + VME_IACK2);
+				*(unsigned char*)(vme_asi_addr + 0x7ffff)
+					= (slot_id << 3) & 0xff;
+				slot_id ++;
+				if (slot_id > 31)
+					break;
+			}
+		}
+	}
+}
+
+int multiverse_init(void)
+{
+	int i;
+	pci_dev_t pdev;
+	unsigned int bar[6];
+
+	pdev = pci_find_device(0x1895, 0x0001, 0);
+
+	if (pdev == 0)
+		return -1;
+
+	for (i = 0; i < 6; i++)
+		pci_read_config_dword (pdev,
+				PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
+
+	pci_reg_addr = bar[0];
+	vme_reg_addr = bar[1] + 0x00F00000;
+	vme_iack_addr = bar[1] + 0x00200000;
+	vme_asi_addr = bar[3];
+
+	pci_write_config_dword (pdev, PCI_COMMAND,
+		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	writel(0xFF000000, pci_reg_addr + P_TA1);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL1);
+	writel(0xf0000000, pci_reg_addr + P_TA2);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL2);
+	writel(0xF1000000, pci_reg_addr + P_TA3);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL3);
+	writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
+	writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL5);
+
+	writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
+	writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
+	writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL1);
+
+	writel(0xF0000000, pci_reg_addr + W_BA2);
+	writel(0xFF000000, pci_reg_addr + W_AM2);
+	writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL2);
+
+	writel(0xFF000000, pci_reg_addr + W_BA3);
+	writel(0xFF000000, pci_reg_addr + W_AM3);
+	writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL3);
+
+	writel(0x00000001, pci_reg_addr + W_ERR_CS);
+	writel(0x00000001, pci_reg_addr + P_ERR_CS);
+
+	multiv_reset(vme_reg_addr);
+	writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
+		vme_reg_addr + VME_CTRL);
+
+	multiv_auto_slot_id(vme_reg_addr);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/board/etin/kvme080/multiverse.h b/qemu/roms/u-boot/board/etin/kvme080/multiverse.h
new file mode 100644
index 000000000..b3b79b7ee
--- /dev/null
+++ b/qemu/roms/u-boot/board/etin/kvme080/multiverse.h
@@ -0,0 +1,173 @@
+/*
+ * multiverse.h
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ *	    dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MULTIVERSE_H__
+#define __MULTIVERSE_H__
+
+#define VME_A32_MSTR_BUS	0x90000000
+#define VME_A32_MSTR_SIZE	0x01000000
+
+#define VME_A32_SLV_SIZE	0x01000000
+
+#define VME_A32_SLV_BUS		0x90000000
+#define VME_A24_SLV_BUS		0x00000000
+#define VME_A16_SLV_BUS		0x00000000
+
+#define VME_A32_SLV_LOCAL	0x00000000
+#define VME_A24_SLV_LOCAL	0x00000000
+#define VME_A16_SLV_LOCAL	0x00000000
+
+#define A32_SLV_WINDOW
+#undef	A24_SLV_WINDOW
+#undef	A16_SLV_WINDOW
+#undef	REG_SLV_WINDOW
+
+/* PCI Registers */
+
+#define P_IMG_CTRL0		0x100
+#define P_BA0			0x104
+#define P_AM0			0x108
+#define P_TA0			0x10C
+#define P_IMG_CTRL1		0x110
+#define P_BA1			0x114
+#define P_AM1			0x118
+#define P_TA1			0x11C
+#define P_IMG_CTRL2		0x120
+#define P_BA2			0x124
+#define P_AM2			0x128
+#define P_TA2			0x12C
+#define P_IMG_CTRL3		0x130
+#define P_BA3			0x134
+#define P_AM3			0x138
+#define P_TA3			0x13C
+#define P_IMG_CTRL4		0x140
+#define P_BA4			0x144
+#define P_AM4			0x148
+#define P_TA4			0x14C
+#define P_IMG_CTRL5		0x150
+#define P_BA5			0x154
+#define P_AM5			0x158
+#define P_TA5			0x15C
+#define P_ERR_CS		0x160
+#define P_ERR_ADDR		0x164
+#define P_ERR_DATA		0x168
+
+#define WB_CONF_SPC_BAR		0x180
+#define W_IMG_CTRL1		0x184
+#define W_BA1			0x188
+#define W_AM1			0x18C
+#define W_TA1			0x190
+#define W_IMG_CTRL2		0x194
+#define W_BA2			0x198
+#define W_AM2			0x19C
+#define W_TA2			0x1A0
+#define W_IMG_CTRL3		0x1A4
+#define W_BA3			0x1A8
+#define W_AM3			0x1AC
+#define W_TA3			0x1B0
+#define W_IMG_CTRL4		0x1B4
+#define W_BA4			0x1B8
+#define W_AM4			0x1BC
+#define W_TA4			0x1C0
+#define W_IMG_CTRL5		0x1C4
+#define W_BA5			0x1C8
+#define W_AM5			0x1CC
+#define W_TA5			0x1D0
+#define W_ERR_CS		0x1D4
+#define W_ERR_ADDR		0x1D8
+#define W_ERR_DATA		0x1DC
+#define CNF_ADDR		0x1E0
+#define CNF_DATA		0x1E4
+#define INT_ACK			0x1E8
+#define ICR			0x1EC
+#define ISR			0x1F0
+
+/* VME registers */
+
+#define VME_SLAVE32_AM		0x03
+#define VME_SLAVE24_AM		0x02
+#define VME_SLAVE16_AM		0x01
+#define VME_SLAVE_REG_AM	0x00
+#define VME_SLAVE32_A		0x07
+#define VME_SLAVE24_A		0x06
+#define VME_SLAVE16_A		0x05
+#define VME_SLAVE_REG_A		0x04
+#define VME_SLAVE32_MASK	0x0B
+#define VME_SLAVE24_MASK	0x0A
+#define VME_SLAVE16_MASK	0x09
+#define VME_SLAVE_REG_MASK	0x08
+#define VME_SLAVE32_EN		0x0F
+#define VME_SLAVE24_EN		0x0E
+#define VME_SLAVE16_EN		0x0D
+#define VME_SLAVE_REG_EN	0x0C
+#define VME_MASTER32_AM		0x13
+#define VME_MASTER24_AM		0x12
+#define VME_MASTER16_AM		0x11
+#define VME_MASTER_REG_AM	0x10
+#define VME_RMW_ADRS		0x14
+#define VME_MBOX		0x18
+#define VME_STATUS		0x1E
+#define VME_CTRL		0x1C
+#define VME_IRQ			0x20
+#define VME_INT_EN		0x21
+#define VME_INT			0x22
+#define VME_IRQ1_REG		0x24
+#define VME_IRQ2_REG		0x28
+#define VME_IRQ3_REG		0x2C
+#define VME_IRQ4_REG		0x30
+#define VME_IRQ5_REG		0x34
+#define VME_IRQ6_REG		0x38
+#define VME_IRQ7_REG		0x3C
+
+/* VME control register */
+
+#define VME_CTRL_BRDRST		0x01
+#define VME_CTRL_SYSRST		0x02
+#define VME_CTRL_RMW		0x04
+#define VME_CTRL_SHORT_D	0x08
+#define VME_CTRL_SYSFAIL	0x10
+#define VME_CTRL_VOWN		0x20
+#define VME_CTRL_A16_REG_MODE	0x40
+
+/* VME status register */
+
+#define VME_STATUS_SYSCON	0x01
+#define VME_STATUS_SYSFAIL	0x02
+#define VME_STATUS_ACFAIL	0x04
+#define VME_STATUS_SYSRST	0x08
+#define VME_STATUS_VOWN		0x10
+
+/* Interrupt types */
+
+#define LVL1			0x0002
+#define LVL2			0x0004
+#define LVL3			0x0008
+#define LVL4			0x0010
+#define LVL5			0x0020
+#define LVL6			0x0040
+#define LVL7			0x0080
+#define MULTIVERSE_INTI_INT	0x0100
+#define MULTIVERSE_WB_INT	0x0200
+#define MULTIVERSE_PCI_INT	0x0400
+
+/* interrupt acknowledge */
+
+#define VME_IACK1		0x04
+#define VME_IACK2		0x08
+#define VME_IACK3		0x0c
+#define VME_IACK4		0x10
+#define VME_IACK5		0x14
+#define VME_IACK6		0x18
+#define VME_IACK7		0x1c
+
+#endif /* __MULTIVERSE_H__ */