Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

6 files changed, 0 insertions, 487 deletions

diff --git a/qemu/roms/u-boot/board/amcc/luan/Makefile b/qemu/roms/u-boot/board/amcc/luan/Makefile
deleted file mode 100644
index 345ad564d..000000000
--- a/qemu/roms/u-boot/board/amcc/luan/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= luan.o flash.o
-extra-y	+= init.o
diff --git a/qemu/roms/u-boot/board/amcc/luan/config.mk b/qemu/roms/u-boot/board/amcc/luan/config.mk
deleted file mode 100644
index f18b09710..000000000
--- a/qemu/roms/u-boot/board/amcc/luan/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/qemu/roms/u-boot/board/amcc/luan/epld.h b/qemu/roms/u-boot/board/amcc/luan/epld.h
deleted file mode 100644
index 569d78c46..000000000
--- a/qemu/roms/u-boot/board/amcc/luan/epld.h
+++ /dev/null
@@ -1,85 +0,0 @@
-#define EPLD0_FSEL_FB2		0x80
-#define EPLD0_BOOT_SMALL_FLASH	0x40	/* 0 boot from large flash, 1 from small flash */
-#define EPLD0_RAW_CARD_BIT0	0x20	/* raw card EC level */
-#define EPLD0_RAW_CARD_BIT1	0x10
-#define EPLD0_RAW_CARD_BIT2	0x08
-#define EPLD0_EXT_ARB_SEL_N	0x04	/* 0 select on-board ext PCI-X, 1 internal arbiter */
-#define EPLD0_FLASH_ONBRD_N	0x02	/* 0 small flash/SRAM active, 1 block access */
-#define EPLD0_FLASH_SRAM_SEL_N	0x01	/* 0 SRAM at mem top, 1 small flash at mem top */
-
-#define EPLD1_CLK_CNTL0		0x80	/* FSEL-FB1 of MPC9772 */
-#define EPLD1_PCIL0_CNTL1	0x40	/* S*0 of 9531 */
-#define EPLD1_PCIL0_CNTL2	0x20	/* S*1 of 9531 */
-#define EPLD1_CLK_CNTL3		0x10	/* FSEL-B1 of MPC9772 */
-#define EPLD1_CLK_CNTL4		0x08	/* FSEL-B0 of MPC9772 */
-#define EPLD1_MASTER_CLOCK6	0x04	/* clock source select 6 */
-#define EPLD1_MASTER_CLOCK7	0x02	/* clock source select 7 */
-#define EPLD1_MASTER_CLOCK8	0x01	/* clock source select 8 */
-
-#define EPLD2_ETH_MODE_10	0x80	/* Ethernet mode 10   (default = 1) */
-#define EPLD2_ETH_MODE_100	0x40	/* Ethernet mode 100  (default = 1) */
-#define EPLD2_ETH_MODE_1000	0x20	/* Ethernet mode 1000 (default = 1) */
-#define EPLD2_ETH_DUPLEX_MODE	0x10	/* Ethernet force full duplex mode */
-#define EPLD2_RESET_ETH_N	0x08	/* Ethernet reset (default = 1) */
-#define EPLD2_ETH_AUTO_NEGO	0x04	/* Ethernet auto negotiation */
-#define EPLD2_DEFAULT_UART_N	0x01	/* 0 select DSR DTR for UART1 */
-
-#define EPLD3_STATUS_LED4	0x08	/* status LED 8 (1 = LED on) */
-#define EPLD3_STATUS_LED3	0x04	/* status LED 4 (1 = LED on) */
-#define EPLD3_STATUS_LED2	0x02	/* status LED 2 (1 = LED on) */
-#define EPLD3_STATUS_LED1	0x01	/* status LED 1 (1 = LED on) */
-
-#define EPLD4_PCIL0_VTH1	0x80	/* PCI-X 0 VTH1 status */
-#define EPLD4_PCIL0_VTH2	0x40	/* PCI-X 0 VTH2 status */
-#define EPLD4_PCIL0_VTH3	0x20	/* PCI-X 0 VTH3 status */
-#define EPLD4_PCIL0_VTH4	0x10	/* PCI-X 0 VTH4 status */
-#define EPLD4_PCIX1_VTH1	0x08	/* PCI-X 1 VTH1 status */
-#define EPLD4_PCIX1_VTH2	0x04	/* PCI-X 1 VTH2 status */
-#define EPLD4_PCIX1_VTH3	0x02	/* PCI-X 1 VTH3 status */
-#define EPLD4_PCIX1_VTH4	0x01	/* PCI-X 1 VTH4 status */
-
-#define EPLD5_PCIL0_INT0	0x80	/* PCIX0 INT0 status, write 0 to reset */
-#define EPLD5_PCIL0_INT1	0x40	/* PCIX0 INT1 status, write 0 to reset */
-#define EPLD5_PCIL0_INT2	0x20	/* PCIX0 INT2 status, write 0 to reset */
-#define EPLD5_PCIL0_INT3	0x10	/* PCIX0 INT3 status, write 0 to reset */
-#define EPLD5_PCIX1_INT0	0x08	/* PCIX1 INT0 status, write 0 to reset */
-#define EPLD5_PCIX1_INT1	0x04	/* PCIX1 INT1 status, write 0 to reset */
-#define EPLD5_PCIX1_INT2	0x02	/* PCIX1 INT2 status, write 0 to reset */
-#define EPLD5_PCIX1_INT3	0x01	/* PCIX1 INT3 status, write 0 to reset */
-
-#define EPLD6_PCIL0_RESET_CTL	0x80	/* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_PCIX1_RESET_CTL	0x40	/* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_ETH_INT_MODE	0x20	/* 0=IRQ5 recv's external eth int */
-#define EPLD6_PCIX2_RESET_CTL	0x10	/* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_PCI1_CLKCNTL1	0x80	/* PCI1 clock control S*0 of 9531 */
-#define EPLD6_PCI1_CLKCNTL2	0x40	/* PCI1 clock control S*1 of 9531 */
-#define EPLD6_PCI2_CLKCNTL1	0x20	/* PCI2 clock control S*0 of 9531 */
-#define EPLD6_PCI2_CLKCNTL2	0x10	/* PCI2 clock control S*1 of 9531 */
-
-#define EPLD7_VTH1		0x80	/* PCI2 VTH1 status */
-#define EPLD7_VTH2		0x40	/* PCI2 VTH2 status */
-#define EPLD7_VTH3		0x20	/* PCI2 VTH3 status */
-#define EPLD7_VTH4		0x10	/* PCI2 VTH4 status */
-#define EPLD7_INTA_MODE		0x80	/* see S5 on SW2 for details */
-#define EPLD7_PCI_INT_MODE_N	0x40	/* see S1 on SW2 for details */
-#define EPLD7_WRITE_ENABLE_GPIO	0x20	/* see S2 on SW2 for details */
-#define EPLD7_WRITE_ENABLE_INT	0x10	/* see S3 on SW2 for details */
-
-
-typedef struct {
-    unsigned char  status;		/* misc status */
-    unsigned char  clock;		/* clock status, PCI-X clock control */
-    unsigned char  ethuart;		/* Ethernet, UART status */
-    unsigned char  leds;		/* LED register */
-    unsigned char  vth01;		/* PCI0, PCI1 VTH register */
-    unsigned char  pciints;		/* PCI0, PCI1 interrupts */
-    unsigned char  pci2;		/* PCI2 interrupts, clock control */
-    unsigned char  vth2;		/* PCI2 VTH register */
-    unsigned char  filler1[4096-8];
-    unsigned char  gpio00;		/* GPIO bits  0-7 */
-    unsigned char  gpio08;		/* GPIO bits  8-15 */
-    unsigned char  gpio16;		/* GPIO bits 16-23 */
-    unsigned char  gpio24;		/* GPIO bits 24-31 */
-    unsigned char  filler2[4096-4];
-    unsigned char  version;		/* EPLD version */
-} epld_t;
diff --git a/qemu/roms/u-boot/board/amcc/luan/flash.c b/qemu/roms/u-boot/board/amcc/luan/flash.c
deleted file mode 100644
index a242befb2..000000000
--- a/qemu/roms/u-boot/board/amcc/luan/flash.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif				/* DEBUG */
-
-static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
-	{0xff900000, 0xff980000, 0xffc00000},	/* 0:000: configuraton 3 */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-
-unsigned long flash_init(void)
-{
-	unsigned long total_b = 0;
-	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-	unsigned short index = 0;
-	int i;
-
-	/* read FPGA base register FPGA_REG0 */
-
-	DEBUGF("\n");
-	DEBUGF("FLASH: Index: %d\n", index);
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-
-		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0) {
-			continue;
-		}
-
-		/* call flash_get_size() to initialize sector address */
-		size_b[i] = flash_get_size((vu_long *)
-					   flash_addr_table[index][i],
-					   &flash_info[i]);
-		flash_info[i].size = size_b[i];
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-			       i, size_b[i], size_b[i] << 20);
-			flash_info[i].sector_count = -1;
-			flash_info[i].size = 0;
-		}
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[2]);
-#ifdef CONFIG_ENV_IS_IN_FLASH
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[2]);
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[2]);
-#endif
-
-		total_b += flash_info[i].size;
-	}
-
-	return total_b;
-}
diff --git a/qemu/roms/u-boot/board/amcc/luan/init.S b/qemu/roms/u-boot/board/amcc/luan/init.S
deleted file mode 100644
index 0f4a78e1e..000000000
--- a/qemu/roms/u-boot/board/amcc/luan/init.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
-
-	tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
-	tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
-	tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
-	tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
-	tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	/* internal ram (l2 cache) */
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
-
-	/* peripherals at f0000000 */
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
-
-	/* PCI */
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
-	tlbtab_end
diff --git a/qemu/roms/u-boot/board/amcc/luan/luan.c b/qemu/roms/u-boot/board/amcc/luan/luan.c
deleted file mode 100644
index 774671db4..000000000
--- a/qemu/roms/u-boot/board/amcc/luan/luan.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2005
- * John Otken, jotken@softadvances.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-isram.h>
-#include <spd_sdram.h>
-#include "epld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-/*************************************************************************
- *  int board_early_init_f()
- *
- ************************************************************************/
-int board_early_init_f(void)
-{
-	u32 mfr;
-
-	mtebc( PB0AP,  0x03800000 );	/* set chip selects */
-	mtebc( PB0CR,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
-	mtebc( PB1AP,  0x03800000 );
-	mtebc( PB1CR,  0xff018000 );	/* ebc0_b1cr, 1MB at 0xff000000 CS1 */
-	mtebc( PB2AP,  0x03800000 );
-	mtebc( PB2CR,  0xff838000 );	/* ebc0_b2cr, 2MB at 0xff800000 CS2 */
-
-	mtdcr( UIC1SR, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( UIC1ER, 0x00000000 );	/* disable all interrupts */
-	mtdcr( UIC1CR, 0x00000000 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( UIC1PR, 0x7fff83ff );	/* Set Interrupt Polarities */
-	mtdcr( UIC1TR, 0x001f8000 );	/* Set Interrupt Trigger Levels */
-	mtdcr( UIC1VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( UIC1SR, 0x00000000 );	/* clear all interrupts */
-	mtdcr( UIC1SR, 0xffffffff );
-
-	mtdcr( UIC0SR, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( UIC0ER, 0x00000000 );	/* disable all interrupts excepted cascade */
-	mtdcr( UIC0CR, 0x00000001 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( UIC0PR, 0xffffffff );	/* Set Interrupt Polarities */
-	mtdcr( UIC0TR, 0x01000004 );	/* Set Interrupt Trigger Levels */
-	mtdcr( UIC0VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( UIC0SR, 0x00000000 );	/* clear all interrupts */
-	mtdcr( UIC0SR, 0xffffffff );
-
-	mfsdr(SDR0_MFR, mfr);
-	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
-	mtsdr(SDR0_MFR, mfr);
-
-	return  0;
-}
-
-
-/*************************************************************************
- *  int misc_init_r()
- *
- ************************************************************************/
-int misc_init_r(void)
-{
-	volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
-
-	/* set modes of operation */
-	x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
-		EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
-	/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
-	x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
-
-	/* put Ethernet+PHY in reset */
-	x->ethuart &= ~EPLD2_RESET_ETH_N;
-	udelay(10000);
-	/* take Ethernet+PHY out of reset */
-	x->ethuart |= EPLD2_RESET_ETH_N;
-
-	return  0;
-}
-
-
-/*************************************************************************
- *  int checkboard()
- *
- ************************************************************************/
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Luan - AMCC PPC440SP Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return  0;
-}
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_clktr(u32 default_val) {
-	return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
-}
-
-/*************************************************************************
- *  hw_watchdog_reset
- *
- *	This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-}
-#endif
-
-
-/*************************************************************************
- *  int on_off()
- *
- ************************************************************************/
-static int on_off( const char *s )
-{
-	if (strcmp(s, "on") == 0) {
-		return  1;
-	} else if (strcmp(s, "off") == 0) {
-		return  0;
-	}
-	return  -1;
-}
-
-
-/*************************************************************************
- *  void l2cache_disable()
- *
- ************************************************************************/
-static void l2cache_disable(void)
-{
-	mtdcr( L2_CACHE_CFG, 0 );
-}
-
-
-/*************************************************************************
- *  void l2cache_enable()
- *
- ************************************************************************/
-static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
-{
-	mtdcr( L2_CACHE_CFG, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
-
-	mtdcr( L2_CACHE_ADDR, 0 );		/* set L2_ADDR with all zeros */
-
-	mtdcr( L2_CACHE_CMD, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
-
-	while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
-
-	mtdcr( L2_CACHE_CMD, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
-
-	mtdcr( L2_CACHE_CMD, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
-
-	mtdcr( L2_CACHE_SNP0, 0 );		/* snoop registers */
-	mtdcr( L2_CACHE_SNP1, 0 );
-
-	__asm__ volatile ("sync");		/* msync */
-
-	mtdcr( L2_CACHE_CFG, 0xe0000000 );	/* inst and data use L2 */
-
-	__asm__ volatile ("sync");
-}
-
-
-/*************************************************************************
- *  int l2cache_status()
- *
- ************************************************************************/
-static int l2cache_status(void)
-{
-	return  (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
-}
-
-
-/*************************************************************************
- *  int do_l2cache()
- *
- ************************************************************************/
-int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
-{
-	switch (argc) {
-	case 2:			/* on / off	*/
-		switch (on_off(argv[1])) {
-		case 0:	l2cache_disable();
-			break;
-		case 1:	l2cache_enable();
-			break;
-		}
-		/* FALL TROUGH */
-	case 1:			/* get status */
-		printf ("L2 Cache is %s\n",
-			l2cache_status() ? "ON" : "OFF");
-		return 0;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return  0;
-}
-
-
-U_BOOT_CMD(
-	l2cache,   2,   1,     do_l2cache,
-	"enable or disable L2 cache",
-	"[on, off]\n"
-	"    - enable or disable L2 cache"
-);