diff options
| author |   RajithaY <rajithax.yerrumsetty@intel.com> | 2017-04-25 03:31:15 -0700 |
|---|---|---|
| committer | Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> | 2017-05-22 06:48:08 +0000 |
| commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
| tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/arch/sh/include/asm/cpu_sh7734.h | |
| parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) | |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/sh/include/asm/cpu_sh7734.h')
| -rw-r--r-- | qemu/roms/u-boot/arch/sh/include/asm/cpu_sh7734.h | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/qemu/roms/u-boot/arch/sh/include/asm/cpu_sh7734.h b/qemu/roms/u-boot/arch/sh/include/asm/cpu_sh7734.h deleted file mode 100644 index 98fd61c21..000000000 --- a/qemu/roms/u-boot/arch/sh/include/asm/cpu_sh7734.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2008, 2011 Renesas Solutions Corp. - * - * SH7734 Internal I/O register - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_CPU_SH7734_H_ -#define _ASM_CPU_SH7734_H_ - -#define CCR 0xFF00001C - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000090d - -/* SCIF */ -#define SCIF0_BASE 0xFFE40000 -#define SCIF1_BASE 0xFFE41000 -#define SCIF2_BASE 0xFFE42000 -#define SCIF3_BASE 0xFFE43000 -#define SCIF4_BASE 0xFFE44000 -#define SCIF5_BASE 0xFFE45000 - -/* Timer */ -#define TMU_BASE 0xFFD80000 - -/* PFC */ -#define PMMR (0xFFFC0000) -#define MODESEL0 (0xFFFC004C) -#define MODESEL2 (MODESEL0 + 0x4) -#define MODESEL2_INIT (0x00003000) - -#define IPSR0 (0xFFFC001C) -#define IPSR1 (IPSR0 + 0x4) -#define IPSR2 (IPSR0 + 0x8) -#define IPSR3 (IPSR0 + 0xC) -#define IPSR4 (IPSR0 + 0x10) -#define IPSR5 (IPSR0 + 0x14) -#define IPSR6 (IPSR0 + 0x18) -#define IPSR7 (IPSR0 + 0x1C) -#define IPSR8 (IPSR0 + 0x20) -#define IPSR9 (IPSR0 + 0x24) -#define IPSR10 (IPSR0 + 0x28) -#define IPSR11 (IPSR0 + 0x2C) - -#define GPSR0 (0xFFFC0004) -#define GPSR1 (GPSR0 + 0x4) -#define GPSR2 (GPSR0 + 0x8) -#define GPSR3 (GPSR0 + 0xC) -#define GPSR4 (GPSR0 + 0x10) -#define GPSR5 (GPSR0 + 0x14) - - -#endif /* _ASM_CPU_SH7734_H_ */ |