diff options
author | 2015-08-28 09:58:54 +0800 | |
---|---|---|
committer | 2015-09-01 12:44:00 +0800 | |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/arch/powerpc/lib/ticks.S | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/powerpc/lib/ticks.S')
-rw-r--r-- | qemu/roms/u-boot/arch/powerpc/lib/ticks.S | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/arch/powerpc/lib/ticks.S b/qemu/roms/u-boot/arch/powerpc/lib/ticks.S new file mode 100644 index 000000000..0473a639e --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/lib/ticks.S @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2000, 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * base on code by + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <config.h> +#include <watchdog.h> + +/* + * unsigned long long get_ticks(void); + * + * read timebase as "long long" + */ + .globl get_ticks +get_ticks: +1: mftbu r3 + mftb r4 + mftbu r5 + cmp 0,r3,r5 + bne 1b + blr + +/* + * Delay for a number of ticks + */ + .globl wait_ticks +wait_ticks: + stwu r1, -16(r1) + mflr r0 /* save link register */ + stw r0, 20(r1) /* Use r0 or GDB will be unhappy */ + stw r14, 12(r1) /* save used registers */ + stw r15, 8(r1) + mr r14, r3 /* save tick count */ + bl get_ticks /* Get start time */ + + /* Calculate end time */ + addc r14, r4, r14 /* Compute end time lower */ + addze r15, r3 /* and end time upper */ + + WATCHDOG_RESET /* Trigger watchdog, if needed */ +1: bl get_ticks /* Get current time */ + subfc r4, r4, r14 /* Subtract current time from end time */ + subfe. r3, r3, r15 + bge 1b /* Loop until time expired */ + + lwz r15, 8(r1) /* restore saved registers */ + lwz r14, 12(r1) + lwz r0, 20(r1) + addi r1,r1,16 + mtlr r0 + blr |